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25 #define IVTV_IRQ_ENC_START_CAP (0x1 << 31)
26 #define IVTV_IRQ_ENC_EOS (0x1 << 30)
27 #define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29)
28 #define IVTV_IRQ_ENC_VIM_RST (0x1 << 28)
29 #define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27)
30 #define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25)
31 #define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24)
32 #define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22)
33 #define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20)
34 #define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19)
35 #define IVTV_IRQ_DMA_ERR (0x1 << 18)
36 #define IVTV_IRQ_DMA_WRITE (0x1 << 17)
37 #define IVTV_IRQ_DMA_READ (0x1 << 16)
38 #define IVTV_IRQ_DEC_VSYNC (0x1 << 10)
41 #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\
42 IVTV_IRQ_DMA_READ|IVTV_IRQ_ENC_PIO_COMPLETE)
44 #define IVTV_IRQ_MASK_CAPTURE (IVTV_IRQ_ENC_START_CAP | IVTV_IRQ_ENC_EOS)
45 #define IVTV_IRQ_MASK_DECODE (IVTV_IRQ_DEC_DATA_REQ|IVTV_IRQ_DEC_AUD_MODE_CHG)