iwl-prph.h

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/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <[email protected]>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
 * All rights reserved.
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 * modification, are permitted provided that the following conditions
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 *****************************************************************************/

#ifndef __iwl_prph_h__
#define __iwl_prph_h__

/*
 * Registers in this file are internal, not PCI bus memory mapped.
 * Driver accesses these via HBUS_TARG_PRPH_* registers.
 */
#define PRPH_BASE   (0x00000)
#define PRPH_END    (0xFFFFF)

/* APMG (power management) constants */
#define APMG_BASE           (PRPH_BASE + 0x3000)
#define APMG_CLK_CTRL_REG       (APMG_BASE + 0x0000)
#define APMG_CLK_EN_REG         (APMG_BASE + 0x0004)
#define APMG_CLK_DIS_REG        (APMG_BASE + 0x0008)
#define APMG_PS_CTRL_REG        (APMG_BASE + 0x000c)
#define APMG_PCIDEV_STT_REG     (APMG_BASE + 0x0010)
#define APMG_RFKILL_REG         (APMG_BASE + 0x0014)
#define APMG_RTC_INT_STT_REG        (APMG_BASE + 0x001c)
#define APMG_RTC_INT_MSK_REG        (APMG_BASE + 0x0020)
#define APMG_DIGITAL_SVR_REG        (APMG_BASE + 0x0058)
#define APMG_ANALOG_SVR_REG     (APMG_BASE + 0x006C)

#define APMS_CLK_VAL_MRB_FUNC_MODE  (0x00000001)
#define APMG_CLK_VAL_DMA_CLK_RQT    (0x00000200)
#define APMG_CLK_VAL_BSM_CLK_RQT    (0x00000800)

#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS    (0x00400000)
#define APMG_PS_CTRL_VAL_RESET_REQ      (0x04000000)
#define APMG_PS_CTRL_MSK_PWR_SRC        (0x03000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN      (0x00000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX       (0x02000000)
#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
#define APMG_SVR_DIGITAL_VOLTAGE_1_32       (0x00000060)

#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS      (0x00000800)

#define SCD_MEM_LOWER_BOUND     (0x0000)

#define SCD_WIN_SIZE                64
#define SCD_FRAME_LIMIT             64

#define SCD_TXFIFO_POS_TID          (0)
#define SCD_TXFIFO_POS_RA           (4)
#define SCD_QUEUE_RA_TID_MAP_RATID_MSK  (0x01FF)

/* agn SCD */
#define SCD_QUEUE_STTS_REG_POS_TXF  (0)
#define SCD_QUEUE_STTS_REG_POS_ACTIVE   (3)
#define SCD_QUEUE_STTS_REG_POS_WSL  (4)
#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
#define SCD_QUEUE_STTS_REG_MSK      (0x017F0000)

#define SCD_QUEUE_CTX_REG1_CREDIT_POS       (8)
#define SCD_QUEUE_CTX_REG1_CREDIT_MSK       (0x00FFFF00)
#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
#define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS     (0)
#define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK     (0x0000007F)
#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS  (16)
#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK  (0x007F0000)

/* Context Data */
#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)

/* Tx status */
#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)

/* Translation Data */
#define SCD_TRANS_TBL_MEM_LOWER_BOUND   (SCD_MEM_LOWER_BOUND + 0x7E0)
#define SCD_TRANS_TBL_MEM_UPPER_BOUND   (SCD_MEM_LOWER_BOUND + 0x808)

#define SCD_CONTEXT_QUEUE_OFFSET(x)\
    (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))

#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
    ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)

#define SCD_BASE            (PRPH_BASE + 0xa02c00)

#define SCD_SRAM_BASE_ADDR  (SCD_BASE + 0x0)
#define SCD_DRAM_BASE_ADDR  (SCD_BASE + 0x8)
#define SCD_AIT         (SCD_BASE + 0x0c)
#define SCD_TXFACT      (SCD_BASE + 0x10)
#define SCD_ACTIVE      (SCD_BASE + 0x14)
#define SCD_QUEUECHAIN_SEL  (SCD_BASE + 0xe8)
#define SCD_CHAINEXT_EN     (SCD_BASE + 0x244)
#define SCD_AGGR_SEL        (SCD_BASE + 0x248)
#define SCD_INTERRUPT_MASK  (SCD_BASE + 0x108)

static inline unsigned int SCD_QUEUE_WRPTR(unsigned int chnl)
{
    if (chnl < 20)
        return SCD_BASE + 0x18 + chnl * 4;
    WARN_ON_ONCE(chnl >= 32);
    return SCD_BASE + 0x284 + (chnl - 20) * 4;
}

static inline unsigned int SCD_QUEUE_RDPTR(unsigned int chnl)
{
    if (chnl < 20)
        return SCD_BASE + 0x68 + chnl * 4;
    WARN_ON_ONCE(chnl >= 32);
    return SCD_BASE + 0x2B4 + (chnl - 20) * 4;
}

static inline unsigned int SCD_QUEUE_STATUS_BITS(unsigned int chnl)
{
    if (chnl < 20)
        return SCD_BASE + 0x10c + chnl * 4;
    WARN_ON_ONCE(chnl >= 32);
    return SCD_BASE + 0x384 + (chnl - 20) * 4;
}

/*********************** END TX SCHEDULER *************************************/

#endif              /* __iwl_prph_h__ */