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jme.h
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1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <[email protected]>
7  *
8  * Author: Guo-Fu Tseng <[email protected]>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  *
23  */
24 
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
27 #include <linux/interrupt.h>
28 
29 #define DRV_NAME "jme"
30 #define DRV_VERSION "1.0.8"
31 #define PFX DRV_NAME ": "
32 
33 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35 
36 /*
37  * Message related definitions
38  */
39 #define JME_DEF_MSG_ENABLE \
40  (NETIF_MSG_PROBE | \
41  NETIF_MSG_LINK | \
42  NETIF_MSG_RX_ERR | \
43  NETIF_MSG_TX_ERR | \
44  NETIF_MSG_HW)
45 
46 #ifdef TX_DEBUG
47 #define tx_dbg(priv, fmt, args...) \
48  printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
49 #else
50 #define tx_dbg(priv, fmt, args...) \
51 do { \
52  if (0) \
53  printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
54 } while (0)
55 #endif
56 
57 /*
58  * Extra PCI Configuration space interface
59  */
60 #define PCI_DCSR_MRRS 0x59
61 #define PCI_DCSR_MRRS_MASK 0x70
62 
63 enum pci_dcsr_mrrs_vals {
64  MRRS_128B = 0x00,
65  MRRS_256B = 0x10,
66  MRRS_512B = 0x20,
67  MRRS_1024B = 0x30,
68  MRRS_2048B = 0x40,
69  MRRS_4096B = 0x50,
70 };
71 
72 #define PCI_SPI 0xB0
73 
74 enum pci_spi_bits {
75  SPI_EN = 0x10,
76  SPI_MISO = 0x08,
77  SPI_MOSI = 0x04,
78  SPI_SCLK = 0x02,
79  SPI_CS = 0x01,
80 };
81 
82 struct jme_spi_op {
83  void __user *uwbuf;
84  void __user *urbuf;
85  __u8 wn; /* Number of write actions */
86  __u8 rn; /* Number of read actions */
87  __u8 bitn; /* Number of bits per action */
88  __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
89  __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
90 
91  /* Internal use only */
92  u8 *kwbuf;
93  u8 *krbuf;
94  u8 sr;
95  u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
96 };
97 
98 enum jme_spi_op_bits {
99  SPI_MODE_CPHA = 0x01,
100  SPI_MODE_CPOL = 0x02,
101  SPI_MODE_DUP = 0x80,
102 };
103 
104 #define HALF_US 500 /* 500 ns */
105 
106 #define PCI_PRIV_PE1 0xE4
107 
108 enum pci_priv_pe1_bit_masks {
109  PE1_ASPMSUPRT = 0x00000003, /*
110  * RW:
111  * Aspm_support[1:0]
112  * (R/W Port of 5C[11:10])
113  */
114  PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
115  PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
116  PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
117  PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
118  PE1_GPREG0 = 0x0000FF00, /*
119  * SRW:
120  * Cfg_gp_reg0
121  * [7:6] phy_giga BG control
122  * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
123  * [4:0] Reserved
124  */
125  PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
126  PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
127  PE1_REVID = 0xFF000000, /* RO: Rev ID */
128 };
129 
130 enum pci_priv_pe1_values {
131  PE1_GPREG0_ENBG = 0x00000000, /* en BG */
132  PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
133  PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
134  PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
135 };
136 
137 /*
138  * Dynamic(adaptive)/Static PCC values
139  */
140 enum dynamic_pcc_values {
141  PCC_OFF = 0,
142  PCC_P1 = 1,
143  PCC_P2 = 2,
144  PCC_P3 = 3,
145 
146  PCC_OFF_TO = 0,
147  PCC_P1_TO = 1,
148  PCC_P2_TO = 64,
149  PCC_P3_TO = 128,
150 
151  PCC_OFF_CNT = 0,
152  PCC_P1_CNT = 1,
153  PCC_P2_CNT = 16,
154  PCC_P3_CNT = 32,
155 };
156 struct dynpcc_info {
157  unsigned long last_bytes;
158  unsigned long last_pkts;
159  unsigned long intr_cnt;
160  unsigned char cur;
161  unsigned char attempt;
162  unsigned char cnt;
163 };
164 #define PCC_INTERVAL_US 100000
165 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
166 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
167 #define PCC_P2_THRESHOLD 800
168 #define PCC_INTR_THRESHOLD 800
169 #define PCC_TX_TO 1000
170 #define PCC_TX_CNT 8
171 
172 /*
173  * TX/RX Descriptors
174  *
175  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
176  */
177 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
178 #define TX_DESC_SIZE 16
179 #define TX_RING_NR 8
180 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
181 
182 struct txdesc {
183  union {
184  __u8 all[16];
185  __le32 dw[4];
186  struct {
187  /* DW0 */
188  __le16 vlan;
189  __u8 rsv1;
190  __u8 flags;
191 
192  /* DW1 */
193  __le16 datalen;
194  __le16 mss;
195 
196  /* DW2 */
197  __le16 pktsize;
198  __le16 rsv2;
199 
200  /* DW3 */
201  __le32 bufaddr;
202  } desc1;
203  struct {
204  /* DW0 */
205  __le16 rsv1;
206  __u8 rsv2;
207  __u8 flags;
208 
209  /* DW1 */
210  __le16 datalen;
211  __le16 rsv3;
212 
213  /* DW2 */
214  __le32 bufaddrh;
215 
216  /* DW3 */
217  __le32 bufaddrl;
218  } desc2;
219  struct {
220  /* DW0 */
221  __u8 ehdrsz;
222  __u8 rsv1;
223  __u8 rsv2;
224  __u8 flags;
225 
226  /* DW1 */
227  __le16 trycnt;
228  __le16 segcnt;
229 
230  /* DW2 */
231  __le16 pktsz;
232  __le16 rsv3;
233 
234  /* DW3 */
235  __le32 bufaddrl;
236  } descwb;
237  };
238 };
239 
240 enum jme_txdesc_flags_bits {
241  TXFLAG_OWN = 0x80,
242  TXFLAG_INT = 0x40,
243  TXFLAG_64BIT = 0x20,
244  TXFLAG_TCPCS = 0x10,
245  TXFLAG_UDPCS = 0x08,
246  TXFLAG_IPCS = 0x04,
247  TXFLAG_LSEN = 0x02,
248  TXFLAG_TAGON = 0x01,
249 };
250 
251 #define TXDESC_MSS_SHIFT 2
252 enum jme_txwbdesc_flags_bits {
253  TXWBFLAG_OWN = 0x80,
254  TXWBFLAG_INT = 0x40,
255  TXWBFLAG_TMOUT = 0x20,
256  TXWBFLAG_TRYOUT = 0x10,
257  TXWBFLAG_COL = 0x08,
258 
259  TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
260  TXWBFLAG_TRYOUT |
261  TXWBFLAG_COL,
262 };
263 
264 #define RX_DESC_SIZE 16
265 #define RX_RING_NR 4
266 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
267 #define RX_BUF_DMA_ALIGN 8
268 #define RX_PREPAD_SIZE 10
269 #define ETH_CRC_LEN 2
270 #define RX_VLANHDR_LEN 2
271 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
272  ETH_HLEN + \
273  ETH_CRC_LEN + \
274  RX_VLANHDR_LEN + \
275  RX_BUF_DMA_ALIGN)
276 
277 struct rxdesc {
278  union {
279  __u8 all[16];
280  __le32 dw[4];
281  struct {
282  /* DW0 */
283  __le16 rsv2;
284  __u8 rsv1;
285  __u8 flags;
286 
287  /* DW1 */
288  __le16 datalen;
289  __le16 wbcpl;
290 
291  /* DW2 */
292  __le32 bufaddrh;
293 
294  /* DW3 */
295  __le32 bufaddrl;
296  } desc1;
297  struct {
298  /* DW0 */
299  __le16 vlan;
300  __le16 flags;
301 
302  /* DW1 */
303  __le16 framesize;
304  __u8 errstat;
305  __u8 desccnt;
306 
307  /* DW2 */
308  __le32 rsshash;
309 
310  /* DW3 */
311  __u8 hashfun;
312  __u8 hashtype;
313  __le16 resrv;
314  } descwb;
315  };
316 };
317 
318 enum jme_rxdesc_flags_bits {
319  RXFLAG_OWN = 0x80,
320  RXFLAG_INT = 0x40,
321  RXFLAG_64BIT = 0x20,
322 };
323 
324 enum jme_rxwbdesc_flags_bits {
325  RXWBFLAG_OWN = 0x8000,
326  RXWBFLAG_INT = 0x4000,
327  RXWBFLAG_MF = 0x2000,
328  RXWBFLAG_64BIT = 0x2000,
329  RXWBFLAG_TCPON = 0x1000,
330  RXWBFLAG_UDPON = 0x0800,
331  RXWBFLAG_IPCS = 0x0400,
332  RXWBFLAG_TCPCS = 0x0200,
333  RXWBFLAG_UDPCS = 0x0100,
334  RXWBFLAG_TAGON = 0x0080,
335  RXWBFLAG_IPV4 = 0x0040,
336  RXWBFLAG_IPV6 = 0x0020,
337  RXWBFLAG_PAUSE = 0x0010,
338  RXWBFLAG_MAGIC = 0x0008,
339  RXWBFLAG_WAKEUP = 0x0004,
340  RXWBFLAG_DEST = 0x0003,
341  RXWBFLAG_DEST_UNI = 0x0001,
342  RXWBFLAG_DEST_MUL = 0x0002,
343  RXWBFLAG_DEST_BRO = 0x0003,
344 };
345 
346 enum jme_rxwbdesc_desccnt_mask {
347  RXWBDCNT_WBCPL = 0x80,
348  RXWBDCNT_DCNT = 0x7F,
349 };
350 
351 enum jme_rxwbdesc_errstat_bits {
352  RXWBERR_LIMIT = 0x80,
353  RXWBERR_MIIER = 0x40,
354  RXWBERR_NIBON = 0x20,
355  RXWBERR_COLON = 0x10,
356  RXWBERR_ABORT = 0x08,
357  RXWBERR_SHORT = 0x04,
358  RXWBERR_OVERUN = 0x02,
359  RXWBERR_CRCERR = 0x01,
360  RXWBERR_ALLERR = 0xFF,
361 };
362 
363 /*
364  * Buffer information corresponding to ring descriptors.
365  */
366 struct jme_buffer_info {
367  struct sk_buff *skb;
368  dma_addr_t mapping;
369  int len;
370  int nr_desc;
371  unsigned long start_xmit;
372 };
373 
374 /*
375  * The structure holding buffer information and ring descriptors all together.
376  */
377 struct jme_ring {
378  void *alloc; /* pointer to allocated memory */
379  void *desc; /* pointer to ring memory */
380  dma_addr_t dmaalloc; /* phys address of ring alloc */
381  dma_addr_t dma; /* phys address for ring dma */
382 
383  /* Buffer information corresponding to each descriptor */
384  struct jme_buffer_info *bufinf;
385 
386  int next_to_use;
387  atomic_t next_to_clean;
388  atomic_t nr_free;
389 };
390 
391 #define NET_STAT(priv) (priv->dev->stats)
392 #define NETDEV_GET_STATS(netdev, fun_ptr)
393 #define DECLARE_NET_DEVICE_STATS
394 
395 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
396 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
397  netif_napi_add(dev, napis, pollfn, q);
398 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
399 #define JME_NAPI_WEIGHT(w) int w
400 #define JME_NAPI_WEIGHT_VAL(w) w
401 #define JME_NAPI_WEIGHT_SET(w, r)
402 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
403 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
404 #define JME_NAPI_DISABLE(priv) \
405  if (!napi_disable_pending(&priv->napi)) \
406  napi_disable(&priv->napi);
407 #define JME_RX_SCHEDULE_PREP(priv) \
408  napi_schedule_prep(&priv->napi)
409 #define JME_RX_SCHEDULE(priv) \
410  __napi_schedule(&priv->napi);
411 
412 /*
413  * Jmac Adapter Private data
414  */
415 struct jme_adapter {
416  struct pci_dev *pdev;
417  struct net_device *dev;
418  void __iomem *regs;
419  struct mii_if_info mii_if;
420  struct jme_ring rxring[RX_RING_NR];
421  struct jme_ring txring[TX_RING_NR];
422  spinlock_t phy_lock;
423  spinlock_t macaddr_lock;
424  spinlock_t rxmcs_lock;
425  struct tasklet_struct rxempty_task;
426  struct tasklet_struct rxclean_task;
427  struct tasklet_struct txclean_task;
428  struct tasklet_struct linkch_task;
429  struct tasklet_struct pcc_task;
430  unsigned long flags;
431  u32 reg_txcs;
432  u32 reg_txpfc;
433  u32 reg_rxcs;
434  u32 reg_rxmcs;
435  u32 reg_ghc;
436  u32 reg_pmcs;
437  u32 reg_gpreg1;
438  u32 phylink;
439  u32 tx_ring_size;
440  u32 tx_ring_mask;
441  u32 tx_wake_threshold;
442  u32 rx_ring_size;
443  u32 rx_ring_mask;
444  u8 mrrs;
445  unsigned int fpgaver;
446  u8 chiprev;
447  u8 chip_main_rev;
448  u8 chip_sub_rev;
449  u8 pcirev;
450  u32 msg_enable;
451  struct ethtool_cmd old_ecmd;
452  unsigned int old_mtu;
453  struct dynpcc_info dpi;
454  atomic_t intr_sem;
455  atomic_t link_changing;
456  atomic_t tx_cleaning;
457  atomic_t rx_cleaning;
458  atomic_t rx_empty;
459  int (*jme_rx)(struct sk_buff *skb);
460  DECLARE_NAPI_STRUCT
461  DECLARE_NET_DEVICE_STATS
462 };
463 
464 enum jme_flags_bits {
465  JME_FLAG_MSI = 1,
466  JME_FLAG_SSET = 2,
467  JME_FLAG_POLL = 5,
468  JME_FLAG_SHUTDOWN = 6,
469 };
470 
471 #define TX_TIMEOUT (5 * HZ)
472 #define JME_REG_LEN 0x500
473 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
474 
475 static inline struct jme_adapter*
476 jme_napi_priv(struct napi_struct *napi)
477 {
478  struct jme_adapter *jme;
479  jme = container_of(napi, struct jme_adapter, napi);
480  return jme;
481 }
482 
483 /*
484  * MMaped I/O Resters
485  */
486 enum jme_iomap_offsets {
487  JME_MAC = 0x0000,
488  JME_PHY = 0x0400,
489  JME_MISC = 0x0800,
490  JME_RSS = 0x0C00,
491 };
492 
493 enum jme_iomap_lens {
494  JME_MAC_LEN = 0x80,
495  JME_PHY_LEN = 0x58,
496  JME_MISC_LEN = 0x98,
497  JME_RSS_LEN = 0xFF,
498 };
499 
500 enum jme_iomap_regs {
501  JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
502  JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
503  JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
504  JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
505  JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
506  JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
507  JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
508  JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
509 
510  JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
511  JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
512  JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
513  JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
514  JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
515  JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
516  JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
517  JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
518  JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
519  JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
520  JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
521  JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
522 
523  JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
524  JME_GHC = JME_MAC | 0x54, /* Global Host Control */
525  JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
526 
527 
528  JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
529  JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
530  JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
531  JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
532  JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
533 
534 
535  JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
536  JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
537  JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
538  JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
539  JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
540  JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
541  JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
542  JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
543  JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
544  JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
545  JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
546  JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
547  JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
548  JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
549  JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
550  JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
551 };
552 
553 /*
554  * TX Control/Status Bits
555  */
556 enum jme_txcs_bits {
557  TXCS_QUEUE7S = 0x00008000,
558  TXCS_QUEUE6S = 0x00004000,
559  TXCS_QUEUE5S = 0x00002000,
560  TXCS_QUEUE4S = 0x00001000,
561  TXCS_QUEUE3S = 0x00000800,
562  TXCS_QUEUE2S = 0x00000400,
563  TXCS_QUEUE1S = 0x00000200,
564  TXCS_QUEUE0S = 0x00000100,
565  TXCS_FIFOTH = 0x000000C0,
566  TXCS_DMASIZE = 0x00000030,
567  TXCS_BURST = 0x00000004,
568  TXCS_ENABLE = 0x00000001,
569 };
570 
571 enum jme_txcs_value {
572  TXCS_FIFOTH_16QW = 0x000000C0,
573  TXCS_FIFOTH_12QW = 0x00000080,
574  TXCS_FIFOTH_8QW = 0x00000040,
575  TXCS_FIFOTH_4QW = 0x00000000,
576 
577  TXCS_DMASIZE_64B = 0x00000000,
578  TXCS_DMASIZE_128B = 0x00000010,
579  TXCS_DMASIZE_256B = 0x00000020,
580  TXCS_DMASIZE_512B = 0x00000030,
581 
582  TXCS_SELECT_QUEUE0 = 0x00000000,
583  TXCS_SELECT_QUEUE1 = 0x00010000,
584  TXCS_SELECT_QUEUE2 = 0x00020000,
585  TXCS_SELECT_QUEUE3 = 0x00030000,
586  TXCS_SELECT_QUEUE4 = 0x00040000,
587  TXCS_SELECT_QUEUE5 = 0x00050000,
588  TXCS_SELECT_QUEUE6 = 0x00060000,
589  TXCS_SELECT_QUEUE7 = 0x00070000,
590 
591  TXCS_DEFAULT = TXCS_FIFOTH_4QW |
592  TXCS_BURST,
593 };
594 
595 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
596 
597 /*
598  * TX MAC Control/Status Bits
599  */
600 enum jme_txmcs_bit_masks {
601  TXMCS_IFG2 = 0xC0000000,
602  TXMCS_IFG1 = 0x30000000,
603  TXMCS_TTHOLD = 0x00000300,
604  TXMCS_FBURST = 0x00000080,
605  TXMCS_CARRIEREXT = 0x00000040,
606  TXMCS_DEFER = 0x00000020,
607  TXMCS_BACKOFF = 0x00000010,
608  TXMCS_CARRIERSENSE = 0x00000008,
609  TXMCS_COLLISION = 0x00000004,
610  TXMCS_CRC = 0x00000002,
611  TXMCS_PADDING = 0x00000001,
612 };
613 
614 enum jme_txmcs_values {
615  TXMCS_IFG2_6_4 = 0x00000000,
616  TXMCS_IFG2_8_5 = 0x40000000,
617  TXMCS_IFG2_10_6 = 0x80000000,
618  TXMCS_IFG2_12_7 = 0xC0000000,
619 
620  TXMCS_IFG1_8_4 = 0x00000000,
621  TXMCS_IFG1_12_6 = 0x10000000,
622  TXMCS_IFG1_16_8 = 0x20000000,
623  TXMCS_IFG1_20_10 = 0x30000000,
624 
625  TXMCS_TTHOLD_1_8 = 0x00000000,
626  TXMCS_TTHOLD_1_4 = 0x00000100,
627  TXMCS_TTHOLD_1_2 = 0x00000200,
628  TXMCS_TTHOLD_FULL = 0x00000300,
629 
630  TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
631  TXMCS_IFG1_16_8 |
632  TXMCS_TTHOLD_FULL |
633  TXMCS_DEFER |
634  TXMCS_CRC |
635  TXMCS_PADDING,
636 };
637 
638 enum jme_txpfc_bits_masks {
639  TXPFC_VLAN_TAG = 0xFFFF0000,
640  TXPFC_VLAN_EN = 0x00008000,
641  TXPFC_PF_EN = 0x00000001,
642 };
643 
644 enum jme_txtrhd_bits_masks {
645  TXTRHD_TXPEN = 0x80000000,
646  TXTRHD_TXP = 0x7FFFFF00,
647  TXTRHD_TXREN = 0x00000080,
648  TXTRHD_TXRL = 0x0000007F,
649 };
650 
651 enum jme_txtrhd_shifts {
652  TXTRHD_TXP_SHIFT = 8,
653  TXTRHD_TXRL_SHIFT = 0,
654 };
655 
656 enum jme_txtrhd_values {
657  TXTRHD_FULLDUPLEX = 0x00000000,
658  TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
659  ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
660  TXTRHD_TXREN |
661  ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
662 };
663 
664 /*
665  * RX Control/Status Bits
666  */
667 enum jme_rxcs_bit_masks {
668  /* FIFO full threshold for transmitting Tx Pause Packet */
669  RXCS_FIFOTHTP = 0x30000000,
670  /* FIFO threshold for processing next packet */
671  RXCS_FIFOTHNP = 0x0C000000,
672  RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
673  RXCS_QUEUESEL = 0x00030000, /* Queue selection */
674  RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
675  RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
676  RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
677  RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
678  RXCS_SHORT = 0x00000010, /* Enable receive short packet */
679  RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
680  RXCS_QST = 0x00000004, /* Receive queue start */
681  RXCS_SUSPEND = 0x00000002,
682  RXCS_ENABLE = 0x00000001,
683 };
684 
685 enum jme_rxcs_values {
686  RXCS_FIFOTHTP_16T = 0x00000000,
687  RXCS_FIFOTHTP_32T = 0x10000000,
688  RXCS_FIFOTHTP_64T = 0x20000000,
689  RXCS_FIFOTHTP_128T = 0x30000000,
690 
691  RXCS_FIFOTHNP_16QW = 0x00000000,
692  RXCS_FIFOTHNP_32QW = 0x04000000,
693  RXCS_FIFOTHNP_64QW = 0x08000000,
694  RXCS_FIFOTHNP_128QW = 0x0C000000,
695 
696  RXCS_DMAREQSZ_16B = 0x00000000,
697  RXCS_DMAREQSZ_32B = 0x01000000,
698  RXCS_DMAREQSZ_64B = 0x02000000,
699  RXCS_DMAREQSZ_128B = 0x03000000,
700 
701  RXCS_QUEUESEL_Q0 = 0x00000000,
702  RXCS_QUEUESEL_Q1 = 0x00010000,
703  RXCS_QUEUESEL_Q2 = 0x00020000,
704  RXCS_QUEUESEL_Q3 = 0x00030000,
705 
706  RXCS_RETRYGAP_256ns = 0x00000000,
707  RXCS_RETRYGAP_512ns = 0x00001000,
708  RXCS_RETRYGAP_1024ns = 0x00002000,
709  RXCS_RETRYGAP_2048ns = 0x00003000,
710  RXCS_RETRYGAP_4096ns = 0x00004000,
711  RXCS_RETRYGAP_8192ns = 0x00005000,
712  RXCS_RETRYGAP_16384ns = 0x00006000,
713  RXCS_RETRYGAP_32768ns = 0x00007000,
714 
715  RXCS_RETRYCNT_0 = 0x00000000,
716  RXCS_RETRYCNT_4 = 0x00000100,
717  RXCS_RETRYCNT_8 = 0x00000200,
718  RXCS_RETRYCNT_12 = 0x00000300,
719  RXCS_RETRYCNT_16 = 0x00000400,
720  RXCS_RETRYCNT_20 = 0x00000500,
721  RXCS_RETRYCNT_24 = 0x00000600,
722  RXCS_RETRYCNT_28 = 0x00000700,
723  RXCS_RETRYCNT_32 = 0x00000800,
724  RXCS_RETRYCNT_36 = 0x00000900,
725  RXCS_RETRYCNT_40 = 0x00000A00,
726  RXCS_RETRYCNT_44 = 0x00000B00,
727  RXCS_RETRYCNT_48 = 0x00000C00,
728  RXCS_RETRYCNT_52 = 0x00000D00,
729  RXCS_RETRYCNT_56 = 0x00000E00,
730  RXCS_RETRYCNT_60 = 0x00000F00,
731 
732  RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
733  RXCS_FIFOTHNP_16QW |
734  RXCS_DMAREQSZ_128B |
735  RXCS_RETRYGAP_256ns |
736  RXCS_RETRYCNT_32,
737 };
738 
739 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
740 
741 /*
742  * RX MAC Control/Status Bits
743  */
744 enum jme_rxmcs_bits {
745  RXMCS_ALLFRAME = 0x00000800,
746  RXMCS_BRDFRAME = 0x00000400,
747  RXMCS_MULFRAME = 0x00000200,
748  RXMCS_UNIFRAME = 0x00000100,
749  RXMCS_ALLMULFRAME = 0x00000080,
750  RXMCS_MULFILTERED = 0x00000040,
751  RXMCS_RXCOLLDEC = 0x00000020,
752  RXMCS_FLOWCTRL = 0x00000008,
753  RXMCS_VTAGRM = 0x00000004,
754  RXMCS_PREPAD = 0x00000002,
755  RXMCS_CHECKSUM = 0x00000001,
756 
757  RXMCS_DEFAULT = RXMCS_VTAGRM |
758  RXMCS_PREPAD |
759  RXMCS_FLOWCTRL |
760  RXMCS_CHECKSUM,
761 };
762 
763 /* Extern PHY common register 2 */
764 
765 #define PHY_GAD_TEST_MODE_1 0x00002000
766 #define PHY_GAD_TEST_MODE_MSK 0x0000E000
767 #define JM_PHY_SPEC_REG_READ 0x00004000
768 #define JM_PHY_SPEC_REG_WRITE 0x00008000
769 #define PHY_CALIBRATION_DELAY 20
770 #define JM_PHY_SPEC_ADDR_REG 0x1E
771 #define JM_PHY_SPEC_DATA_REG 0x1F
772 
773 #define JM_PHY_EXT_COMM_0_REG 0x30
774 #define JM_PHY_EXT_COMM_1_REG 0x31
775 #define JM_PHY_EXT_COMM_2_REG 0x32
776 #define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
777 #define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
778 #define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
779 #define PCI_PRIV_SHARE_NICCTRL 0xF5
780 #define JME_FLAG_PHYEA_ENABLE 0x2
781 
782 /*
783  * Wakeup Frame setup interface registers
784  */
785 #define WAKEUP_FRAME_NR 8
786 #define WAKEUP_FRAME_MASK_DWNR 4
787 
788 enum jme_wfoi_bit_masks {
789  WFOI_MASK_SEL = 0x00000070,
790  WFOI_CRC_SEL = 0x00000008,
791  WFOI_FRAME_SEL = 0x00000007,
792 };
793 
794 enum jme_wfoi_shifts {
795  WFOI_MASK_SHIFT = 4,
796 };
797 
798 /*
799  * SMI Related definitions
800  */
801 enum jme_smi_bit_mask {
802  SMI_DATA_MASK = 0xFFFF0000,
803  SMI_REG_ADDR_MASK = 0x0000F800,
804  SMI_PHY_ADDR_MASK = 0x000007C0,
805  SMI_OP_WRITE = 0x00000020,
806  /* Set to 1, after req done it'll be cleared to 0 */
807  SMI_OP_REQ = 0x00000010,
808  SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
809  SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
810  SMI_OP_MDC = 0x00000002, /* Software CLK Control */
811  SMI_OP_MDEN = 0x00000001, /* Software access Enable */
812 };
813 
814 enum jme_smi_bit_shift {
815  SMI_DATA_SHIFT = 16,
816  SMI_REG_ADDR_SHIFT = 11,
817  SMI_PHY_ADDR_SHIFT = 6,
818 };
819 
820 static inline u32 smi_reg_addr(int x)
821 {
822  return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
823 }
824 
825 static inline u32 smi_phy_addr(int x)
826 {
827  return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
828 }
829 
830 #define JME_PHY_TIMEOUT 100 /* 100 msec */
831 #define JME_PHY_REG_NR 32
832 
833 /*
834  * Global Host Control
835  */
836 enum jme_ghc_bit_mask {
837  GHC_SWRST = 0x40000000,
838  GHC_TO_CLK_SRC = 0x00C00000,
839  GHC_TXMAC_CLK_SRC = 0x00300000,
840  GHC_DPX = 0x00000040,
841  GHC_SPEED = 0x00000030,
842  GHC_LINK_POLL = 0x00000001,
843 };
844 
845 enum jme_ghc_speed_val {
846  GHC_SPEED_10M = 0x00000010,
847  GHC_SPEED_100M = 0x00000020,
848  GHC_SPEED_1000M = 0x00000030,
849 };
850 
851 enum jme_ghc_to_clk {
852  GHC_TO_CLK_OFF = 0x00000000,
853  GHC_TO_CLK_GPHY = 0x00400000,
854  GHC_TO_CLK_PCIE = 0x00800000,
855  GHC_TO_CLK_INVALID = 0x00C00000,
856 };
857 
858 enum jme_ghc_txmac_clk {
859  GHC_TXMAC_CLK_OFF = 0x00000000,
860  GHC_TXMAC_CLK_GPHY = 0x00100000,
861  GHC_TXMAC_CLK_PCIE = 0x00200000,
862  GHC_TXMAC_CLK_INVALID = 0x00300000,
863 };
864 
865 /*
866  * Power management control and status register
867  */
868 enum jme_pmcs_bit_masks {
869  PMCS_STMASK = 0xFFFF0000,
870  PMCS_WF7DET = 0x80000000,
871  PMCS_WF6DET = 0x40000000,
872  PMCS_WF5DET = 0x20000000,
873  PMCS_WF4DET = 0x10000000,
874  PMCS_WF3DET = 0x08000000,
875  PMCS_WF2DET = 0x04000000,
876  PMCS_WF1DET = 0x02000000,
877  PMCS_WF0DET = 0x01000000,
878  PMCS_LFDET = 0x00040000,
879  PMCS_LRDET = 0x00020000,
880  PMCS_MFDET = 0x00010000,
881  PMCS_ENMASK = 0x0000FFFF,
882  PMCS_WF7EN = 0x00008000,
883  PMCS_WF6EN = 0x00004000,
884  PMCS_WF5EN = 0x00002000,
885  PMCS_WF4EN = 0x00001000,
886  PMCS_WF3EN = 0x00000800,
887  PMCS_WF2EN = 0x00000400,
888  PMCS_WF1EN = 0x00000200,
889  PMCS_WF0EN = 0x00000100,
890  PMCS_LFEN = 0x00000004,
891  PMCS_LREN = 0x00000002,
892  PMCS_MFEN = 0x00000001,
893 };
894 
895 /*
896  * New PHY Power Control Register
897  */
898 enum jme_phy_pwr_bit_masks {
899  PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
900  PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
901  PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
902  PHY_PWR_CLKSEL = 0x08000000, /*
903  * XTL_OUT Clock select
904  * (an internal free-running clock)
905  * 0: xtl_out = phy_giga.A_XTL25_O
906  * 1: xtl_out = phy_giga.PD_OSC
907  */
908 };
909 
910 /*
911  * Giga PHY Status Registers
912  */
913 enum jme_phy_link_bit_mask {
914  PHY_LINK_SPEED_MASK = 0x0000C000,
915  PHY_LINK_DUPLEX = 0x00002000,
916  PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
917  PHY_LINK_UP = 0x00000400,
918  PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
919  PHY_LINK_MDI_STAT = 0x00000040,
920 };
921 
922 enum jme_phy_link_speed_val {
923  PHY_LINK_SPEED_10M = 0x00000000,
924  PHY_LINK_SPEED_100M = 0x00004000,
925  PHY_LINK_SPEED_1000M = 0x00008000,
926 };
927 
928 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
929 
930 /*
931  * SMB Control and Status
932  */
933 enum jme_smbcsr_bit_mask {
934  SMBCSR_CNACK = 0x00020000,
935  SMBCSR_RELOAD = 0x00010000,
936  SMBCSR_EEPROMD = 0x00000020,
937  SMBCSR_INITDONE = 0x00000010,
938  SMBCSR_BUSY = 0x0000000F,
939 };
940 
941 enum jme_smbintf_bit_mask {
942  SMBINTF_HWDATR = 0xFF000000,
943  SMBINTF_HWDATW = 0x00FF0000,
944  SMBINTF_HWADDR = 0x0000FF00,
945  SMBINTF_HWRWN = 0x00000020,
946  SMBINTF_HWCMD = 0x00000010,
947  SMBINTF_FASTM = 0x00000008,
948  SMBINTF_GPIOSCL = 0x00000004,
949  SMBINTF_GPIOSDA = 0x00000002,
950  SMBINTF_GPIOEN = 0x00000001,
951 };
952 
953 enum jme_smbintf_vals {
954  SMBINTF_HWRWN_READ = 0x00000020,
955  SMBINTF_HWRWN_WRITE = 0x00000000,
956 };
957 
958 enum jme_smbintf_shifts {
959  SMBINTF_HWDATR_SHIFT = 24,
960  SMBINTF_HWDATW_SHIFT = 16,
961  SMBINTF_HWADDR_SHIFT = 8,
962 };
963 
964 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
965 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
966 #define JME_SMB_LEN 256
967 #define JME_EEPROM_MAGIC 0x250
968 
969 /*
970  * Timer Control/Status Register
971  */
972 enum jme_tmcsr_bit_masks {
973  TMCSR_SWIT = 0x80000000,
974  TMCSR_EN = 0x01000000,
975  TMCSR_CNT = 0x00FFFFFF,
976 };
977 
978 /*
979  * General Purpose REG-0
980  */
981 enum jme_gpreg0_masks {
982  GPREG0_DISSH = 0xFF000000,
983  GPREG0_PCIRLMT = 0x00300000,
984  GPREG0_PCCNOMUTCLR = 0x00040000,
985  GPREG0_LNKINTPOLL = 0x00001000,
986  GPREG0_PCCTMR = 0x00000300,
987  GPREG0_PHYADDR = 0x0000001F,
988 };
989 
990 enum jme_gpreg0_vals {
991  GPREG0_DISSH_DW7 = 0x80000000,
992  GPREG0_DISSH_DW6 = 0x40000000,
993  GPREG0_DISSH_DW5 = 0x20000000,
994  GPREG0_DISSH_DW4 = 0x10000000,
995  GPREG0_DISSH_DW3 = 0x08000000,
996  GPREG0_DISSH_DW2 = 0x04000000,
997  GPREG0_DISSH_DW1 = 0x02000000,
998  GPREG0_DISSH_DW0 = 0x01000000,
999  GPREG0_DISSH_ALL = 0xFF000000,
1000 
1001  GPREG0_PCIRLMT_8 = 0x00000000,
1002  GPREG0_PCIRLMT_6 = 0x00100000,
1003  GPREG0_PCIRLMT_5 = 0x00200000,
1004  GPREG0_PCIRLMT_4 = 0x00300000,
1005 
1006  GPREG0_PCCTMR_16ns = 0x00000000,
1007  GPREG0_PCCTMR_256ns = 0x00000100,
1008  GPREG0_PCCTMR_1us = 0x00000200,
1009  GPREG0_PCCTMR_1ms = 0x00000300,
1010 
1011  GPREG0_PHYADDR_1 = 0x00000001,
1012 
1013  GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1014  GPREG0_PCCTMR_1us |
1015  GPREG0_PHYADDR_1,
1016 };
1017 
1018 /*
1019  * General Purpose REG-1
1020  */
1021 enum jme_gpreg1_bit_masks {
1022  GPREG1_RXCLKOFF = 0x04000000,
1023  GPREG1_PCREQN = 0x00020000,
1024  GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1025  GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1026  GPREG1_INTRDELAYUNIT = 0x00000018,
1027  GPREG1_INTRDELAYENABLE = 0x00000007,
1028 };
1029 
1030 enum jme_gpreg1_vals {
1031  GPREG1_INTDLYUNIT_16NS = 0x00000000,
1032  GPREG1_INTDLYUNIT_256NS = 0x00000008,
1033  GPREG1_INTDLYUNIT_1US = 0x00000010,
1034  GPREG1_INTDLYUNIT_16US = 0x00000018,
1035 
1036  GPREG1_INTDLYEN_1U = 0x00000001,
1037  GPREG1_INTDLYEN_2U = 0x00000002,
1038  GPREG1_INTDLYEN_3U = 0x00000003,
1039  GPREG1_INTDLYEN_4U = 0x00000004,
1040  GPREG1_INTDLYEN_5U = 0x00000005,
1041  GPREG1_INTDLYEN_6U = 0x00000006,
1042  GPREG1_INTDLYEN_7U = 0x00000007,
1043 
1044  GPREG1_DEFAULT = GPREG1_PCREQN,
1045 };
1046 
1047 /*
1048  * Interrupt Status Bits
1049  */
1050 enum jme_interrupt_bits {
1051  INTR_SWINTR = 0x80000000,
1052  INTR_TMINTR = 0x40000000,
1053  INTR_LINKCH = 0x20000000,
1054  INTR_PAUSERCV = 0x10000000,
1055  INTR_MAGICRCV = 0x08000000,
1056  INTR_WAKERCV = 0x04000000,
1057  INTR_PCCRX0TO = 0x02000000,
1058  INTR_PCCRX1TO = 0x01000000,
1059  INTR_PCCRX2TO = 0x00800000,
1060  INTR_PCCRX3TO = 0x00400000,
1061  INTR_PCCTXTO = 0x00200000,
1062  INTR_PCCRX0 = 0x00100000,
1063  INTR_PCCRX1 = 0x00080000,
1064  INTR_PCCRX2 = 0x00040000,
1065  INTR_PCCRX3 = 0x00020000,
1066  INTR_PCCTX = 0x00010000,
1067  INTR_RX3EMP = 0x00008000,
1068  INTR_RX2EMP = 0x00004000,
1069  INTR_RX1EMP = 0x00002000,
1070  INTR_RX0EMP = 0x00001000,
1071  INTR_RX3 = 0x00000800,
1072  INTR_RX2 = 0x00000400,
1073  INTR_RX1 = 0x00000200,
1074  INTR_RX0 = 0x00000100,
1075  INTR_TX7 = 0x00000080,
1076  INTR_TX6 = 0x00000040,
1077  INTR_TX5 = 0x00000020,
1078  INTR_TX4 = 0x00000010,
1079  INTR_TX3 = 0x00000008,
1080  INTR_TX2 = 0x00000004,
1081  INTR_TX1 = 0x00000002,
1082  INTR_TX0 = 0x00000001,
1083 };
1084 
1085 static const u32 INTR_ENABLE = INTR_SWINTR |
1086  INTR_TMINTR |
1087  INTR_LINKCH |
1088  INTR_PCCRX0TO |
1089  INTR_PCCRX0 |
1090  INTR_PCCTXTO |
1091  INTR_PCCTX |
1092  INTR_RX0EMP;
1093 
1094 /*
1095  * PCC Control Registers
1096  */
1097 enum jme_pccrx_masks {
1098  PCCRXTO_MASK = 0xFFFF0000,
1099  PCCRX_MASK = 0x0000FF00,
1100 };
1101 
1102 enum jme_pcctx_masks {
1103  PCCTXTO_MASK = 0xFFFF0000,
1104  PCCTX_MASK = 0x0000FF00,
1105  PCCTX_QS_MASK = 0x000000FF,
1106 };
1107 
1108 enum jme_pccrx_shifts {
1109  PCCRXTO_SHIFT = 16,
1110  PCCRX_SHIFT = 8,
1111 };
1112 
1113 enum jme_pcctx_shifts {
1114  PCCTXTO_SHIFT = 16,
1115  PCCTX_SHIFT = 8,
1116 };
1117 
1118 enum jme_pcctx_bits {
1119  PCCTXQ0_EN = 0x00000001,
1120  PCCTXQ1_EN = 0x00000002,
1121  PCCTXQ2_EN = 0x00000004,
1122  PCCTXQ3_EN = 0x00000008,
1123  PCCTXQ4_EN = 0x00000010,
1124  PCCTXQ5_EN = 0x00000020,
1125  PCCTXQ6_EN = 0x00000040,
1126  PCCTXQ7_EN = 0x00000080,
1127 };
1128 
1129 /*
1130  * Chip Mode Register
1131  */
1132 enum jme_chipmode_bit_masks {
1133  CM_FPGAVER_MASK = 0xFFFF0000,
1134  CM_CHIPREV_MASK = 0x0000FF00,
1135  CM_CHIPMODE_MASK = 0x0000000F,
1136 };
1137 
1138 enum jme_chipmode_shifts {
1139  CM_FPGAVER_SHIFT = 16,
1140  CM_CHIPREV_SHIFT = 8,
1141 };
1142 
1143 /*
1144  * Aggressive Power Mode Control
1145  */
1146 enum jme_apmc_bits {
1147  JME_APMC_PCIE_SD_EN = 0x40000000,
1148  JME_APMC_PSEUDO_HP_EN = 0x20000000,
1149  JME_APMC_EPIEN = 0x04000000,
1150  JME_APMC_EPIEN_CTRL = 0x03000000,
1151 };
1152 
1153 enum jme_apmc_values {
1154  JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1155  JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1156 };
1157 
1158 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1159 
1160 #ifdef REG_DEBUG
1161 static char *MAC_REG_NAME[] = {
1162  "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1163  "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1164  "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1165  "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1166  "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1167  "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1168  "JME_PMCS"};
1169 
1170 static char *PE_REG_NAME[] = {
1171  "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1172  "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1173  "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1174  "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1175  "JME_SMBCSR", "JME_SMBINTF"};
1176 
1177 static char *MISC_REG_NAME[] = {
1178  "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1179  "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1180  "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1181  "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1182  "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1183  "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1184  "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1185  "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1186  "JME_PCCSRX0"};
1187 
1188 static inline void reg_dbg(const struct jme_adapter *jme,
1189  const char *msg, u32 val, u32 reg)
1190 {
1191  const char *regname;
1192  switch (reg & 0xF00) {
1193  case 0x000:
1194  regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1195  break;
1196  case 0x400:
1197  regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1198  break;
1199  case 0x800:
1200  regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1201  break;
1202  default:
1203  regname = PE_REG_NAME[0];
1204  }
1205  printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1206  msg, val, regname);
1207 }
1208 #else
1209 static inline void reg_dbg(const struct jme_adapter *jme,
1210  const char *msg, u32 val, u32 reg) {}
1211 #endif
1212 
1213 /*
1214  * Read/Write MMaped I/O Registers
1215  */
1216 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1217 {
1218  return readl(jme->regs + reg);
1219 }
1220 
1221 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1222 {
1223  reg_dbg(jme, "REG WRITE", val, reg);
1224  writel(val, jme->regs + reg);
1225  reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1226 }
1227 
1228 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1229 {
1230  /*
1231  * Read after write should cause flush
1232  */
1233  reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1234  writel(val, jme->regs + reg);
1235  readl(jme->regs + reg);
1236  reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1237 }
1238 
1239 /*
1240  * PHY Regs
1241  */
1242 enum jme_phy_reg17_bit_masks {
1243  PREG17_SPEED = 0xC000,
1244  PREG17_DUPLEX = 0x2000,
1245  PREG17_SPDRSV = 0x0800,
1246  PREG17_LNKUP = 0x0400,
1247  PREG17_MDI = 0x0040,
1248 };
1249 
1250 enum jme_phy_reg17_vals {
1251  PREG17_SPEED_10M = 0x0000,
1252  PREG17_SPEED_100M = 0x4000,
1253  PREG17_SPEED_1000M = 0x8000,
1254 };
1255 
1256 #define BMSR_ANCOMP 0x0020
1257 
1258 /*
1259  * Workaround
1260  */
1261 static inline int is_buggy250(unsigned short device, u8 chiprev)
1262 {
1263  return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1264 }
1265 
1266 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1267 {
1268  return chip_main_rev >= 5;
1269 }
1270 
1271 /*
1272  * Function prototypes
1273  */
1274 static int jme_set_settings(struct net_device *netdev,
1275  struct ethtool_cmd *ecmd);
1276 static void jme_set_unicastaddr(struct net_device *netdev);
1277 static void jme_set_multi(struct net_device *netdev);
1278 
1279 #endif
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