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kn05.h
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1 /*
2  * include/asm-mips/dec/kn05.h
3  *
4  * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
5  * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
6  * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
7  * definitions.
8  *
9  * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
10  *
11  * This program is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License
13  * as published by the Free Software Foundation; either version
14  * 2 of the License, or (at your option) any later version.
15  *
16  * WARNING! All this information is pure guesswork based on the
17  * ROM. It is provided here in hope it will give someone some
18  * food for thought. No documentation for the KN05 nor the KN04
19  * module has been located so far.
20  */
21 #ifndef __ASM_MIPS_DEC_KN05_H
22 #define __ASM_MIPS_DEC_KN05_H
23 
24 #include <asm/dec/ioasic_addrs.h>
25 
26 /*
27  * The oncard MB (Memory Buffer) ASIC provides an additional address
28  * decoder. Certain address ranges within the "high" 16 slots are
29  * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
30  * Others are handled locally. "Low" slots are always passed.
31  */
32 #define KN4K_SLOT_BASE 0x1fc00000
33 
34 #define KN4K_MB_ROM (0*IOASIC_SLOT_SIZE) /* KN05/KN04 card ROM */
35 #define KN4K_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
36 #define KN4K_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
37 #define KN4K_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
38 #define KN4K_MB_INT (4*IOASIC_SLOT_SIZE) /* MB interrupt register */
39 #define KN4K_MB_EA (5*IOASIC_SLOT_SIZE) /* MB error address? */
40 #define KN4K_MB_EC (6*IOASIC_SLOT_SIZE) /* MB error ??? */
41 #define KN4K_MB_CSR (7*IOASIC_SLOT_SIZE) /* MB control & status */
42 #define KN4K_RES_08 (8*IOASIC_SLOT_SIZE) /* unused? */
43 #define KN4K_RES_09 (9*IOASIC_SLOT_SIZE) /* unused? */
44 #define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */
45 #define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */
46 #define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
47 #define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */
48 #define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */
49 #define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
50 
51 /*
52  * Bits for the MB interrupt register.
53  * The register appears read-only.
54  */
55 #define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
56 #define KN4K_MB_INT_RTC (1<<1) /* RTC? */
57 #define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */
58 
59 /*
60  * Bits for the MB control & status register.
61  * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
62  */
63 #define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
64 #define KN4K_MB_CSR_F (1<<1) /* ??? */
65 #define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */
66 #define KN4K_MB_CSR_OD (1<<10) /* ??? */
67 #define KN4K_MB_CSR_CP (1<<11) /* ??? */
68 #define KN4K_MB_CSR_UNC (1<<12) /* ??? */
69 #define KN4K_MB_CSR_IM (1<<13) /* ??? */
70 #define KN4K_MB_CSR_NC (1<<14) /* ??? */
71 #define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
72 #define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
73 #define KN4K_MB_CSR_FW (1<<21) /* ??? */
74 #define KN4K_MB_CSR_W (1<<31) /* ??? */
75 
76 #endif /* __ASM_MIPS_DEC_KN05_H */