Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
m32700ut_pld.h
Go to the documentation of this file.
1 #ifndef _M32700UT_M32700UT_PLD_H
2 #define _M32700UT_M32700UT_PLD_H
3 
4 /*
5  * include/asm-m32r/m32700ut/m32700ut_pld.h
6  *
7  * Definitions for Programmable Logic Device(PLD) on M32700UT board.
8  *
9  * Copyright (c) 2002 Takeo Takahashi
10  *
11  * This file is subject to the terms and conditions of the GNU General
12  * Public License. See the file "COPYING" in the main directory of
13  * this archive for more details.
14  */
15 
16 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV)
17 #define PLD_PLAT_BASE 0x04c00000
18 #else
19 #error "no platform configuration"
20 #endif
21 
22 #ifndef __ASSEMBLY__
23 /*
24  * C functions use non-cache address.
25  */
26 #define PLD_BASE (PLD_PLAT_BASE /* + NONCACHE_OFFSET */)
27 #define __reg8 (volatile unsigned char *)
28 #define __reg16 (volatile unsigned short *)
29 #define __reg32 (volatile unsigned int *)
30 #else
31 #define PLD_BASE (PLD_PLAT_BASE + NONCACHE_OFFSET)
32 #define __reg8
33 #define __reg16
34 #define __reg32
35 #endif /* __ASSEMBLY__ */
36 
37 /* CFC */
38 #define PLD_CFRSTCR __reg16(PLD_BASE + 0x0000)
39 #define PLD_CFSTS __reg16(PLD_BASE + 0x0002)
40 #define PLD_CFIMASK __reg16(PLD_BASE + 0x0004)
41 #define PLD_CFBUFCR __reg16(PLD_BASE + 0x0006)
42 #define PLD_CFVENCR __reg16(PLD_BASE + 0x0008)
43 #define PLD_CFCR0 __reg16(PLD_BASE + 0x000a)
44 #define PLD_CFCR1 __reg16(PLD_BASE + 0x000c)
45 #define PLD_IDERSTCR __reg16(PLD_BASE + 0x0010)
46 
47 /* MMC */
48 #define PLD_MMCCR __reg16(PLD_BASE + 0x4000)
49 #define PLD_MMCMOD __reg16(PLD_BASE + 0x4002)
50 #define PLD_MMCSTS __reg16(PLD_BASE + 0x4006)
51 #define PLD_MMCBAUR __reg16(PLD_BASE + 0x400a)
52 #define PLD_MMCCMDBCUT __reg16(PLD_BASE + 0x400c)
53 #define PLD_MMCCDTBCUT __reg16(PLD_BASE + 0x400e)
54 #define PLD_MMCDET __reg16(PLD_BASE + 0x4010)
55 #define PLD_MMCWP __reg16(PLD_BASE + 0x4012)
56 #define PLD_MMCWDATA __reg16(PLD_BASE + 0x5000)
57 #define PLD_MMCRDATA __reg16(PLD_BASE + 0x6000)
58 #define PLD_MMCCMDDATA __reg16(PLD_BASE + 0x7000)
59 #define PLD_MMCRSPDATA __reg16(PLD_BASE + 0x7006)
60 
61 /* ICU
62  * ICUISTS: status register
63  * ICUIREQ0: request register
64  * ICUIREQ1: request register
65  * ICUCR3: control register for CFIREQ# interrupt
66  * ICUCR4: control register for CFC Card insert interrupt
67  * ICUCR5: control register for CFC Card eject interrupt
68  * ICUCR6: control register for external interrupt
69  * ICUCR11: control register for MMC Card insert/eject interrupt
70  * ICUCR13: control register for SC error interrupt
71  * ICUCR14: control register for SC receive interrupt
72  * ICUCR15: control register for SC send interrupt
73  * ICUCR16: control register for SIO0 receive interrupt
74  * ICUCR17: control register for SIO0 send interrupt
75  */
76 #if !defined(CONFIG_PLAT_USRV)
77 #define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
78 #define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
79 #define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
80 #define PLD_IRQ_CFIREQ (M32700UT_PLD_IRQ_BASE + 3) /* CF IREQ */
81 #define PLD_IRQ_CFC_INSERT (M32700UT_PLD_IRQ_BASE + 4) /* CF Insert */
82 #define PLD_IRQ_CFC_EJECT (M32700UT_PLD_IRQ_BASE + 5) /* CF Eject */
83 #define PLD_IRQ_EXINT (M32700UT_PLD_IRQ_BASE + 6) /* EXINT */
84 #define PLD_IRQ_INT7 (M32700UT_PLD_IRQ_BASE + 7) /* reserved */
85 #define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
86 #define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
87 #define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
88 #define PLD_IRQ_MMCCARD (M32700UT_PLD_IRQ_BASE + 11) /* MMC Insert/Eject */
89 #define PLD_IRQ_INT12 (M32700UT_PLD_IRQ_BASE + 12) /* reserved */
90 #define PLD_IRQ_SC_ERROR (M32700UT_PLD_IRQ_BASE + 13) /* SC error */
91 #define PLD_IRQ_SC_RCV (M32700UT_PLD_IRQ_BASE + 14) /* SC receive */
92 #define PLD_IRQ_SC_SND (M32700UT_PLD_IRQ_BASE + 15) /* SC send */
93 #define PLD_IRQ_SIO0_RCV (M32700UT_PLD_IRQ_BASE + 16) /* SIO receive */
94 #define PLD_IRQ_SIO0_SND (M32700UT_PLD_IRQ_BASE + 17) /* SIO send */
95 #define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
96 #define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
97 #define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
98 #define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
99 #define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
100 #define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
101 #define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
102 #define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
103 #define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
104 #define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
105 #define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
106 #define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
107 #define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
108 #define PLD_IRQ_INT31 (M32700UT_PLD_IRQ_BASE + 31) /* reserved */
109 
110 #else /* CONFIG_PLAT_USRV */
111 
112 #define PLD_IRQ_INT0 (M32700UT_PLD_IRQ_BASE + 0) /* None */
113 #define PLD_IRQ_INT1 (M32700UT_PLD_IRQ_BASE + 1) /* reserved */
114 #define PLD_IRQ_INT2 (M32700UT_PLD_IRQ_BASE + 2) /* reserved */
115 #define PLD_IRQ_CF0 (M32700UT_PLD_IRQ_BASE + 3) /* CF0# */
116 #define PLD_IRQ_CF1 (M32700UT_PLD_IRQ_BASE + 4) /* CF1# */
117 #define PLD_IRQ_CF2 (M32700UT_PLD_IRQ_BASE + 5) /* CF2# */
118 #define PLD_IRQ_CF3 (M32700UT_PLD_IRQ_BASE + 6) /* CF3# */
119 #define PLD_IRQ_CF4 (M32700UT_PLD_IRQ_BASE + 7) /* CF4# */
120 #define PLD_IRQ_INT8 (M32700UT_PLD_IRQ_BASE + 8) /* reserved */
121 #define PLD_IRQ_INT9 (M32700UT_PLD_IRQ_BASE + 9) /* reserved */
122 #define PLD_IRQ_INT10 (M32700UT_PLD_IRQ_BASE + 10) /* reserved */
123 #define PLD_IRQ_INT11 (M32700UT_PLD_IRQ_BASE + 11) /* reserved */
124 #define PLD_IRQ_UART0 (M32700UT_PLD_IRQ_BASE + 12) /* UARTIRQ0 */
125 #define PLD_IRQ_UART1 (M32700UT_PLD_IRQ_BASE + 13) /* UARTIRQ1 */
126 #define PLD_IRQ_INT14 (M32700UT_PLD_IRQ_BASE + 14) /* reserved */
127 #define PLD_IRQ_INT15 (M32700UT_PLD_IRQ_BASE + 15) /* reserved */
128 #define PLD_IRQ_SNDINT (M32700UT_PLD_IRQ_BASE + 16) /* SNDINT# */
129 #define PLD_IRQ_INT17 (M32700UT_PLD_IRQ_BASE + 17) /* reserved */
130 #define PLD_IRQ_INT18 (M32700UT_PLD_IRQ_BASE + 18) /* reserved */
131 #define PLD_IRQ_INT19 (M32700UT_PLD_IRQ_BASE + 19) /* reserved */
132 #define PLD_IRQ_INT20 (M32700UT_PLD_IRQ_BASE + 20) /* reserved */
133 #define PLD_IRQ_INT21 (M32700UT_PLD_IRQ_BASE + 21) /* reserved */
134 #define PLD_IRQ_INT22 (M32700UT_PLD_IRQ_BASE + 22) /* reserved */
135 #define PLD_IRQ_INT23 (M32700UT_PLD_IRQ_BASE + 23) /* reserved */
136 #define PLD_IRQ_INT24 (M32700UT_PLD_IRQ_BASE + 24) /* reserved */
137 #define PLD_IRQ_INT25 (M32700UT_PLD_IRQ_BASE + 25) /* reserved */
138 #define PLD_IRQ_INT26 (M32700UT_PLD_IRQ_BASE + 26) /* reserved */
139 #define PLD_IRQ_INT27 (M32700UT_PLD_IRQ_BASE + 27) /* reserved */
140 #define PLD_IRQ_INT28 (M32700UT_PLD_IRQ_BASE + 28) /* reserved */
141 #define PLD_IRQ_INT29 (M32700UT_PLD_IRQ_BASE + 29) /* reserved */
142 #define PLD_IRQ_INT30 (M32700UT_PLD_IRQ_BASE + 30) /* reserved */
143 
144 #endif /* CONFIG_PLAT_USRV */
145 
146 #define PLD_ICUISTS __reg16(PLD_BASE + 0x8002)
147 #define PLD_ICUISTS_VECB_MASK (0xf000)
148 #define PLD_ICUISTS_VECB(x) ((x) & PLD_ICUISTS_VECB_MASK)
149 #define PLD_ICUISTS_ISN_MASK (0x07c0)
150 #define PLD_ICUISTS_ISN(x) ((x) & PLD_ICUISTS_ISN_MASK)
151 #define PLD_ICUIREQ0 __reg16(PLD_BASE + 0x8004)
152 #define PLD_ICUIREQ1 __reg16(PLD_BASE + 0x8006)
153 #define PLD_ICUCR1 __reg16(PLD_BASE + 0x8100)
154 #define PLD_ICUCR2 __reg16(PLD_BASE + 0x8102)
155 #define PLD_ICUCR3 __reg16(PLD_BASE + 0x8104)
156 #define PLD_ICUCR4 __reg16(PLD_BASE + 0x8106)
157 #define PLD_ICUCR5 __reg16(PLD_BASE + 0x8108)
158 #define PLD_ICUCR6 __reg16(PLD_BASE + 0x810a)
159 #define PLD_ICUCR7 __reg16(PLD_BASE + 0x810c)
160 #define PLD_ICUCR8 __reg16(PLD_BASE + 0x810e)
161 #define PLD_ICUCR9 __reg16(PLD_BASE + 0x8110)
162 #define PLD_ICUCR10 __reg16(PLD_BASE + 0x8112)
163 #define PLD_ICUCR11 __reg16(PLD_BASE + 0x8114)
164 #define PLD_ICUCR12 __reg16(PLD_BASE + 0x8116)
165 #define PLD_ICUCR13 __reg16(PLD_BASE + 0x8118)
166 #define PLD_ICUCR14 __reg16(PLD_BASE + 0x811a)
167 #define PLD_ICUCR15 __reg16(PLD_BASE + 0x811c)
168 #define PLD_ICUCR16 __reg16(PLD_BASE + 0x811e)
169 #define PLD_ICUCR17 __reg16(PLD_BASE + 0x8120)
170 #define PLD_ICUCR_IEN (0x1000)
171 #define PLD_ICUCR_IREQ (0x0100)
172 #define PLD_ICUCR_ISMOD00 (0x0000) /* Low edge */
173 #define PLD_ICUCR_ISMOD01 (0x0010) /* Low level */
174 #define PLD_ICUCR_ISMOD02 (0x0020) /* High edge */
175 #define PLD_ICUCR_ISMOD03 (0x0030) /* High level */
176 #define PLD_ICUCR_ILEVEL0 (0x0000)
177 #define PLD_ICUCR_ILEVEL1 (0x0001)
178 #define PLD_ICUCR_ILEVEL2 (0x0002)
179 #define PLD_ICUCR_ILEVEL3 (0x0003)
180 #define PLD_ICUCR_ILEVEL4 (0x0004)
181 #define PLD_ICUCR_ILEVEL5 (0x0005)
182 #define PLD_ICUCR_ILEVEL6 (0x0006)
183 #define PLD_ICUCR_ILEVEL7 (0x0007)
184 
185 /* Power Control of MMC and CF */
186 #define PLD_CPCR __reg16(PLD_BASE + 0x14000)
187 #define PLD_CPCR_CF 0x0001
188 #define PLD_CPCR_MMC 0x0002
189 
190 /* LED Control
191  *
192  * 1: DIP swich side
193  * 2: Reset switch side
194  */
195 #define PLD_IOLEDCR __reg16(PLD_BASE + 0x14002)
196 #define PLD_IOLED_1_ON 0x001
197 #define PLD_IOLED_1_OFF 0x000
198 #define PLD_IOLED_2_ON 0x002
199 #define PLD_IOLED_2_OFF 0x000
200 
201 /* DIP Switch
202  * 0: Write-protect of Flash Memory (0:protected, 1:non-protected)
203  * 1: -
204  * 2: -
205  * 3: -
206  */
207 #define PLD_IOSWSTS __reg16(PLD_BASE + 0x14004)
208 #define PLD_IOSWSTS_IOSW2 0x0200
209 #define PLD_IOSWSTS_IOSW1 0x0100
210 #define PLD_IOSWSTS_IOWP0 0x0001
211 
212 /* CRC */
213 #define PLD_CRC7DATA __reg16(PLD_BASE + 0x18000)
214 #define PLD_CRC7INDATA __reg16(PLD_BASE + 0x18002)
215 #define PLD_CRC16DATA __reg16(PLD_BASE + 0x18004)
216 #define PLD_CRC16INDATA __reg16(PLD_BASE + 0x18006)
217 #define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
218 #define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
219 
220 /* RTC */
221 #define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
222 #define PLD_RTCBAUR __reg16(PLD_BASE + 0x1c002)
223 #define PLD_RTCWRDATA __reg16(PLD_BASE + 0x1c004)
224 #define PLD_RTCRDDATA __reg16(PLD_BASE + 0x1c006)
225 #define PLD_RTCRSTODT __reg16(PLD_BASE + 0x1c008)
226 
227 /* SIO0 */
228 #define PLD_ESIO0CR __reg16(PLD_BASE + 0x20000)
229 #define PLD_ESIO0CR_TXEN 0x0001
230 #define PLD_ESIO0CR_RXEN 0x0002
231 #define PLD_ESIO0MOD0 __reg16(PLD_BASE + 0x20002)
232 #define PLD_ESIO0MOD0_CTSS 0x0040
233 #define PLD_ESIO0MOD0_RTSS 0x0080
234 #define PLD_ESIO0MOD1 __reg16(PLD_BASE + 0x20004)
235 #define PLD_ESIO0MOD1_LMFS 0x0010
236 #define PLD_ESIO0STS __reg16(PLD_BASE + 0x20006)
237 #define PLD_ESIO0STS_TEMP 0x0001
238 #define PLD_ESIO0STS_TXCP 0x0002
239 #define PLD_ESIO0STS_RXCP 0x0004
240 #define PLD_ESIO0STS_TXSC 0x0100
241 #define PLD_ESIO0STS_RXSC 0x0200
242 #define PLD_ESIO0STS_TXREADY (PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
243 #define PLD_ESIO0INTCR __reg16(PLD_BASE + 0x20008)
244 #define PLD_ESIO0INTCR_TXIEN 0x0002
245 #define PLD_ESIO0INTCR_RXCEN 0x0004
246 #define PLD_ESIO0BAUR __reg16(PLD_BASE + 0x2000a)
247 #define PLD_ESIO0TXB __reg16(PLD_BASE + 0x2000c)
248 #define PLD_ESIO0RXB __reg16(PLD_BASE + 0x2000e)
249 
250 /* SIM Card */
251 #define PLD_SCCR __reg16(PLD_BASE + 0x38000)
252 #define PLD_SCMOD __reg16(PLD_BASE + 0x38004)
253 #define PLD_SCSTS __reg16(PLD_BASE + 0x38006)
254 #define PLD_SCINTCR __reg16(PLD_BASE + 0x38008)
255 #define PLD_SCBAUR __reg16(PLD_BASE + 0x3800a)
256 #define PLD_SCTXB __reg16(PLD_BASE + 0x3800c)
257 #define PLD_SCRXB __reg16(PLD_BASE + 0x3800e)
258 
259 #endif /* _M32700UT_M32700UT_PLD.H */
Generated on Thu Jan 10 2013 13:07:25 for Linux Kernel by   doxygen 1.8.2