|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
#include <asm/m52xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m5272)" |
| #define | CPU_INSTR_PER_JIFFY 3 |
| #define | MCF_BUSCLK MCF_CLK |
| #define | MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ |
| #define | MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ |
| #define | MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ |
| #define | MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ |
| #define | MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ |
| #define | MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ |
| #define | MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ |
| #define | MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ |
| #define | MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ |
| #define | MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ |
| #define | MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ |
| #define | MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ |
| #define | MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ |
| #define | MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ |
| #define | MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ |
| #define | MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ |
| #define | MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ |
| #define | MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ |
| #define | MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ |
| #define | MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ |
| #define | MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ |
| #define | MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ |
| #define | MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ |
| #define | MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ |
| #define | MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ |
| #define | MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ |
| #define | MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ |
| #define | MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ |
| #define | MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ |
| #define | MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ |
| #define | MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ |
| #define | MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ |
| #define | MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ |
| #define | MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ |
| #define | MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ |
| #define | MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ |
| #define | MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ |
| #define | MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ |
| #define | MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ |
| #define | MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ |
| #define | MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ |
| #define | MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ |
| #define | MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ |
| #define | MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ |
| #define | MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ |
| #define | MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ |
| #define | MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ |
| #define | MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ |
| #define | MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ |
| #define | MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ |
| #define | MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ |
| #define | MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ |
| #define | MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ |
| #define | MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ |
| #define | MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ |
| #define | MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ |
| #define | MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ |
| #define | MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */ |
| #define | MCFFEC_SIZE0 0x1d0 |
| #define | MCFINT_VECBASE 64 /* Base of interrupts */ |
| #define | MCF_IRQ_SPURIOUS 64 /* User Spurious */ |
| #define | MCF_IRQ_EINT1 65 /* External Interrupt 1 */ |
| #define | MCF_IRQ_EINT2 66 /* External Interrupt 2 */ |
| #define | MCF_IRQ_EINT3 67 /* External Interrupt 3 */ |
| #define | MCF_IRQ_EINT4 68 /* External Interrupt 4 */ |
| #define | MCF_IRQ_TIMER1 69 /* Timer 1 */ |
| #define | MCF_IRQ_TIMER2 70 /* Timer 2 */ |
| #define | MCF_IRQ_TIMER3 71 /* Timer 3 */ |
| #define | MCF_IRQ_TIMER4 72 /* Timer 4 */ |
| #define | MCF_IRQ_UART0 73 /* UART 0 */ |
| #define | MCF_IRQ_UART1 74 /* UART 1 */ |
| #define | MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ |
| #define | MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ |
| #define | MCF_IRQ_USB0 77 /* USB Endpoint 0 */ |
| #define | MCF_IRQ_USB1 78 /* USB Endpoint 1 */ |
| #define | MCF_IRQ_USB2 79 /* USB Endpoint 2 */ |
| #define | MCF_IRQ_USB3 80 /* USB Endpoint 3 */ |
| #define | MCF_IRQ_USB4 81 /* USB Endpoint 4 */ |
| #define | MCF_IRQ_USB5 82 /* USB Endpoint 5 */ |
| #define | MCF_IRQ_USB6 83 /* USB Endpoint 6 */ |
| #define | MCF_IRQ_USB7 84 /* USB Endpoint 7 */ |
| #define | MCF_IRQ_DMA 85 /* DMA Controller */ |
| #define | MCF_IRQ_FECRX0 86 /* Ethernet Receiver */ |
| #define | MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */ |
| #define | MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */ |
| #define | MCF_IRQ_QSPI 89 /* Queued Serial Interface */ |
| #define | MCF_IRQ_EINT5 90 /* External Interrupt 5 */ |
| #define | MCF_IRQ_EINT6 91 /* External Interrupt 6 */ |
| #define | MCF_IRQ_SWTO 92 /* Software Watchdog */ |
| #define | MCFINT_VECMAX 95 /* Maxmum interrupt */ |
| #define | MCF_IRQ_TIMER MCF_IRQ_TIMER1 |
| #define | MCF_IRQ_PROFILER MCF_IRQ_TIMER2 |
| #define | MCFGPIO_PIN_MAX 48 |
| #define | MCFGPIO_IRQ_MAX -1 |
| #define | MCFGPIO_IRQ_VECBASE -1 |
| #define CPU_INSTR_PER_JIFFY 3 |
Definition at line 16 of file m5272sim.h.
| #define CPU_NAME "COLDFIRE(m5272)" |
Definition at line 15 of file m5272sim.h.
| #define MCF_BUSCLK MCF_CLK |
Definition at line 17 of file m5272sim.h.
| #define MCF_IRQ_DMA 85 /* DMA Controller */ |
Definition at line 119 of file m5272sim.h.
| #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */ |
Definition at line 99 of file m5272sim.h.
| #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */ |
Definition at line 100 of file m5272sim.h.
| #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */ |
Definition at line 101 of file m5272sim.h.
| #define MCF_IRQ_EINT4 68 /* External Interrupt 4 */ |
Definition at line 102 of file m5272sim.h.
| #define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ |
Definition at line 124 of file m5272sim.h.
| #define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ |
Definition at line 125 of file m5272sim.h.
| #define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */ |
Definition at line 122 of file m5272sim.h.
| #define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */ |
Definition at line 120 of file m5272sim.h.
| #define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */ |
Definition at line 121 of file m5272sim.h.
| #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ |
Definition at line 110 of file m5272sim.h.
| #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ |
Definition at line 109 of file m5272sim.h.
| #define MCF_IRQ_PROFILER MCF_IRQ_TIMER2 |
Definition at line 130 of file m5272sim.h.
| #define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ |
Definition at line 123 of file m5272sim.h.
| #define MCF_IRQ_SPURIOUS 64 /* User Spurious */ |
Definition at line 98 of file m5272sim.h.
| #define MCF_IRQ_SWTO 92 /* Software Watchdog */ |
Definition at line 126 of file m5272sim.h.
| #define MCF_IRQ_TIMER MCF_IRQ_TIMER1 |
Definition at line 129 of file m5272sim.h.
| #define MCF_IRQ_TIMER1 69 /* Timer 1 */ |
Definition at line 103 of file m5272sim.h.
| #define MCF_IRQ_TIMER2 70 /* Timer 2 */ |
Definition at line 104 of file m5272sim.h.
| #define MCF_IRQ_TIMER3 71 /* Timer 3 */ |
Definition at line 105 of file m5272sim.h.
| #define MCF_IRQ_TIMER4 72 /* Timer 4 */ |
Definition at line 106 of file m5272sim.h.
| #define MCF_IRQ_UART0 73 /* UART 0 */ |
Definition at line 107 of file m5272sim.h.
| #define MCF_IRQ_UART1 74 /* UART 1 */ |
Definition at line 108 of file m5272sim.h.
| #define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ |
Definition at line 111 of file m5272sim.h.
| #define MCF_IRQ_USB1 78 /* USB Endpoint 1 */ |
Definition at line 112 of file m5272sim.h.
| #define MCF_IRQ_USB2 79 /* USB Endpoint 2 */ |
Definition at line 113 of file m5272sim.h.
| #define MCF_IRQ_USB3 80 /* USB Endpoint 3 */ |
Definition at line 114 of file m5272sim.h.
| #define MCF_IRQ_USB4 81 /* USB Endpoint 4 */ |
Definition at line 115 of file m5272sim.h.
| #define MCF_IRQ_USB5 82 /* USB Endpoint 5 */ |
Definition at line 116 of file m5272sim.h.
| #define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ |
Definition at line 117 of file m5272sim.h.
| #define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ |
Definition at line 118 of file m5272sim.h.
| #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ |
Definition at line 84 of file m5272sim.h.
| #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */ |
Definition at line 91 of file m5272sim.h.
| #define MCFFEC_SIZE0 0x1d0 |
Definition at line 92 of file m5272sim.h.
| #define MCFGPIO_IRQ_MAX -1 |
Definition at line 136 of file m5272sim.h.
| #define MCFGPIO_IRQ_VECBASE -1 |
Definition at line 137 of file m5272sim.h.
| #define MCFGPIO_PIN_MAX 48 |
Definition at line 135 of file m5272sim.h.
| #define MCFINT_VECBASE 64 /* Base of interrupts */ |
Definition at line 97 of file m5272sim.h.
| #define MCFINT_VECMAX 95 /* Maxmum interrupt */ |
Definition at line 127 of file m5272sim.h.
| #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ |
Definition at line 27 of file m5272sim.h.
| #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ |
Definition at line 45 of file m5272sim.h.
| #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ |
Definition at line 47 of file m5272sim.h.
| #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ |
Definition at line 49 of file m5272sim.h.
| #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ |
Definition at line 51 of file m5272sim.h.
| #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ |
Definition at line 53 of file m5272sim.h.
| #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ |
Definition at line 55 of file m5272sim.h.
| #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ |
Definition at line 57 of file m5272sim.h.
| #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ |
Definition at line 59 of file m5272sim.h.
| #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ |
Definition at line 46 of file m5272sim.h.
| #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ |
Definition at line 48 of file m5272sim.h.
| #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ |
Definition at line 50 of file m5272sim.h.
| #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ |
Definition at line 52 of file m5272sim.h.
| #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ |
Definition at line 54 of file m5272sim.h.
| #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ |
Definition at line 56 of file m5272sim.h.
| #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ |
Definition at line 58 of file m5272sim.h.
| #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ |
Definition at line 60 of file m5272sim.h.
| #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ |
Definition at line 64 of file m5272sim.h.
| #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ |
Definition at line 67 of file m5272sim.h.
| #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ |
Definition at line 66 of file m5272sim.h.
| #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ |
Definition at line 69 of file m5272sim.h.
| #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ |
Definition at line 65 of file m5272sim.h.
| #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ |
Definition at line 68 of file m5272sim.h.
| #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ |
Definition at line 28 of file m5272sim.h.
| #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ |
Definition at line 30 of file m5272sim.h.
| #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ |
Definition at line 31 of file m5272sim.h.
| #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ |
Definition at line 32 of file m5272sim.h.
| #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ |
Definition at line 33 of file m5272sim.h.
| #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ |
Definition at line 35 of file m5272sim.h.
| #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ |
Definition at line 74 of file m5272sim.h.
| #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ |
Definition at line 76 of file m5272sim.h.
| #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ |
Definition at line 75 of file m5272sim.h.
| #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ |
Definition at line 77 of file m5272sim.h.
| #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ |
Definition at line 79 of file m5272sim.h.
| #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ |
Definition at line 78 of file m5272sim.h.
| #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ |
Definition at line 81 of file m5272sim.h.
| #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ |
Definition at line 80 of file m5272sim.h.
| #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ |
Definition at line 82 of file m5272sim.h.
| #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ |
Definition at line 36 of file m5272sim.h.
| #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ |
Definition at line 38 of file m5272sim.h.
| #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ |
Definition at line 37 of file m5272sim.h.
| #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ |
Definition at line 26 of file m5272sim.h.
| #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ |
Definition at line 24 of file m5272sim.h.
| #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ |
Definition at line 62 of file m5272sim.h.
| #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ |
Definition at line 63 of file m5272sim.h.
| #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ |
Definition at line 25 of file m5272sim.h.
| #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ |
Definition at line 42 of file m5272sim.h.
| #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ |
Definition at line 43 of file m5272sim.h.
| #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ |
Definition at line 41 of file m5272sim.h.
| #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ |
Definition at line 40 of file m5272sim.h.
| #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ |
Definition at line 86 of file m5272sim.h.
| #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ |
Definition at line 87 of file m5272sim.h.
| #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ |
Definition at line 88 of file m5272sim.h.
| #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ |
Definition at line 89 of file m5272sim.h.
| #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ |
Definition at line 71 of file m5272sim.h.
| #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ |
Definition at line 72 of file m5272sim.h.
1.8.2