|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Macros | |
| #define | CACR_DEC 0x80000000 /* Enable data cache */ |
| #define | CACR_DWP 0x40000000 /* Data write protection */ |
| #define | CACR_DESB 0x20000000 /* Enable data store buffer */ |
| #define | CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ |
| #define | CACR_DHCLK 0x08000000 /* Half data cache lock mode */ |
| #define | CACR_DDCM_WT 0x00000000 /* Write through cache*/ |
| #define | CACR_DDCM_CP 0x02000000 /* Copyback cache */ |
| #define | CACR_DDCM_P 0x04000000 /* No cache, precise */ |
| #define | CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ |
| #define | CACR_DCINVA 0x01000000 /* Invalidate data cache */ |
| #define | CACR_BEC 0x00080000 /* Enable branch cache */ |
| #define | CACR_BCINVA 0x00040000 /* Invalidate branch cache */ |
| #define | CACR_IEC 0x00008000 /* Enable instruction cache */ |
| #define | CACR_DNFB 0x00002000 /* Inhibited fill buffer */ |
| #define | CACR_IDPI 0x00001000 /* Disable CPUSHL */ |
| #define | CACR_IHLCK 0x00000800 /* Intruction cache half lock */ |
| #define | CACR_IDCM 0x00000400 /* Intruction cache inhibit */ |
| #define | CACR_ICINVA 0x00000100 /* Invalidate instr cache */ |
| #define | CACR_EUSP 0x00000020 /* Enable separate user a7 */ |
| #define | ACR_BASE_POS 24 /* Address Base */ |
| #define | ACR_MASK_POS 16 /* Address Mask */ |
| #define | ACR_ENABLE 0x00008000 /* Enable address */ |
| #define | ACR_USER 0x00000000 /* User mode access only */ |
| #define | ACR_SUPER 0x00002000 /* Supervisor mode only */ |
| #define | ACR_ANY 0x00004000 /* Match any access mode */ |
| #define | ACR_CM_WT 0x00000000 /* Write through mode */ |
| #define | ACR_CM_CP 0x00000020 /* Copyback mode */ |
| #define | ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ |
| #define | ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ |
| #define | ACR_CM 0x00000060 /* Cache mode mask */ |
| #define | ACR_SP 0x00000008 /* Supervisor protect */ |
| #define | ACR_WPROTECT 0x00000004 /* Write protect */ |
| #define | ACR_BA(x) ((x) & 0xff000000) |
| #define | ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) |
| #define | CACHE_LINE_SIZE 0x0010 /* 16 bytes */ |
| #define | CACHE_WAYS 4 /* 4 ways */ |
| #define | ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) |
| #define | DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) |
| #define | ICACHE_MAX_ADDR ICACHE_SET_MASK |
| #define | DCACHE_MAX_ADDR DCACHE_SET_MASK |
| #define | CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) |
| #define | CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) |
| #define | DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) |
| #define | INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) |
| #define | CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) |
| #define | CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) |
| #define | CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) |
| #define | ACR0_MODE (0x000f0000+DATA_CACHE_MODE) |
| #define | ACR1_MODE 0 |
| #define | ACR2_MODE (0x000f0000+INSN_CACHE_MODE) |
| #define | ACR3_MODE 0 |
| #define ACR0_MODE (0x000f0000+DATA_CACHE_MODE) |
Definition at line 120 of file m54xxacr.h.
| #define ACR1_MODE 0 |
Definition at line 121 of file m54xxacr.h.
| #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) |
Definition at line 122 of file m54xxacr.h.
| #define ACR3_MODE 0 |
Definition at line 123 of file m54xxacr.h.
Definition at line 46 of file m54xxacr.h.
| #define ACR_ANY 0x00004000 /* Match any access mode */ |
Definition at line 36 of file m54xxacr.h.
Definition at line 45 of file m54xxacr.h.
| #define ACR_BASE_POS 24 /* Address Base */ |
Definition at line 31 of file m54xxacr.h.
| #define ACR_CM 0x00000060 /* Cache mode mask */ |
Definition at line 41 of file m54xxacr.h.
| #define ACR_CM_CP 0x00000020 /* Copyback mode */ |
Definition at line 38 of file m54xxacr.h.
| #define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ |
Definition at line 40 of file m54xxacr.h.
| #define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ |
Definition at line 39 of file m54xxacr.h.
| #define ACR_CM_WT 0x00000000 /* Write through mode */ |
Definition at line 37 of file m54xxacr.h.
| #define ACR_ENABLE 0x00008000 /* Enable address */ |
Definition at line 33 of file m54xxacr.h.
| #define ACR_MASK_POS 16 /* Address Mask */ |
Definition at line 32 of file m54xxacr.h.
| #define ACR_SP 0x00000008 /* Supervisor protect */ |
Definition at line 42 of file m54xxacr.h.
| #define ACR_SUPER 0x00002000 /* Supervisor mode only */ |
Definition at line 35 of file m54xxacr.h.
| #define ACR_USER 0x00000000 /* User mode access only */ |
Definition at line 34 of file m54xxacr.h.
| #define ACR_WPROTECT 0x00000004 /* Write protect */ |
Definition at line 43 of file m54xxacr.h.
| #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) |
Definition at line 89 of file m54xxacr.h.
| #define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA) |
Definition at line 117 of file m54xxacr.h.
| #define CACHE_INVALIDATED (CACHE_MODE+CACR_DCINVA) |
Definition at line 119 of file m54xxacr.h.
| #define CACHE_INVALIDATEI (CACHE_MODE+CACR_BCINVA+CACR_ICINVA) |
Definition at line 118 of file m54xxacr.h.
| #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ |
Definition at line 64 of file m54xxacr.h.
Definition at line 87 of file m54xxacr.h.
| #define CACHE_WAYS 4 /* 4 ways */ |
Definition at line 65 of file m54xxacr.h.
| #define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ |
Definition at line 22 of file m54xxacr.h.
| #define CACR_BEC 0x00080000 /* Enable branch cache */ |
Definition at line 21 of file m54xxacr.h.
| #define CACR_DCINVA 0x01000000 /* Invalidate data cache */ |
Definition at line 20 of file m54xxacr.h.
| #define CACR_DDCM_CP 0x02000000 /* Copyback cache */ |
Definition at line 17 of file m54xxacr.h.
| #define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ |
Definition at line 19 of file m54xxacr.h.
| #define CACR_DDCM_P 0x04000000 /* No cache, precise */ |
Definition at line 18 of file m54xxacr.h.
| #define CACR_DDCM_WT 0x00000000 /* Write through cache*/ |
Definition at line 16 of file m54xxacr.h.
| #define CACR_DDPI 0x10000000 /* Disable invalidation by CPUSHL */ |
Definition at line 14 of file m54xxacr.h.
| #define CACR_DEC 0x80000000 /* Enable data cache */ |
Definition at line 11 of file m54xxacr.h.
| #define CACR_DESB 0x20000000 /* Enable data store buffer */ |
Definition at line 13 of file m54xxacr.h.
| #define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ |
Definition at line 15 of file m54xxacr.h.
| #define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ |
Definition at line 24 of file m54xxacr.h.
| #define CACR_DWP 0x40000000 /* Data write protection */ |
Definition at line 12 of file m54xxacr.h.
| #define CACR_EUSP 0x00000020 /* Enable separate user a7 */ |
Definition at line 29 of file m54xxacr.h.
| #define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ |
Definition at line 28 of file m54xxacr.h.
| #define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ |
Definition at line 27 of file m54xxacr.h.
| #define CACR_IDPI 0x00001000 /* Disable CPUSHL */ |
Definition at line 25 of file m54xxacr.h.
| #define CACR_IEC 0x00008000 /* Enable instruction cache */ |
Definition at line 23 of file m54xxacr.h.
| #define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ |
Definition at line 26 of file m54xxacr.h.
| #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) |
Definition at line 113 of file m54xxacr.h.
| #define DCACHE_MAX_ADDR DCACHE_SET_MASK |
Definition at line 70 of file m54xxacr.h.
| #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) |
Definition at line 68 of file m54xxacr.h.
| #define ICACHE_MAX_ADDR ICACHE_SET_MASK |
Definition at line 69 of file m54xxacr.h.
| #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) |
Definition at line 67 of file m54xxacr.h.
| #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) |
Definition at line 115 of file m54xxacr.h.
1.8.2