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Macros
m54xxpci.h File Reference

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Macros

#define PCIIDR   (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
 
#define PCISCR   (CONFIG_MBAR + 0xb04) /* PCI status/command */
 
#define PCICCRIR   (CONFIG_MBAR + 0xb08) /* PCI class/revision */
 
#define PCICR1   (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
 
#define PCIBAR0   (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
 
#define PCIBAR1   (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
 
#define PCICCPR   (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
 
#define PCISID   (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
 
#define PCIERBAR   (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
 
#define PCICPR   (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
 
#define PCICR2   (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
 
#define PCIGSCR   (CONFIG_MBAR + 0xb60) /* Global status/control */
 
#define PCITBATR0   (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
 
#define PCITBATR1   (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
 
#define PCITCR   (CONFIG_MBAR + 0xb6c) /* Target control */
 
#define PCIIW0BTAR   (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
 
#define PCIIW1BTAR   (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
 
#define PCIIW2BTAR   (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
 
#define PCIIWCR   (CONFIG_MBAR + 0xb80) /* Initiator window config */
 
#define PCIICR   (CONFIG_MBAR + 0xb84) /* Initiator control */
 
#define PCIISR   (CONFIG_MBAR + 0xb88) /* Initiator status */
 
#define PCICAR   (CONFIG_MBAR + 0xbf8) /* Configuration address */
 
#define PCITPSR   (CONFIG_MBAR + 0x8400) /* TX packet size */
 
#define PCITSAR   (CONFIG_MBAR + 0x8404) /* TX start address */
 
#define PCITTCR   (CONFIG_MBAR + 0x8408) /* TX transaction control */
 
#define PCITER   (CONFIG_MBAR + 0x840c) /* TX enables */
 
#define PCITNAR   (CONFIG_MBAR + 0x8410) /* TX next address */
 
#define PCITLWR   (CONFIG_MBAR + 0x8414) /* TX last word */
 
#define PCITDCR   (CONFIG_MBAR + 0x8418) /* TX done counts */
 
#define PCITSR   (CONFIG_MBAR + 0x841c) /* TX status */
 
#define PCITFDR   (CONFIG_MBAR + 0x8440) /* TX FIFO data */
 
#define PCITFSR   (CONFIG_MBAR + 0x8444) /* TX FIFO status */
 
#define PCITFCR   (CONFIG_MBAR + 0x8448) /* TX FIFO control */
 
#define PCITFAR   (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
 
#define PCITFRPR   (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
 
#define PCITFWPR   (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
 
#define PCIRPSR   (CONFIG_MBAR + 0x8480) /* RX packet size */
 
#define PCIRSAR   (CONFIG_MBAR + 0x8484) /* RX start address */
 
#define PCIRTCR   (CONFIG_MBAR + 0x8488) /* RX transaction control */
 
#define PCIRER   (CONFIG_MBAR + 0x848c) /* RX enables */
 
#define PCIRNAR   (CONFIG_MBAR + 0x8490) /* RX next address */
 
#define PCIRDCR   (CONFIG_MBAR + 0x8498) /* RX done counts */
 
#define PCIRSR   (CONFIG_MBAR + 0x849c) /* RX status */
 
#define PCIRFDR   (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
 
#define PCIRFSR   (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
 
#define PCIRFCR   (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
 
#define PCIRFAR   (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
 
#define PCIRFRPR   (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
 
#define PCIRFWPR   (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
 
#define PACR   (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
 
#define PASR   (COFNIG_MBAR + 0xc04) /* PCI arbiter status */
 
#define PCIGSCR_PE   0x20000000 /* Parity error detected */
 
#define PCIGSCR_SE   0x10000000 /* System error detected */
 
#define PCIGSCR_XCLKBIN   0x07000000 /* XLB2CLKIN mask */
 
#define PCIGSCR_PEE   0x00002000 /* Parity error intr enable */
 
#define PCIGSCR_SEE   0x00001000 /* System error intr enable */
 
#define PCIGSCR_RESET   0x00000001 /* Reset bit */
 
#define PCICAR_E   0x80000000 /* Enable config space */
 
#define PCICAR_BUSN   16 /* Move bus bits */
 
#define PCICAR_DEVFNN   8 /* Move devfn bits */
 
#define PCICAR_DWORDN   0 /* Move dword bits */
 
#define WXBTAR(hostaddr, pciaddr, size)
 
#define PCIIWCR_W0_MEM   0x00000000 /* Window 0 is memory */
 
#define PCIIWCR_W0_IO   0x08000000 /* Window 0 is IO */
 
#define PCIIWCR_W0_MRD   0x00000000 /* Window 0 memory read */
 
#define PCIIWCR_W0_MRDL   0x02000000 /* Window 0 memory read line */
 
#define PCIIWCR_W0_MRDM   0x04000000 /* Window 0 memory read mult */
 
#define PCIIWCR_W0_E   0x01000000 /* Window 0 enable */
 
#define PCIIWCR_W1_MEM   0x00000000 /* Window 0 is memory */
 
#define PCIIWCR_W1_IO   0x00080000 /* Window 0 is IO */
 
#define PCIIWCR_W1_MRD   0x00000000 /* Window 0 memory read */
 
#define PCIIWCR_W1_MRDL   0x00020000 /* Window 0 memory read line */
 
#define PCIIWCR_W1_MRDM   0x00040000 /* Window 0 memory read mult */
 
#define PCIIWCR_W1_E   0x00010000 /* Window 0 enable */
 
#define PCITBATR0_E   0x00000001 /* Enable window 0 */
 
#define PCITBATR1_E   0x00000001 /* Enable window 1 */
 
#define PACR_INTMPRI   0x00000001
 
#define PACR_EXTMPRI(x)   (((x) & 0x1f) << 1)
 
#define PACR_INTMINTE   0x00010000
 
#define PACR_EXTMINTE(x)   (((x) & 0x1f) << 17)
 
#define PACR_PKMD   0x40000000
 
#define PACR_DS   0x80000000
 
#define PCICR1_CL(x)   ((x) & 0xf) /* Cacheline size field */
 
#define PCICR1_LT(x)   (((x) & 0xff) << 8) /* Latency timer field */
 

Macro Definition Documentation

#define PACR   (CONFIG_MBAR + 0xc00) /* PCI arbiter control */

Definition at line 74 of file m54xxpci.h.

#define PACR_DS   0x80000000

Definition at line 132 of file m54xxpci.h.

#define PACR_EXTMINTE (   x)    (((x) & 0x1f) << 17)

Definition at line 130 of file m54xxpci.h.

#define PACR_EXTMPRI (   x)    (((x) & 0x1f) << 1)

Definition at line 128 of file m54xxpci.h.

#define PACR_INTMINTE   0x00010000

Definition at line 129 of file m54xxpci.h.

#define PACR_INTMPRI   0x00000001

Definition at line 127 of file m54xxpci.h.

#define PACR_PKMD   0x40000000

Definition at line 131 of file m54xxpci.h.

#define PASR   (COFNIG_MBAR + 0xc04) /* PCI arbiter status */

Definition at line 75 of file m54xxpci.h.

#define PCIBAR0   (CONFIG_MBAR + 0xb10) /* PCI base address 0 */

Definition at line 25 of file m54xxpci.h.

#define PCIBAR1   (CONFIG_MBAR + 0xb14) /* PCI base address 1 */

Definition at line 26 of file m54xxpci.h.

#define PCICAR   (CONFIG_MBAR + 0xbf8) /* Configuration address */

Definition at line 43 of file m54xxpci.h.

#define PCICAR_BUSN   16 /* Move bus bits */

Definition at line 91 of file m54xxpci.h.

#define PCICAR_DEVFNN   8 /* Move devfn bits */

Definition at line 92 of file m54xxpci.h.

#define PCICAR_DWORDN   0 /* Move dword bits */

Definition at line 93 of file m54xxpci.h.

#define PCICAR_E   0x80000000 /* Enable config space */

Definition at line 90 of file m54xxpci.h.

#define PCICCPR   (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */

Definition at line 27 of file m54xxpci.h.

#define PCICCRIR   (CONFIG_MBAR + 0xb08) /* PCI class/revision */

Definition at line 23 of file m54xxpci.h.

#define PCICPR   (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */

Definition at line 30 of file m54xxpci.h.

#define PCICR1   (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */

Definition at line 24 of file m54xxpci.h.

#define PCICR1_CL (   x)    ((x) & 0xf) /* Cacheline size field */

Definition at line 134 of file m54xxpci.h.

#define PCICR1_LT (   x)    (((x) & 0xff) << 8) /* Latency timer field */

Definition at line 135 of file m54xxpci.h.

#define PCICR2   (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */

Definition at line 31 of file m54xxpci.h.

#define PCIERBAR   (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */

Definition at line 29 of file m54xxpci.h.

#define PCIGSCR   (CONFIG_MBAR + 0xb60) /* Global status/control */

Definition at line 33 of file m54xxpci.h.

#define PCIGSCR_PE   0x20000000 /* Parity error detected */

Definition at line 80 of file m54xxpci.h.

#define PCIGSCR_PEE   0x00002000 /* Parity error intr enable */

Definition at line 83 of file m54xxpci.h.

#define PCIGSCR_RESET   0x00000001 /* Reset bit */

Definition at line 85 of file m54xxpci.h.

#define PCIGSCR_SE   0x10000000 /* System error detected */

Definition at line 81 of file m54xxpci.h.

#define PCIGSCR_SEE   0x00001000 /* System error intr enable */

Definition at line 84 of file m54xxpci.h.

#define PCIGSCR_XCLKBIN   0x07000000 /* XLB2CLKIN mask */

Definition at line 82 of file m54xxpci.h.

#define PCIICR   (CONFIG_MBAR + 0xb84) /* Initiator control */

Definition at line 41 of file m54xxpci.h.

#define PCIIDR   (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */

Definition at line 21 of file m54xxpci.h.

#define PCIISR   (CONFIG_MBAR + 0xb88) /* Initiator status */

Definition at line 42 of file m54xxpci.h.

#define PCIIW0BTAR   (CONFIG_MBAR + 0xb70) /* Initiator window 0 */

Definition at line 37 of file m54xxpci.h.

#define PCIIW1BTAR   (CONFIG_MBAR + 0xb74) /* Initiator window 1 */

Definition at line 38 of file m54xxpci.h.

#define PCIIW2BTAR   (CONFIG_MBAR + 0xb78) /* Initiator window 2 */

Definition at line 39 of file m54xxpci.h.

#define PCIIWCR   (CONFIG_MBAR + 0xb80) /* Initiator window config */

Definition at line 40 of file m54xxpci.h.

#define PCIIWCR_W0_E   0x01000000 /* Window 0 enable */

Definition at line 109 of file m54xxpci.h.

#define PCIIWCR_W0_IO   0x08000000 /* Window 0 is IO */

Definition at line 105 of file m54xxpci.h.

#define PCIIWCR_W0_MEM   0x00000000 /* Window 0 is memory */

Definition at line 104 of file m54xxpci.h.

#define PCIIWCR_W0_MRD   0x00000000 /* Window 0 memory read */

Definition at line 106 of file m54xxpci.h.

#define PCIIWCR_W0_MRDL   0x02000000 /* Window 0 memory read line */

Definition at line 107 of file m54xxpci.h.

#define PCIIWCR_W0_MRDM   0x04000000 /* Window 0 memory read mult */

Definition at line 108 of file m54xxpci.h.

#define PCIIWCR_W1_E   0x00010000 /* Window 0 enable */

Definition at line 116 of file m54xxpci.h.

#define PCIIWCR_W1_IO   0x00080000 /* Window 0 is IO */

Definition at line 112 of file m54xxpci.h.

#define PCIIWCR_W1_MEM   0x00000000 /* Window 0 is memory */

Definition at line 111 of file m54xxpci.h.

#define PCIIWCR_W1_MRD   0x00000000 /* Window 0 memory read */

Definition at line 113 of file m54xxpci.h.

#define PCIIWCR_W1_MRDL   0x00020000 /* Window 0 memory read line */

Definition at line 114 of file m54xxpci.h.

#define PCIIWCR_W1_MRDM   0x00040000 /* Window 0 memory read mult */

Definition at line 115 of file m54xxpci.h.

#define PCIRDCR   (CONFIG_MBAR + 0x8498) /* RX done counts */

Definition at line 65 of file m54xxpci.h.

#define PCIRER   (CONFIG_MBAR + 0x848c) /* RX enables */

Definition at line 63 of file m54xxpci.h.

#define PCIRFAR   (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */

Definition at line 70 of file m54xxpci.h.

#define PCIRFCR   (CONFIG_MBAR + 0x84c8) /* RX FIFO control */

Definition at line 69 of file m54xxpci.h.

#define PCIRFDR   (CONFIG_MBAR + 0x84c0) /* RX FIFO data */

Definition at line 67 of file m54xxpci.h.

#define PCIRFRPR   (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */

Definition at line 71 of file m54xxpci.h.

#define PCIRFSR   (CONFIG_MBAR + 0x84c4) /* RX FIFO status */

Definition at line 68 of file m54xxpci.h.

#define PCIRFWPR   (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */

Definition at line 72 of file m54xxpci.h.

#define PCIRNAR   (CONFIG_MBAR + 0x8490) /* RX next address */

Definition at line 64 of file m54xxpci.h.

#define PCIRPSR   (CONFIG_MBAR + 0x8480) /* RX packet size */

Definition at line 60 of file m54xxpci.h.

#define PCIRSAR   (CONFIG_MBAR + 0x8484) /* RX start address */

Definition at line 61 of file m54xxpci.h.

#define PCIRSR   (CONFIG_MBAR + 0x849c) /* RX status */

Definition at line 66 of file m54xxpci.h.

#define PCIRTCR   (CONFIG_MBAR + 0x8488) /* RX transaction control */

Definition at line 62 of file m54xxpci.h.

#define PCISCR   (CONFIG_MBAR + 0xb04) /* PCI status/command */

Definition at line 22 of file m54xxpci.h.

#define PCISID   (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */

Definition at line 28 of file m54xxpci.h.

#define PCITBATR0   (CONFIG_MBAR + 0xb64) /* Target base translation 0 */

Definition at line 34 of file m54xxpci.h.

#define PCITBATR0_E   0x00000001 /* Enable window 0 */

Definition at line 121 of file m54xxpci.h.

#define PCITBATR1   (CONFIG_MBAR + 0xb68) /* Target base translation 1 */

Definition at line 35 of file m54xxpci.h.

#define PCITBATR1_E   0x00000001 /* Enable window 1 */

Definition at line 122 of file m54xxpci.h.

#define PCITCR   (CONFIG_MBAR + 0xb6c) /* Target control */

Definition at line 36 of file m54xxpci.h.

#define PCITDCR   (CONFIG_MBAR + 0x8418) /* TX done counts */

Definition at line 51 of file m54xxpci.h.

#define PCITER   (CONFIG_MBAR + 0x840c) /* TX enables */

Definition at line 48 of file m54xxpci.h.

#define PCITFAR   (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */

Definition at line 56 of file m54xxpci.h.

#define PCITFCR   (CONFIG_MBAR + 0x8448) /* TX FIFO control */

Definition at line 55 of file m54xxpci.h.

#define PCITFDR   (CONFIG_MBAR + 0x8440) /* TX FIFO data */

Definition at line 53 of file m54xxpci.h.

#define PCITFRPR   (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */

Definition at line 57 of file m54xxpci.h.

#define PCITFSR   (CONFIG_MBAR + 0x8444) /* TX FIFO status */

Definition at line 54 of file m54xxpci.h.

#define PCITFWPR   (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */

Definition at line 58 of file m54xxpci.h.

#define PCITLWR   (CONFIG_MBAR + 0x8414) /* TX last word */

Definition at line 50 of file m54xxpci.h.

#define PCITNAR   (CONFIG_MBAR + 0x8410) /* TX next address */

Definition at line 49 of file m54xxpci.h.

#define PCITPSR   (CONFIG_MBAR + 0x8400) /* TX packet size */

Definition at line 45 of file m54xxpci.h.

#define PCITSAR   (CONFIG_MBAR + 0x8404) /* TX start address */

Definition at line 46 of file m54xxpci.h.

#define PCITSR   (CONFIG_MBAR + 0x841c) /* TX status */

Definition at line 52 of file m54xxpci.h.

#define PCITTCR   (CONFIG_MBAR + 0x8408) /* TX transaction control */

Definition at line 47 of file m54xxpci.h.

#define WXBTAR (   hostaddr,
  pciaddr,
  size 
)
Value:
(((hostaddr) & 0xff000000) | \
((((size) - 1) & 0xff000000) >> 8) | \
(((pciaddr) & 0xff000000) >> 16))

Definition at line 99 of file m54xxpci.h.