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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <asm/m54xxacr.h>Go to the source code of this file.
Macros | |
| #define | CPU_NAME "COLDFIRE(m54xx)" |
| #define | CPU_INSTR_PER_JIFFY 2 |
| #define | MCF_BUSCLK (MCF_CLK / 2) |
| #define | MCFINT_VECBASE 64 |
| #define | MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ |
| #define | MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
| #define | MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
| #define | MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
| #define | MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
| #define | MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
| #define | MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
| #define | MCFINTC_IRLR 0x18 /* */ |
| #define | MCFINTC_IACKL 0x19 /* */ |
| #define | MCFINTC_ICR0 0x40 /* Base ICR register */ |
| #define | MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ |
| #define | MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ |
| #define | MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ |
| #define | MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ |
| #define | MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ |
| #define | MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ |
| #define | MCF_IRQ_UART0 (MCFINT_VECBASE + 35) |
| #define | MCF_IRQ_UART1 (MCFINT_VECBASE + 34) |
| #define | MCF_IRQ_UART2 (MCFINT_VECBASE + 33) |
| #define | MCF_IRQ_UART3 (MCFINT_VECBASE + 32) |
| #define | MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */ |
| #define | MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */ |
| #define | MCFGPIO_PIN_MAX 0 /* I am too lazy to count */ |
| #define | MCFGPIO_IRQ_MAX -1 |
| #define | MCFGPIO_IRQ_VECBASE -1 |
| #define | MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ |
| #define | MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ |
| #define | MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ |
| #define | MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ |
| #define | MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ |
| #define | MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ |
| #define | MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) |
| #define | MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42) |
| #define | MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43) |
| #define | MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44) |
| #define | MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */ |
| #define | MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */ |
| #define | MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F) |
| #define | MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E) |
| #define | MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D) |
| #define | MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C) |
| #define | MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50) |
| #define | MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52) |
| #define | MCF_PAR_SDA (0x0008) |
| #define | MCF_PAR_SCL (0x0004) |
| #define | MCF_PAR_PSC_TXD (0x04) |
| #define | MCF_PAR_PSC_RXD (0x08) |
| #define | MCF_PAR_PSC_CTS_GPIO (0x00) |
| #define | MCF_PAR_PSC_CTS_BCLK (0x80) |
| #define | MCF_PAR_PSC_CTS_CTS (0xC0) |
| #define | MCF_PAR_PSC_RTS_GPIO (0x00) |
| #define | MCF_PAR_PSC_RTS_FSYNC (0x20) |
| #define | MCF_PAR_PSC_RTS_RTS (0x30) |
| #define | MCF_PAR_PSC_CANRX (0x40) |
| #define CPU_INSTR_PER_JIFFY 2 |
Definition at line 9 of file m54xxsim.h.
| #define CPU_NAME "COLDFIRE(m54xx)" |
Definition at line 8 of file m54xxsim.h.
| #define MCF_BUSCLK (MCF_CLK / 2) |
Definition at line 10 of file m54xxsim.h.
| #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ |
Definition at line 43 of file m54xxsim.h.
| #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ |
Definition at line 42 of file m54xxsim.h.
| #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) |
Definition at line 44 of file m54xxsim.h.
| #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) |
Definition at line 45 of file m54xxsim.h.
| #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) |
Definition at line 46 of file m54xxsim.h.
| #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) |
Definition at line 47 of file m54xxsim.h.
| #define MCF_PAR_PSC_CANRX (0x40) |
Definition at line 98 of file m54xxsim.h.
| #define MCF_PAR_PSC_CTS_BCLK (0x80) |
Definition at line 93 of file m54xxsim.h.
| #define MCF_PAR_PSC_CTS_CTS (0xC0) |
Definition at line 94 of file m54xxsim.h.
| #define MCF_PAR_PSC_CTS_GPIO (0x00) |
Definition at line 92 of file m54xxsim.h.
| #define MCF_PAR_PSC_RTS_FSYNC (0x20) |
Definition at line 96 of file m54xxsim.h.
| #define MCF_PAR_PSC_RTS_GPIO (0x00) |
Definition at line 95 of file m54xxsim.h.
| #define MCF_PAR_PSC_RTS_RTS (0x30) |
Definition at line 97 of file m54xxsim.h.
| #define MCF_PAR_PSC_RXD (0x08) |
Definition at line 91 of file m54xxsim.h.
| #define MCF_PAR_PSC_TXD (0x04) |
Definition at line 90 of file m54xxsim.h.
| #define MCF_PAR_SCL (0x0004) |
Definition at line 89 of file m54xxsim.h.
| #define MCF_PAR_SDA (0x0008) |
Definition at line 88 of file m54xxsim.h.
| #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ |
Definition at line 66 of file m54xxsim.h.
| #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ |
Definition at line 68 of file m54xxsim.h.
| #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ |
Definition at line 70 of file m54xxsim.h.
| #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ |
Definition at line 67 of file m54xxsim.h.
| #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ |
Definition at line 65 of file m54xxsim.h.
| #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ |
Definition at line 69 of file m54xxsim.h.
| #define MCFGPIO_IRQ_MAX -1 |
Definition at line 59 of file m54xxsim.h.
| #define MCFGPIO_IRQ_VECBASE -1 |
Definition at line 60 of file m54xxsim.h.
| #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43) |
Definition at line 77 of file m54xxsim.h.
| #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50) |
Definition at line 85 of file m54xxsim.h.
| #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42) |
Definition at line 76 of file m54xxsim.h.
| #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) |
Definition at line 75 of file m54xxsim.h.
| #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44) |
Definition at line 78 of file m54xxsim.h.
| #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */ |
Definition at line 79 of file m54xxsim.h.
| #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */ |
Definition at line 80 of file m54xxsim.h.
| #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F) |
Definition at line 81 of file m54xxsim.h.
| #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E) |
Definition at line 82 of file m54xxsim.h.
| #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D) |
Definition at line 83 of file m54xxsim.h.
| #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C) |
Definition at line 84 of file m54xxsim.h.
| #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52) |
Definition at line 86 of file m54xxsim.h.
Definition at line 58 of file m54xxsim.h.
| #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ |
Definition at line 19 of file m54xxsim.h.
| #define MCFINT_VECBASE 64 |
Definition at line 14 of file m54xxsim.h.
| #define MCFINTC_IACKL 0x19 /* */ |
Definition at line 28 of file m54xxsim.h.
| #define MCFINTC_ICR0 0x40 /* Base ICR register */ |
Definition at line 29 of file m54xxsim.h.
| #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ |
Definition at line 23 of file m54xxsim.h.
| #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ |
Definition at line 24 of file m54xxsim.h.
| #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ |
Definition at line 25 of file m54xxsim.h.
| #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ |
Definition at line 26 of file m54xxsim.h.
| #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ |
Definition at line 21 of file m54xxsim.h.
| #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ |
Definition at line 22 of file m54xxsim.h.
| #define MCFINTC_IRLR 0x18 /* */ |
Definition at line 27 of file m54xxsim.h.
| #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */ |
Definition at line 52 of file m54xxsim.h.
| #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */ |
Definition at line 53 of file m54xxsim.h.
| #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ |
Definition at line 34 of file m54xxsim.h.
| #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ |
Definition at line 35 of file m54xxsim.h.
| #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ |
Definition at line 36 of file m54xxsim.h.
| #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ |
Definition at line 37 of file m54xxsim.h.
1.8.2