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Data Structures | Macros | Functions
maceps2.c File Reference
#include <linux/module.h>
#include <linux/init.h>
#include <linux/serio.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>

Go to the source code of this file.

Data Structures

struct  maceps2_data
 

Macros

#define MACE_PS2_TIMEOUT   10000 /* in 50us unit */
 
#define PS2_STATUS_CLOCK_SIGNAL   BIT(0) /* external clock signal */
 
#define PS2_STATUS_CLOCK_INHIBIT   BIT(1) /* clken output signal */
 
#define PS2_STATUS_TX_INPROGRESS   BIT(2) /* transmission in progress */
 
#define PS2_STATUS_TX_EMPTY   BIT(3) /* empty transmit buffer */
 
#define PS2_STATUS_RX_FULL   BIT(4) /* full receive buffer */
 
#define PS2_STATUS_RX_INPROGRESS   BIT(5) /* reception in progress */
 
#define PS2_STATUS_ERROR_PARITY   BIT(6) /* parity error */
 
#define PS2_STATUS_ERROR_FRAMING   BIT(7) /* framing error */
 
#define PS2_CONTROL_TX_CLOCK_DISABLE   BIT(0) /* inhibit clock signal after TX */
 
#define PS2_CONTROL_TX_ENABLE   BIT(1) /* transmit enable */
 
#define PS2_CONTROL_TX_INT_ENABLE   BIT(2) /* enable transmit interrupt */
 
#define PS2_CONTROL_RX_INT_ENABLE   BIT(3) /* enable receive interrupt */
 
#define PS2_CONTROL_RX_CLOCK_ENABLE   BIT(4) /* pause reception if set to 0 */
 
#define PS2_CONTROL_RESET   BIT(5) /* reset */
 

Functions

 MODULE_AUTHOR ("Vivien Chappelier <[email protected]")
 
 MODULE_DESCRIPTION ("SGI O2 MACE PS2 controller driver")
 
 MODULE_LICENSE ("GPL")
 
 module_init (maceps2_init)
 
 module_exit (maceps2_exit)
 

Macro Definition Documentation

#define MACE_PS2_TIMEOUT   10000 /* in 50us unit */

Definition at line 31 of file maceps2.c.

#define PS2_CONTROL_RESET   BIT(5) /* reset */

Definition at line 47 of file maceps2.c.

#define PS2_CONTROL_RX_CLOCK_ENABLE   BIT(4) /* pause reception if set to 0 */

Definition at line 46 of file maceps2.c.

#define PS2_CONTROL_RX_INT_ENABLE   BIT(3) /* enable receive interrupt */

Definition at line 45 of file maceps2.c.

#define PS2_CONTROL_TX_CLOCK_DISABLE   BIT(0) /* inhibit clock signal after TX */

Definition at line 42 of file maceps2.c.

#define PS2_CONTROL_TX_ENABLE   BIT(1) /* transmit enable */

Definition at line 43 of file maceps2.c.

#define PS2_CONTROL_TX_INT_ENABLE   BIT(2) /* enable transmit interrupt */

Definition at line 44 of file maceps2.c.

#define PS2_STATUS_CLOCK_INHIBIT   BIT(1) /* clken output signal */

Definition at line 34 of file maceps2.c.

#define PS2_STATUS_CLOCK_SIGNAL   BIT(0) /* external clock signal */

Definition at line 33 of file maceps2.c.

#define PS2_STATUS_ERROR_FRAMING   BIT(7) /* framing error */

Definition at line 40 of file maceps2.c.

#define PS2_STATUS_ERROR_PARITY   BIT(6) /* parity error */

Definition at line 39 of file maceps2.c.

#define PS2_STATUS_RX_FULL   BIT(4) /* full receive buffer */

Definition at line 37 of file maceps2.c.

#define PS2_STATUS_RX_INPROGRESS   BIT(5) /* reception in progress */

Definition at line 38 of file maceps2.c.

#define PS2_STATUS_TX_EMPTY   BIT(3) /* empty transmit buffer */

Definition at line 36 of file maceps2.c.

#define PS2_STATUS_TX_INPROGRESS   BIT(2) /* transmission in progress */

Definition at line 35 of file maceps2.c.

Function Documentation

MODULE_AUTHOR ( )
MODULE_DESCRIPTION ( "SGI O2 MACE PS2 controller driver )
module_exit ( maceps2_exit  )
module_init ( maceps2_init  )
MODULE_LICENSE ( "GPL"  )