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#define ANOMALY_05000074 (1) |
#define ANOMALY_05000099 (0) |
#define ANOMALY_05000119 (1) |
#define ANOMALY_05000120 (0) |
#define ANOMALY_05000122 (1) |
#define ANOMALY_05000125 (0) |
#define ANOMALY_05000149 (0) |
#define ANOMALY_05000158 (0) |
#define ANOMALY_05000166 (1) |
#define ANOMALY_05000171 (0) |
#define ANOMALY_05000179 (1) |
#define ANOMALY_05000180 (1) |
#define ANOMALY_05000182 (0) |
#define ANOMALY_05000189 (0) |
#define ANOMALY_05000193 (1) |
#define ANOMALY_05000198 (0) |
#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000202 (0) |
#define ANOMALY_05000215 (0) |
#define ANOMALY_05000219 (1) |
#define ANOMALY_05000220 (0) |
#define ANOMALY_05000227 (0) |
#define ANOMALY_05000229 (1) |
#define ANOMALY_05000230 (0) |
#define ANOMALY_05000231 (0) |
#define ANOMALY_05000233 (1) |
#define ANOMALY_05000234 (0) |
#define ANOMALY_05000242 (0) |
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3) |
#define ANOMALY_05000245 (1) |
#define ANOMALY_05000248 (0) |
#define ANOMALY_05000250 (0) |
#define ANOMALY_05000253 (1) |
#define ANOMALY_05000254 (0) |
#define ANOMALY_05000257 (0) |
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3) |
#define ANOMALY_05000263 (0) |
#define ANOMALY_05000266 (0) |
#define ANOMALY_05000270 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000273 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000274 (0) |
#define ANOMALY_05000277 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000278 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000281 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000282 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000283 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000287 (0) |
#define ANOMALY_05000288 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000291 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000293 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000294 (1) |
#define ANOMALY_05000301 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000304 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000305 (0) |
#define ANOMALY_05000307 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000310 (1) |
#define ANOMALY_05000311 (0) |
#define ANOMALY_05000312 (__SILICON_REVISION__ < 5) |
#define ANOMALY_05000313 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000315 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */ |
#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */ |
#define ANOMALY_05000323 (0) |
#define ANOMALY_05000353 (1) |
#define ANOMALY_05000355 (__SILICON_REVISION__ < 5) |
#define ANOMALY_05000357 (__SILICON_REVISION__ < 5) |
#define ANOMALY_05000362 (1) |
#define ANOMALY_05000363 (0) |
#define ANOMALY_05000364 (0) |
#define ANOMALY_05000366 (1) |
#define ANOMALY_05000371 (__SILICON_REVISION__ < 5) |
#define ANOMALY_05000374 (__SILICON_REVISION__ == 4) |
#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) |
#define ANOMALY_05000380 (0) |
#define ANOMALY_05000383 (0) |
#define ANOMALY_05000386 (1) |
#define ANOMALY_05000389 (0) |
#define ANOMALY_05000400 (0) |
#define ANOMALY_05000402 (__SILICON_REVISION__ == 3) |
#define ANOMALY_05000403 (1) |
#define ANOMALY_05000412 (0) |
#define ANOMALY_05000416 (1) |
#define ANOMALY_05000425 (1) |
#define ANOMALY_05000426 (1) |
#define ANOMALY_05000430 (0) |
#define ANOMALY_05000432 (0) |
#define ANOMALY_05000435 (0) |
#define ANOMALY_05000436 (__SILICON_REVISION__ > 3) |
#define ANOMALY_05000440 (0) |
#define ANOMALY_05000443 (1) |
#define ANOMALY_05000447 (0) |
#define ANOMALY_05000448 (0) |
#define ANOMALY_05000450 (0) |
#define ANOMALY_05000456 (0) |
#define ANOMALY_05000461 (1) |
#define ANOMALY_05000462 (1) |
#define ANOMALY_05000465 (0) |
#define ANOMALY_05000467 (0) |
#define ANOMALY_05000473 (1) |
#define ANOMALY_05000474 (0) |
#define ANOMALY_05000475 (1) |
#define ANOMALY_05000477 (1) |
#define ANOMALY_05000480 (0) |
#define ANOMALY_05000481 (1) |
#define ANOMALY_05000485 (0) |
#define ANOMALY_05000489 (1) |
#define ANOMALY_05000491 (1) |
#define ANOMALY_05000494 (1) |
#define ANOMALY_05000501 (1) |