#include <plat/cpu.h>
#include <mach/map.h>
#include <mach/regs-pmu.h>

Macros
#define	__ASM_ARCH_REGS_CLOCK_H __FILE__

#define	EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))

#define	EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)

#define	EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)

#define	EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)

#define	EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)

#define	EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)

#define	EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)

#define	EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)

#define	EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)

#define	EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)

#define	EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)

#define	EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)

#define	EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)

#define	EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)

#define	EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)

#define	EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)

#define	EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)

#define	EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)

#define	EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)

#define	EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)

#define	EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)

#define	EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)

#define	EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)

#define	EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)

#define	EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)

#define	EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)

#define	EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)

#define	EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)

#define	EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)

#define	EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)

#define	EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)

#define	EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)

#define	EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)

#define	EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)

#define	EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)

#define	EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)

#define	EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)

#define	EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)

#define	EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)

#define	EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)

#define	EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)

#define	EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)

#define	EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)

#define	EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)

#define	EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)

#define	EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)

#define	EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)

#define	EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)

#define	EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)

#define	EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)

#define	EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)

#define	EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)

#define	EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)

#define	EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)

#define	EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)

#define	EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)

#define	EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)

#define	EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)

#define	EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)

#define	EXYNOS4_CLKGATE_IP_IMAGE

#define	EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)

#define	EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)

#define	EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)

#define	EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)

#define	EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)

#define	EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)

#define	EXYNOS4_CLKGATE_IP_PERIR

#define	EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)

#define	EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)

#define	EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)

#define	EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)

#define	EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)

#define	EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)

#define	EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)

#define	EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)

#define	EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)

#define	EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)

#define	EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)

#define	EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)

#define	EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)

#define	EXYNOS4_MPLL_LOCK

#define	EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)

#define	EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)

#define	EXYNOS4_MPLL_CON0

#define	EXYNOS4_MPLL_CON1

#define	EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)

#define	EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)

#define	EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)

#define	EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)

#define	EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)

#define	EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)

#define	EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)

#define	EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)

#define	EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)

#define	EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)

#define	EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */

#define	EXYNOS4_APLLCON0_ENABLE_SHIFT (31)

#define	EXYNOS4_APLLCON0_LOCKED_SHIFT (29)

#define	EXYNOS4_APLL_VAL_1000 ((250 << 16) \| (6 << 8) \| 1)

#define	EXYNOS4_APLL_VAL_800 ((200 << 16) \| (6 << 8) \| 1)

#define	EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)

#define	EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)

#define	EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)

#define	EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)

#define	EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)

#define	EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)

#define	EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)

#define	EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)

#define	EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)

#define	EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)

#define	EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)

#define	EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)

#define	EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)

#define	EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28

#define	EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)

#define	EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0

#define	EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)

#define	EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4

#define	EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)

#define	EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8

#define	EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)

#define	EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)

#define	EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)

#define	EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)

#define	EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)

#define	EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)

#define	EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)

#define	EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)

#define	EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)

#define	EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)

#define	EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)

#define	EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)

#define	EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)

#define	EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)

#define	EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)

#define	EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)

#define	EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)

#define	EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)

#define	EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)

#define	EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)

#define	EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)

#define	EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)

#define	EXYNOS4_CLKDIV_MFC_SHIFT (0)

#define	EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)

#define	EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)

#define	EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)

#define	EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)

#define	EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)

#define	EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)

#define	EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)

#define	EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)

#define	EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)

#define	EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)

#define	EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)

#define	EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)

#define	EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)

#define	EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)

#define	EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)

#define	EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)

#define	EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)

#define	EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)

#define	EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)

#define	EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)

#define	EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)

#define	EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)

#define	EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)

#define	EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)

#define	EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)

#define	EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)

#define	EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)

#define	EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)

#define	EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)

#define	EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)

#define	EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)

#define	EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)

#define	EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)

#define	EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)

#define	EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)

#define	EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)

#define	EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)

#define	EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)

#define	EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)

#define	EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)

#define	EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)

#define	EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)

#define	EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)

#define	EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)

#define	EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)

#define	EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)

#define	EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)

#define	EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)

#define	EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)

#define	EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)

#define	EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)

#define	EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)

#define	EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)

#define	EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)

#define	EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)

#define	EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)

#define	EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)

#define	EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)

#define	EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)

#define	EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)

#define	EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)

#define	EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)

#define	EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)

#define	EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)

#define	EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)

#define	EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)

#define	EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)

#define	EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)

#define	EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)

#define	EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)

#define	EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)

#define	EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)

#define	EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)

#define	EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)

#define	EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)

#define	EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)

#define	EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)

#define	EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)

#define	EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)

#define	EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)

#define	EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)

#define	EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)

#define	EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)

#define	EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)

#define	EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)

#define	EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)

#define	EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)

#define	EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)

#define	EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)

#define	EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)

#define	EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)

#define	EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)

#define	EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)

#define	EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)

#define	EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)

#define	EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)

#define	EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)

#define	EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)

#define	EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)

#define	EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)

#define	EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)

#define	EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)

#define	S5P_EPLL_CON EXYNOS4_EPLL_CON0

Macro Definition Documentation

#define __ASM_ARCH_REGS_CLOCK_H __FILE__

Definition at line 14 of file regs-clock.h.

#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)

Definition at line 247 of file regs-clock.h.

#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)

Definition at line 90 of file regs-clock.h.

#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)

Definition at line 248 of file regs-clock.h.

#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)

Definition at line 99 of file regs-clock.h.

#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)

Definition at line 245 of file regs-clock.h.

#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)

Definition at line 246 of file regs-clock.h.

#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)

Definition at line 91 of file regs-clock.h.

#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)

Definition at line 100 of file regs-clock.h.

#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)

Definition at line 118 of file regs-clock.h.

#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)

Definition at line 119 of file regs-clock.h.

#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)

Definition at line 114 of file regs-clock.h.

#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */

Definition at line 141 of file regs-clock.h.

#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)

Definition at line 145 of file regs-clock.h.

#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)

Definition at line 146 of file regs-clock.h.

#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)

Definition at line 143 of file regs-clock.h.

#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)

Definition at line 144 of file regs-clock.h.

#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)

Definition at line 77 of file regs-clock.h.

#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)

Definition at line 230 of file regs-clock.h.

#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)

Definition at line 229 of file regs-clock.h.

#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)

Definition at line 232 of file regs-clock.h.

#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)

Definition at line 231 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)

Definition at line 60 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)

Definition at line 252 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)

Definition at line 257 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)

Definition at line 256 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)

Definition at line 235 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)

Definition at line 234 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)

Definition at line 237 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)

Definition at line 236 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)

Definition at line 239 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)

Definition at line 238 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)

Definition at line 241 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)

Definition at line 240 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)

Definition at line 130 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)

Definition at line 170 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)

Definition at line 169 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)

Definition at line 166 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)

Definition at line 165 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)

Definition at line 172 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28

Definition at line 171 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)

Definition at line 158 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)

Definition at line 157 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)

Definition at line 160 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)

Definition at line 159 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)

Definition at line 162 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)

Definition at line 161 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)

Definition at line 168 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)

Definition at line 167 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)

Definition at line 164 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)

Definition at line 163 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)

Definition at line 131 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)

Definition at line 175 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0

Definition at line 174 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)

Definition at line 179 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8

Definition at line 178 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)

Definition at line 177 of file regs-clock.h.

#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4

Definition at line 176 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)

Definition at line 105 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)

Definition at line 182 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)

Definition at line 181 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)

Definition at line 184 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)

Definition at line 183 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)

Definition at line 194 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)

Definition at line 193 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)

Definition at line 196 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)

Definition at line 195 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)

Definition at line 188 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)

Definition at line 187 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)

Definition at line 190 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)

Definition at line 189 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)

Definition at line 192 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)

Definition at line 191 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)

Definition at line 186 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)

Definition at line 185 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)

Definition at line 106 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)

Definition at line 201 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)

Definition at line 200 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)

Definition at line 205 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)

Definition at line 204 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)

Definition at line 209 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)

Definition at line 208 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)

Definition at line 207 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)

Definition at line 206 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)

Definition at line 199 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)

Definition at line 198 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)

Definition at line 203 of file regs-clock.h.

#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)

Definition at line 202 of file regs-clock.h.

#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)

Definition at line 67 of file regs-clock.h.

#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)

Definition at line 68 of file regs-clock.h.

#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)

Definition at line 69 of file regs-clock.h.

#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)

Definition at line 70 of file regs-clock.h.

#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)

Definition at line 63 of file regs-clock.h.

#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)

Definition at line 64 of file regs-clock.h.

#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)

Definition at line 65 of file regs-clock.h.

#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)

Definition at line 21 of file regs-clock.h.

#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)

Definition at line 66 of file regs-clock.h.

#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)

Definition at line 62 of file regs-clock.h.

#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)

Definition at line 212 of file regs-clock.h.

#define EXYNOS4_CLKDIV_MFC_SHIFT (0)

Definition at line 211 of file regs-clock.h.

#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)

Definition at line 71 of file regs-clock.h.

#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)

Definition at line 72 of file regs-clock.h.

#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)

Definition at line 73 of file regs-clock.h.

#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)

Definition at line 74 of file regs-clock.h.

#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)

Definition at line 75 of file regs-clock.h.

#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)

Definition at line 76 of file regs-clock.h.

#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)

Definition at line 25 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)

Definition at line 254 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)

Definition at line 107 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)

Definition at line 108 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)

Definition at line 22 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)

Definition at line 80 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)

Definition at line 26 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)

Definition at line 79 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)

Definition at line 132 of file regs-clock.h.

#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)

Definition at line 133 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)

Definition at line 59 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)

Definition at line 217 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)

Definition at line 216 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)

Definition at line 221 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)

Definition at line 220 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)

Definition at line 219 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)

Definition at line 218 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)

Definition at line 215 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)

Definition at line 214 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)

Definition at line 225 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)

Definition at line 224 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)

Definition at line 227 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)

Definition at line 226 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)

Definition at line 223 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)

Definition at line 222 of file regs-clock.h.

#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)

Definition at line 61 of file regs-clock.h.

#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)

Definition at line 101 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)

Definition at line 83 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)

Definition at line 136 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)

Definition at line 109 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)

Definition at line 93 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)

Definition at line 86 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)

Definition at line 94 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_IMAGE

Value:

(soc_is_exynos4210() ? \
                        EXYNOS_CLKREG(0x0C930) : \
                        EXYNOS_CLKREG(0x04930))

Definition at line 87 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)

Definition at line 138 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)

Definition at line 139 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)

Definition at line 92 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)

Definition at line 23 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)

Definition at line 85 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)

Definition at line 95 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_PERIR

Value:

(soc_is_exynos4210() ? \
                        EXYNOS_CLKREG(0x0C960) : \
                        EXYNOS_CLKREG(0x08960))

Definition at line 96 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)

Definition at line 27 of file regs-clock.h.

#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)

Definition at line 84 of file regs-clock.h.

#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)

Definition at line 82 of file regs-clock.h.

#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)

Definition at line 135 of file regs-clock.h.

#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)

Definition at line 128 of file regs-clock.h.

#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)

Definition at line 155 of file regs-clock.h.

#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)

Definition at line 39 of file regs-clock.h.

#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)

Definition at line 127 of file regs-clock.h.

#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)

Definition at line 154 of file regs-clock.h.

#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)

Definition at line 104 of file regs-clock.h.

#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)

Definition at line 46 of file regs-clock.h.

#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)

Definition at line 42 of file regs-clock.h.

#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)

Definition at line 43 of file regs-clock.h.

#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)

Definition at line 44 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)

Definition at line 51 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)

Definition at line 103 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)

Definition at line 55 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)

Definition at line 53 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)

Definition at line 54 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)

Definition at line 56 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)

Definition at line 57 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)

Definition at line 50 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)

Definition at line 52 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)

Definition at line 45 of file regs-clock.h.

#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)

Definition at line 41 of file regs-clock.h.

#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)

Definition at line 47 of file regs-clock.h.

#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)

Definition at line 48 of file regs-clock.h.

#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)

Definition at line 37 of file regs-clock.h.

#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)

Definition at line 38 of file regs-clock.h.

#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)

Definition at line 40 of file regs-clock.h.

#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)

Definition at line 111 of file regs-clock.h.

#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)

Definition at line 112 of file regs-clock.h.

#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)

Definition at line 32 of file regs-clock.h.

#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)

Definition at line 33 of file regs-clock.h.

#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)

Definition at line 29 of file regs-clock.h.

#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)

Definition at line 148 of file regs-clock.h.

#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)

Definition at line 149 of file regs-clock.h.

#define EXYNOS4_MPLL_CON0

Value:

(soc_is_exynos4210() ? \
                        EXYNOS_CLKREG(0x14108) : \
                        EXYNOS_CLKREG(0x10108))

Definition at line 120 of file regs-clock.h.

#define EXYNOS4_MPLL_CON1

Value:

(soc_is_exynos4210() ? \
                        EXYNOS_CLKREG(0x1410C) : \
                        EXYNOS_CLKREG(0x1010C))

Definition at line 123 of file regs-clock.h.

#define EXYNOS4_MPLL_LOCK

Value:

(soc_is_exynos4210() ? \
                        EXYNOS_CLKREG(0x14004) :  \
                        EXYNOS_CLKREG(0x10008))

Definition at line 115 of file regs-clock.h.

#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)

Definition at line 34 of file regs-clock.h.

#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)

Definition at line 35 of file regs-clock.h.

#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)

Definition at line 30 of file regs-clock.h.

#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)

Definition at line 151 of file regs-clock.h.

#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)

Definition at line 152 of file regs-clock.h.

#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)

Definition at line 262 of file regs-clock.h.

#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)

Definition at line 261 of file regs-clock.h.

#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)

Definition at line 337 of file regs-clock.h.

#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)

Definition at line 275 of file regs-clock.h.

#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)

Definition at line 339 of file regs-clock.h.

#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)

Definition at line 265 of file regs-clock.h.

#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)

Definition at line 266 of file regs-clock.h.

#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)

Definition at line 308 of file regs-clock.h.

#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)

Definition at line 311 of file regs-clock.h.

#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)

Definition at line 312 of file regs-clock.h.

#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)

Definition at line 313 of file regs-clock.h.

#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)

Definition at line 314 of file regs-clock.h.

#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)

Definition at line 309 of file regs-clock.h.

#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)

Definition at line 307 of file regs-clock.h.

#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)

Definition at line 310 of file regs-clock.h.

#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)

Definition at line 315 of file regs-clock.h.

#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)

Definition at line 316 of file regs-clock.h.

#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)

Definition at line 317 of file regs-clock.h.

#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)

Definition at line 318 of file regs-clock.h.

#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)

Definition at line 319 of file regs-clock.h.

#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)

Definition at line 320 of file regs-clock.h.

#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)

Definition at line 267 of file regs-clock.h.

#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)

Definition at line 268 of file regs-clock.h.

#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)

Definition at line 305 of file regs-clock.h.

#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)

Definition at line 306 of file regs-clock.h.

#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)

Definition at line 335 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)

Definition at line 323 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)

Definition at line 273 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)

Definition at line 327 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)

Definition at line 331 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)

Definition at line 329 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)

Definition at line 330 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)

Definition at line 332 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)

Definition at line 326 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)

Definition at line 324 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)

Definition at line 325 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)

Definition at line 328 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)

Definition at line 333 of file regs-clock.h.

#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)

Definition at line 334 of file regs-clock.h.

#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)

Definition at line 264 of file regs-clock.h.

#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)

Definition at line 338 of file regs-clock.h.

#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)

Definition at line 271 of file regs-clock.h.

#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)

Definition at line 263 of file regs-clock.h.

#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)

Definition at line 290 of file regs-clock.h.

#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)

Definition at line 292 of file regs-clock.h.

#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)

Definition at line 289 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)

Definition at line 299 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)

Definition at line 301 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)

Definition at line 298 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)

Definition at line 300 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)

Definition at line 302 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)

Definition at line 303 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)

Definition at line 297 of file regs-clock.h.

#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)

Definition at line 291 of file regs-clock.h.

#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)

Definition at line 293 of file regs-clock.h.

#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)

Definition at line 294 of file regs-clock.h.

#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)

Definition at line 285 of file regs-clock.h.

#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)

Definition at line 286 of file regs-clock.h.

#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)

Definition at line 287 of file regs-clock.h.

#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)

Definition at line 288 of file regs-clock.h.

#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)

Definition at line 283 of file regs-clock.h.

#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)

Definition at line 277 of file regs-clock.h.

#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)

Definition at line 278 of file regs-clock.h.

#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)

Definition at line 279 of file regs-clock.h.

#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)

Definition at line 343 of file regs-clock.h.

#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)

Definition at line 345 of file regs-clock.h.

#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)

Definition at line 270 of file regs-clock.h.

#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)

Definition at line 341 of file regs-clock.h.

#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)

Definition at line 321 of file regs-clock.h.

#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)

Definition at line 295 of file regs-clock.h.

#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)

Definition at line 280 of file regs-clock.h.

#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)

Definition at line 281 of file regs-clock.h.

#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)

Definition at line 282 of file regs-clock.h.

#define EXYNOS_CLKREG ( x ) (S5P_VA_CMU + (x))

Definition at line 19 of file regs-clock.h.

#define S5P_EPLL_CON EXYNOS4_EPLL_CON0

Definition at line 351 of file regs-clock.h.

Macros

Macro Definition Documentation