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11 #ifndef __ASM_ARCH_BRIDGE_REGS_H
12 #define __ASM_ARCH_BRIDGE_REGS_H
16 #define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
17 #define CPU_CONFIG_ERROR_PROP 0x00000004
19 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
20 #define CPU_RESET 0x00000002
22 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
23 #define WDT_RESET_OUT_EN 0x00000002
24 #define SOFT_RESET_OUT_EN 0x00000004
26 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
27 #define SOFT_RESET 0x00000001
29 #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
30 #define WDT_INT_REQ 0x0008
32 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
34 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
35 #define IRQ_CAUSE_LOW_OFF 0x0000
36 #define IRQ_MASK_LOW_OFF 0x0004
37 #define IRQ_CAUSE_HIGH_OFF 0x0010
38 #define IRQ_MASK_HIGH_OFF 0x0014
40 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
41 #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
43 #define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
44 #define L2_WRITETHROUGH 0x00000010
46 #define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
47 #define CGC_BIT_GE0 (0)
48 #define CGC_BIT_PEX0 (2)
49 #define CGC_BIT_USB0 (3)
50 #define CGC_BIT_SDIO (4)
51 #define CGC_BIT_TSU (5)
52 #define CGC_BIT_DUNIT (6)
53 #define CGC_BIT_RUNIT (7)
54 #define CGC_BIT_XOR0 (8)
55 #define CGC_BIT_AUDIO (9)
56 #define CGC_BIT_SATA0 (14)
57 #define CGC_BIT_SATA1 (15)
58 #define CGC_BIT_XOR1 (16)
59 #define CGC_BIT_CRYPTO (17)
60 #define CGC_BIT_PEX1 (18)
61 #define CGC_BIT_GE1 (19)
62 #define CGC_BIT_TDM (20)
63 #define CGC_GE0 (1 << 0)
64 #define CGC_PEX0 (1 << 2)
65 #define CGC_USB0 (1 << 3)
66 #define CGC_SDIO (1 << 4)
67 #define CGC_TSU (1 << 5)
68 #define CGC_DUNIT (1 << 6)
69 #define CGC_RUNIT (1 << 7)
70 #define CGC_XOR0 (1 << 8)
71 #define CGC_AUDIO (1 << 9)
72 #define CGC_SATA0 (1 << 14)
73 #define CGC_SATA1 (1 << 15)
74 #define CGC_XOR1 (1 << 16)
75 #define CGC_CRYPTO (1 << 17)
76 #define CGC_PEX1 (1 << 18)
77 #define CGC_GE1 (1 << 19)
78 #define CGC_TDM (1 << 20)
79 #define CGC_RESERVED (0x6 << 21)