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9 #ifndef __ASM_ARCH_BRIDGE_REGS_H
10 #define __ASM_ARCH_BRIDGE_REGS_H
14 #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
15 #define L2_WRITETHROUGH 0x00020000
17 #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
18 #define SOFT_RESET_OUT_EN 0x00000004
20 #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
21 #define SOFT_RESET 0x00000001
23 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
25 #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
26 #define IRQ_CAUSE_ERR_OFF 0x0000
27 #define IRQ_CAUSE_LOW_OFF 0x0004
28 #define IRQ_CAUSE_HIGH_OFF 0x0008
29 #define IRQ_MASK_ERR_OFF 0x000c
30 #define IRQ_MASK_LOW_OFF 0x0010
31 #define IRQ_MASK_HIGH_OFF 0x0014
33 #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
34 #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)