Linux Kernel
3.7.1
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#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE) |
#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE) |
#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000) |
#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500) |
#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570) |
#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000) |
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000) |
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000) |
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000) |
#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000) |
#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000) |
#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100) |
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000) |
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100) |
#define MV78XX0_PCIE_IO_PHYS_BASE | ( | i | ) | (0xf0800000 + ((i) << 20)) |
#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000) |
#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000) |
#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000) |
#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000) |
#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000) |
#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000) |
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000) |
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000) |
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034) |
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030) |
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000) |
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000) |
#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000) |
#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100) |
#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100) |
#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200) |
#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200) |
#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300) |
#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300) |
#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000) |
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000) |
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000) |