war.h File Reference

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Macros
#define	R4600_V1_INDEX_ICACHEOP_WAR   0
#define	R4600_V1_HIT_CACHEOP_WAR   0
#define	R4600_V2_HIT_CACHEOP_WAR   0
#define	R5432_CP0_INTERRUPT_WAR   0
#define	BCM1250_M3_WAR   0
#define	SIBYTE_1956_WAR   0
#define	MIPS4K_ICACHE_REFILL_WAR   0
#define	MIPS_CACHE_SYNC_WAR   0
#define	TX49XX_ICACHE_INDEX_INV_WAR   0
#define	RM9000_CDEX_SMP_WAR   0
#define	ICACHE_REFILLS_WORKAROUND_WAR   0
#define	R10000_LLSC_WAR   0
#define	MIPS34K_MISSED_ITLB_WAR   0

Macro Definition Documentation

#define BCM1250_M3_WAR   0

Definition at line 28 of file war.h.

#define ICACHE_REFILLS_WORKAROUND_WAR   0

Definition at line 37 of file war.h.

#define MIPS34K_MISSED_ITLB_WAR   0

Definition at line 39 of file war.h.

#define MIPS4K_ICACHE_REFILL_WAR   0

Definition at line 33 of file war.h.

#define MIPS_CACHE_SYNC_WAR   0

Definition at line 34 of file war.h.

#define R10000_LLSC_WAR   0

Definition at line 38 of file war.h.

#define R4600_V1_HIT_CACHEOP_WAR   0

Definition at line 12 of file war.h.

#define R4600_V1_INDEX_ICACHEOP_WAR   0

Definition at line 11 of file war.h.

#define R4600_V2_HIT_CACHEOP_WAR   0

Definition at line 13 of file war.h.

#define R5432_CP0_INTERRUPT_WAR   0

Definition at line 14 of file war.h.

#define RM9000_CDEX_SMP_WAR   0

Definition at line 36 of file war.h.

#define SIBYTE_1956_WAR   0

Definition at line 29 of file war.h.

#define TX49XX_ICACHE_INDEX_INV_WAR   0

Definition at line 35 of file war.h.