Linux Kernel  3.7.1
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cache-l2x0.c
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1 /*
2  * Copyright (C) ST-Ericsson SA 2011
3  *
4  * License terms: GNU General Public License (GPL) version 2
5  */
6 
7 #include <linux/io.h>
8 #include <linux/of.h>
9 
10 #include <asm/cacheflush.h>
12 #include <mach/hardware.h>
13 #include <mach/id.h>
14 
15 static void __iomem *l2x0_base;
16 
17 static int __init ux500_l2x0_unlock(void)
18 {
19  int i;
20 
21  /*
22  * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
23  * apparently locks both caches before jumping to the kernel. The
24  * l2x0 core will not touch the unlock registers if the l2x0 is
25  * already enabled, so we do it right here instead. The PL310 has
26  * 8 sets of registers, one per possible CPU.
27  */
28  for (i = 0; i < 8; i++) {
29  writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
31  writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
33  }
34  return 0;
35 }
36 
37 static int __init ux500_l2x0_init(void)
38 {
39  u32 aux_val = 0x3e000000;
40 
41  if (cpu_is_u8500_family() || cpu_is_ux540_family())
42  l2x0_base = __io_address(U8500_L2CC_BASE);
43  else
45 
46  /* Unlock before init */
47  ux500_l2x0_unlock();
48 
49  /* DB9540's L2 has 128KB way size */
50  if (cpu_is_u9540())
51  /* 128KB way size */
52  aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
53  else
54  /* 64KB way size */
55  aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
56 
57  /* 64KB way size, 8 way associativity, force WA */
58  if (of_have_populated_dt())
59  l2x0_of_init(aux_val, 0xc0000fff);
60  else
61  l2x0_init(l2x0_base, aux_val, 0xc0000fff);
62 
63  /*
64  * We can't disable l2 as we are in non secure mode, currently
65  * this seems be called only during kexec path. So let's
66  * override outer.disable with nasty assignment until we have
67  * some SMI service available.
68  */
69  outer_cache.disable = NULL;
70 
71  return 0;
72 }
73 
74 early_initcall(ux500_l2x0_init);