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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | MB862XX_MMIO_BASE 0x01fc0000 |
| #define | MB862XX_MMIO_HIGH_BASE 0x03fc0000 |
| #define | MB862XX_I2C_BASE 0x0000c000 |
| #define | MB862XX_DISP_BASE 0x00010000 |
| #define | MB862XX_CAP_BASE 0x00018000 |
| #define | MB862XX_DRAW_BASE 0x00030000 |
| #define | MB862XX_GEO_BASE 0x00038000 |
| #define | MB862XX_PIO_BASE 0x00038000 |
| #define | MB862XX_MMIO_SIZE 0x40000 |
| #define | GC_IST 0x00000020 |
| #define | GC_IMASK 0x00000024 |
| #define | GC_SRST 0x0000002c |
| #define | GC_CCF 0x00000038 |
| #define | GC_RSW 0x0000005c |
| #define | GC_CID 0x000000f0 |
| #define | GC_REVISION 0x00000084 |
| #define | GC_CCF_CGE_100 0x00000000 |
| #define | GC_CCF_CGE_133 0x00040000 |
| #define | GC_CCF_CGE_166 0x00080000 |
| #define | GC_CCF_COT_100 0x00000000 |
| #define | GC_CCF_COT_133 0x00010000 |
| #define | GC_CID_CNAME_MSK 0x0000ff00 |
| #define | GC_CID_VERSION_MSK 0x000000ff |
| #define | GC_INT_EN 0x00000000 |
| #define | GC_MMR 0x0000fffc |
| #define | GC_DCM0 0x00000000 |
| #define | GC_HTP 0x00000004 |
| #define | GC_HDB_HDP 0x00000008 |
| #define | GC_VSW_HSW_HSP 0x0000000c |
| #define | GC_VTR 0x00000010 |
| #define | GC_VDP_VSP 0x00000014 |
| #define | GC_WY_WX 0x00000018 |
| #define | GC_WH_WW 0x0000001c |
| #define | GC_L0M 0x00000020 |
| #define | GC_L0OA0 0x00000024 |
| #define | GC_L0DA0 0x00000028 |
| #define | GC_L0DY_L0DX 0x0000002c |
| #define | GC_L1M 0x00000030 |
| #define | GC_L1DA 0x00000034 |
| #define | GC_DCM1 0x00000100 |
| #define | GC_L0EM 0x00000110 |
| #define | GC_L0WY_L0WX 0x00000114 |
| #define | GC_L0WH_L0WW 0x00000118 |
| #define | GC_L1EM 0x00000120 |
| #define | GC_L1WY_L1WX 0x00000124 |
| #define | GC_L1WH_L1WW 0x00000128 |
| #define | GC_DLS 0x00000180 |
| #define | GC_DCM2 0x00000104 |
| #define | GC_DCM3 0x00000108 |
| #define | GC_CPM_CUTC 0x000000a0 |
| #define | GC_CUOA0 0x000000a4 |
| #define | GC_CUY0_CUX0 0x000000a8 |
| #define | GC_CUOA1 0x000000ac |
| #define | GC_CUY1_CUX1 0x000000b0 |
| #define | GC_L0PAL0 0x00000400 |
| #define | GC_CPM_CEN0 0x00100000 |
| #define | GC_CPM_CEN1 0x00200000 |
| #define | GC_DCM1_DEN 0x80000000 |
| #define | GC_DCM1_L1E 0x00020000 |
| #define | GC_L1M_16 0x80000000 |
| #define | GC_L1M_YC 0x40000000 |
| #define | GC_L1M_CS 0x20000000 |
| #define | GC_DCM01_ESY 0x00000004 |
| #define | GC_DCM01_SC 0x00003f00 |
| #define | GC_DCM01_RESV 0x00004000 |
| #define | GC_DCM01_CKS 0x00008000 |
| #define | GC_DCM01_L0E 0x00010000 |
| #define | GC_DCM01_DEN 0x80000000 |
| #define | GC_L0M_L0C_8 0x00000000 |
| #define | GC_L0M_L0C_16 0x80000000 |
| #define | GC_L0EM_L0EC_24 0x40000000 |
| #define | GC_L0M_L0W_UNIT 64 |
| #define | GC_L1EM_DM 0x02000000 |
| #define | GC_DISP_REFCLK_400 400 |
| #define | GC_I2C_BSR 0x00000000 /* BSR */ |
| #define | GC_I2C_BCR 0x00000004 /* BCR */ |
| #define | GC_I2C_CCR 0x00000008 /* CCR */ |
| #define | GC_I2C_ADR 0x0000000C /* ADR */ |
| #define | GC_I2C_DAR 0x00000010 /* DAR */ |
| #define | I2C_DISABLE 0x00000000 |
| #define | I2C_STOP 0x00000000 |
| #define | I2C_START 0x00000010 |
| #define | I2C_REPEATED_START 0x00000030 |
| #define | I2C_CLOCK_AND_ENABLE 0x0000003f |
| #define | I2C_READY 0x01 |
| #define | I2C_INT 0x01 |
| #define | I2C_INTE 0x02 |
| #define | I2C_ACK 0x08 |
| #define | I2C_BER 0x80 |
| #define | I2C_BEIE 0x40 |
| #define | I2C_TRX 0x80 |
| #define | I2C_LRB 0x10 |
| #define | GC_CAP_VCM 0x00000000 |
| #define | GC_CAP_CSC 0x00000004 |
| #define | GC_CAP_VCS 0x00000008 |
| #define | GC_CAP_CBM 0x00000010 |
| #define | GC_CAP_CBOA 0x00000014 |
| #define | GC_CAP_CBLA 0x00000018 |
| #define | GC_CAP_IMG_START 0x0000001C |
| #define | GC_CAP_IMG_END 0x00000020 |
| #define | GC_CAP_CMSS 0x00000048 |
| #define | GC_CAP_CMDS 0x0000004C |
| #define | GC_VCM_VIE 0x80000000 |
| #define | GC_VCM_CM 0x03000000 |
| #define | GC_VCM_VS_PAL 0x00000002 |
| #define | GC_CBM_OO 0x80000000 |
| #define | GC_CBM_HRV 0x00000010 |
| #define | GC_CBM_CBST 0x00000001 |
| #define | MB86297_DRAW_BASE 0x00020000 |
| #define | MB86297_DISP0_BASE 0x00100000 |
| #define | MB86297_DISP1_BASE 0x00140000 |
| #define | MB86297_WRBACK_BASE 0x00180000 |
| #define | MB86297_CAP0_BASE 0x00200000 |
| #define | MB86297_CAP1_BASE 0x00280000 |
| #define | MB86297_DRAMCTRL_BASE 0x00300000 |
| #define | MB86297_CTRL_BASE 0x00400000 |
| #define | MB86297_I2C_BASE 0x00500000 |
| #define | GC_CTRL_STATUS 0x00000000 |
| #define | GC_CTRL_INT_MASK 0x00000004 |
| #define | GC_CTRL_CLK_ENABLE 0x0000000c |
| #define | GC_CTRL_SOFT_RST 0x00000010 |
| #define | GC_CTRL_CLK_EN_DRAM 0x00000001 |
| #define | GC_CTRL_CLK_EN_2D3D 0x00000002 |
| #define | GC_CTRL_CLK_EN_DISP0 0x00000020 |
| #define | GC_CTRL_CLK_EN_DISP1 0x00000040 |
| #define | GC_2D3D_REV 0x000004b4 |
| #define | GC_RE_REVISION 0x24240200 |
| #define | GC_CARMINE_INT_EN 0x00000004 |
| #define | GC_DCTL_MODE_ADD 0x00000000 |
| #define | GC_DCTL_SETTIME1_EMODE 0x00000004 |
| #define | GC_DCTL_REFRESH_SETTIME2 0x00000008 |
| #define | GC_DCTL_RSV0_STATES 0x0000000C |
| #define | GC_DCTL_RSV2_RSV1 0x00000010 |
| #define | GC_DCTL_DDRIF2_DDRIF1 0x00000014 |
| #define | GC_DCTL_IOCONT1_IOCONT0 0x00000024 |
| #define | GC_DCTL_STATES_MSK 0x0000000f |
| #define | GC_DCTL_INIT_WAIT_CNT 3000 |
| #define | GC_DCTL_INIT_WAIT_INTERVAL 1 |
| #define | GC_EVB_DCTL_MODE_ADD 0x012105c3 |
| #define | GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3 |
| #define | GC_EVB_DCTL_SETTIME1_EMODE 0x47498000 |
| #define | GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22 |
| #define | GC_EVB_DCTL_RSV0_STATES 0x00200003 |
| #define | GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002 |
| #define | GC_EVB_DCTL_RSV2_RSV1 0x0000000f |
| #define | GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646 |
| #define | GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555 |
| #define | GC_DISP_REFCLK_533 533 |
| #define GC_2D3D_REV 0x000004b4 |
Definition at line 156 of file mb862xx_reg.h.
| #define GC_CAP_CBLA 0x00000018 |
Definition at line 122 of file mb862xx_reg.h.
| #define GC_CAP_CBM 0x00000010 |
Definition at line 120 of file mb862xx_reg.h.
| #define GC_CAP_CBOA 0x00000014 |
Definition at line 121 of file mb862xx_reg.h.
| #define GC_CAP_CMDS 0x0000004C |
Definition at line 126 of file mb862xx_reg.h.
| #define GC_CAP_CMSS 0x00000048 |
Definition at line 125 of file mb862xx_reg.h.
| #define GC_CAP_CSC 0x00000004 |
Definition at line 118 of file mb862xx_reg.h.
| #define GC_CAP_IMG_END 0x00000020 |
Definition at line 124 of file mb862xx_reg.h.
| #define GC_CAP_IMG_START 0x0000001C |
Definition at line 123 of file mb862xx_reg.h.
| #define GC_CAP_VCM 0x00000000 |
Definition at line 117 of file mb862xx_reg.h.
| #define GC_CAP_VCS 0x00000008 |
Definition at line 119 of file mb862xx_reg.h.
| #define GC_CARMINE_INT_EN 0x00000004 |
Definition at line 160 of file mb862xx_reg.h.
| #define GC_CBM_CBST 0x00000001 |
Definition at line 133 of file mb862xx_reg.h.
| #define GC_CBM_HRV 0x00000010 |
Definition at line 132 of file mb862xx_reg.h.
| #define GC_CBM_OO 0x80000000 |
Definition at line 131 of file mb862xx_reg.h.
| #define GC_CCF 0x00000038 |
Definition at line 22 of file mb862xx_reg.h.
| #define GC_CCF_CGE_100 0x00000000 |
Definition at line 27 of file mb862xx_reg.h.
| #define GC_CCF_CGE_133 0x00040000 |
Definition at line 28 of file mb862xx_reg.h.
| #define GC_CCF_CGE_166 0x00080000 |
Definition at line 29 of file mb862xx_reg.h.
| #define GC_CCF_COT_100 0x00000000 |
Definition at line 30 of file mb862xx_reg.h.
| #define GC_CCF_COT_133 0x00010000 |
Definition at line 31 of file mb862xx_reg.h.
| #define GC_CID 0x000000f0 |
Definition at line 24 of file mb862xx_reg.h.
| #define GC_CID_CNAME_MSK 0x0000ff00 |
Definition at line 32 of file mb862xx_reg.h.
| #define GC_CID_VERSION_MSK 0x000000ff |
Definition at line 33 of file mb862xx_reg.h.
| #define GC_CPM_CEN0 0x00100000 |
Definition at line 73 of file mb862xx_reg.h.
| #define GC_CPM_CEN1 0x00200000 |
Definition at line 74 of file mb862xx_reg.h.
| #define GC_CPM_CUTC 0x000000a0 |
Definition at line 66 of file mb862xx_reg.h.
| #define GC_CTRL_CLK_EN_2D3D 0x00000002 |
Definition at line 152 of file mb862xx_reg.h.
| #define GC_CTRL_CLK_EN_DISP0 0x00000020 |
Definition at line 153 of file mb862xx_reg.h.
| #define GC_CTRL_CLK_EN_DISP1 0x00000040 |
Definition at line 154 of file mb862xx_reg.h.
| #define GC_CTRL_CLK_EN_DRAM 0x00000001 |
Definition at line 151 of file mb862xx_reg.h.
| #define GC_CTRL_CLK_ENABLE 0x0000000c |
Definition at line 148 of file mb862xx_reg.h.
| #define GC_CTRL_INT_MASK 0x00000004 |
Definition at line 147 of file mb862xx_reg.h.
| #define GC_CTRL_SOFT_RST 0x00000010 |
Definition at line 149 of file mb862xx_reg.h.
| #define GC_CTRL_STATUS 0x00000000 |
Definition at line 146 of file mb862xx_reg.h.
| #define GC_CUOA0 0x000000a4 |
Definition at line 67 of file mb862xx_reg.h.
| #define GC_CUOA1 0x000000ac |
Definition at line 69 of file mb862xx_reg.h.
| #define GC_CUY0_CUX0 0x000000a8 |
Definition at line 68 of file mb862xx_reg.h.
| #define GC_CUY1_CUX1 0x000000b0 |
Definition at line 70 of file mb862xx_reg.h.
| #define GC_DCM0 0x00000000 |
Definition at line 42 of file mb862xx_reg.h.
| #define GC_DCM01_CKS 0x00008000 |
Definition at line 84 of file mb862xx_reg.h.
| #define GC_DCM01_DEN 0x80000000 |
Definition at line 86 of file mb862xx_reg.h.
| #define GC_DCM01_ESY 0x00000004 |
Definition at line 81 of file mb862xx_reg.h.
| #define GC_DCM01_L0E 0x00010000 |
Definition at line 85 of file mb862xx_reg.h.
| #define GC_DCM01_RESV 0x00004000 |
Definition at line 83 of file mb862xx_reg.h.
| #define GC_DCM01_SC 0x00003f00 |
Definition at line 82 of file mb862xx_reg.h.
| #define GC_DCM1 0x00000100 |
Definition at line 56 of file mb862xx_reg.h.
| #define GC_DCM1_DEN 0x80000000 |
Definition at line 75 of file mb862xx_reg.h.
| #define GC_DCM1_L1E 0x00020000 |
Definition at line 76 of file mb862xx_reg.h.
| #define GC_DCM2 0x00000104 |
Definition at line 64 of file mb862xx_reg.h.
| #define GC_DCM3 0x00000108 |
Definition at line 65 of file mb862xx_reg.h.
| #define GC_DCTL_DDRIF2_DDRIF1 0x00000014 |
Definition at line 168 of file mb862xx_reg.h.
| #define GC_DCTL_INIT_WAIT_CNT 3000 |
Definition at line 172 of file mb862xx_reg.h.
| #define GC_DCTL_INIT_WAIT_INTERVAL 1 |
Definition at line 173 of file mb862xx_reg.h.
| #define GC_DCTL_IOCONT1_IOCONT0 0x00000024 |
Definition at line 169 of file mb862xx_reg.h.
| #define GC_DCTL_MODE_ADD 0x00000000 |
Definition at line 163 of file mb862xx_reg.h.
| #define GC_DCTL_REFRESH_SETTIME2 0x00000008 |
Definition at line 165 of file mb862xx_reg.h.
| #define GC_DCTL_RSV0_STATES 0x0000000C |
Definition at line 166 of file mb862xx_reg.h.
| #define GC_DCTL_RSV2_RSV1 0x00000010 |
Definition at line 167 of file mb862xx_reg.h.
| #define GC_DCTL_SETTIME1_EMODE 0x00000004 |
Definition at line 164 of file mb862xx_reg.h.
| #define GC_DCTL_STATES_MSK 0x0000000f |
Definition at line 171 of file mb862xx_reg.h.
| #define GC_DISP_REFCLK_400 400 |
Definition at line 93 of file mb862xx_reg.h.
| #define GC_DISP_REFCLK_533 533 |
Definition at line 186 of file mb862xx_reg.h.
| #define GC_DLS 0x00000180 |
Definition at line 63 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646 |
Definition at line 183 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555 |
Definition at line 184 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_MODE_ADD 0x012105c3 |
Definition at line 176 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3 |
Definition at line 177 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22 |
Definition at line 179 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_RSV0_STATES 0x00200003 |
Definition at line 180 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002 |
Definition at line 181 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_RSV2_RSV1 0x0000000f |
Definition at line 182 of file mb862xx_reg.h.
| #define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000 |
Definition at line 178 of file mb862xx_reg.h.
| #define GC_HDB_HDP 0x00000008 |
Definition at line 44 of file mb862xx_reg.h.
| #define GC_HTP 0x00000004 |
Definition at line 43 of file mb862xx_reg.h.
| #define GC_I2C_ADR 0x0000000C /* ADR */ |
Definition at line 99 of file mb862xx_reg.h.
| #define GC_I2C_BCR 0x00000004 /* BCR */ |
Definition at line 97 of file mb862xx_reg.h.
| #define GC_I2C_BSR 0x00000000 /* BSR */ |
Definition at line 96 of file mb862xx_reg.h.
| #define GC_I2C_CCR 0x00000008 /* CCR */ |
Definition at line 98 of file mb862xx_reg.h.
| #define GC_I2C_DAR 0x00000010 /* DAR */ |
Definition at line 100 of file mb862xx_reg.h.
| #define GC_IMASK 0x00000024 |
Definition at line 20 of file mb862xx_reg.h.
| #define GC_INT_EN 0x00000000 |
Definition at line 36 of file mb862xx_reg.h.
| #define GC_IST 0x00000020 |
Definition at line 19 of file mb862xx_reg.h.
| #define GC_L0DA0 0x00000028 |
Definition at line 52 of file mb862xx_reg.h.
| #define GC_L0DY_L0DX 0x0000002c |
Definition at line 53 of file mb862xx_reg.h.
| #define GC_L0EM 0x00000110 |
Definition at line 57 of file mb862xx_reg.h.
| #define GC_L0EM_L0EC_24 0x40000000 |
Definition at line 89 of file mb862xx_reg.h.
| #define GC_L0M 0x00000020 |
Definition at line 50 of file mb862xx_reg.h.
| #define GC_L0M_L0C_16 0x80000000 |
Definition at line 88 of file mb862xx_reg.h.
| #define GC_L0M_L0C_8 0x00000000 |
Definition at line 87 of file mb862xx_reg.h.
| #define GC_L0M_L0W_UNIT 64 |
Definition at line 90 of file mb862xx_reg.h.
| #define GC_L0OA0 0x00000024 |
Definition at line 51 of file mb862xx_reg.h.
| #define GC_L0PAL0 0x00000400 |
Definition at line 71 of file mb862xx_reg.h.
| #define GC_L0WH_L0WW 0x00000118 |
Definition at line 59 of file mb862xx_reg.h.
| #define GC_L0WY_L0WX 0x00000114 |
Definition at line 58 of file mb862xx_reg.h.
| #define GC_L1DA 0x00000034 |
Definition at line 55 of file mb862xx_reg.h.
| #define GC_L1EM 0x00000120 |
Definition at line 60 of file mb862xx_reg.h.
| #define GC_L1EM_DM 0x02000000 |
Definition at line 91 of file mb862xx_reg.h.
| #define GC_L1M 0x00000030 |
Definition at line 54 of file mb862xx_reg.h.
| #define GC_L1M_16 0x80000000 |
Definition at line 77 of file mb862xx_reg.h.
| #define GC_L1M_CS 0x20000000 |
Definition at line 79 of file mb862xx_reg.h.
| #define GC_L1M_YC 0x40000000 |
Definition at line 78 of file mb862xx_reg.h.
| #define GC_L1WH_L1WW 0x00000128 |
Definition at line 62 of file mb862xx_reg.h.
| #define GC_L1WY_L1WX 0x00000124 |
Definition at line 61 of file mb862xx_reg.h.
| #define GC_MMR 0x0000fffc |
Definition at line 39 of file mb862xx_reg.h.
| #define GC_RE_REVISION 0x24240200 |
Definition at line 157 of file mb862xx_reg.h.
| #define GC_REVISION 0x00000084 |
Definition at line 25 of file mb862xx_reg.h.
| #define GC_RSW 0x0000005c |
Definition at line 23 of file mb862xx_reg.h.
| #define GC_SRST 0x0000002c |
Definition at line 21 of file mb862xx_reg.h.
| #define GC_VCM_CM 0x03000000 |
Definition at line 129 of file mb862xx_reg.h.
| #define GC_VCM_VIE 0x80000000 |
Definition at line 128 of file mb862xx_reg.h.
| #define GC_VCM_VS_PAL 0x00000002 |
Definition at line 130 of file mb862xx_reg.h.
| #define GC_VDP_VSP 0x00000014 |
Definition at line 47 of file mb862xx_reg.h.
| #define GC_VSW_HSW_HSP 0x0000000c |
Definition at line 45 of file mb862xx_reg.h.
| #define GC_VTR 0x00000010 |
Definition at line 46 of file mb862xx_reg.h.
| #define GC_WH_WW 0x0000001c |
Definition at line 49 of file mb862xx_reg.h.
| #define GC_WY_WX 0x00000018 |
Definition at line 48 of file mb862xx_reg.h.
| #define I2C_ACK 0x08 |
Definition at line 110 of file mb862xx_reg.h.
| #define I2C_BEIE 0x40 |
Definition at line 112 of file mb862xx_reg.h.
| #define I2C_BER 0x80 |
Definition at line 111 of file mb862xx_reg.h.
| #define I2C_CLOCK_AND_ENABLE 0x0000003f |
Definition at line 106 of file mb862xx_reg.h.
| #define I2C_DISABLE 0x00000000 |
Definition at line 102 of file mb862xx_reg.h.
| #define I2C_INT 0x01 |
Definition at line 108 of file mb862xx_reg.h.
| #define I2C_INTE 0x02 |
Definition at line 109 of file mb862xx_reg.h.
| #define I2C_LRB 0x10 |
Definition at line 114 of file mb862xx_reg.h.
| #define I2C_READY 0x01 |
Definition at line 107 of file mb862xx_reg.h.
| #define I2C_REPEATED_START 0x00000030 |
Definition at line 105 of file mb862xx_reg.h.
| #define I2C_START 0x00000010 |
Definition at line 104 of file mb862xx_reg.h.
| #define I2C_STOP 0x00000000 |
Definition at line 103 of file mb862xx_reg.h.
| #define I2C_TRX 0x80 |
Definition at line 113 of file mb862xx_reg.h.
| #define MB86297_CAP0_BASE 0x00200000 |
Definition at line 140 of file mb862xx_reg.h.
| #define MB86297_CAP1_BASE 0x00280000 |
Definition at line 141 of file mb862xx_reg.h.
| #define MB86297_CTRL_BASE 0x00400000 |
Definition at line 143 of file mb862xx_reg.h.
| #define MB86297_DISP0_BASE 0x00100000 |
Definition at line 137 of file mb862xx_reg.h.
| #define MB86297_DISP1_BASE 0x00140000 |
Definition at line 138 of file mb862xx_reg.h.
| #define MB86297_DRAMCTRL_BASE 0x00300000 |
Definition at line 142 of file mb862xx_reg.h.
| #define MB86297_DRAW_BASE 0x00020000 |
Definition at line 136 of file mb862xx_reg.h.
| #define MB86297_I2C_BASE 0x00500000 |
Definition at line 144 of file mb862xx_reg.h.
| #define MB86297_WRBACK_BASE 0x00180000 |
Definition at line 139 of file mb862xx_reg.h.
| #define MB862XX_CAP_BASE 0x00018000 |
Definition at line 12 of file mb862xx_reg.h.
| #define MB862XX_DISP_BASE 0x00010000 |
Definition at line 11 of file mb862xx_reg.h.
| #define MB862XX_DRAW_BASE 0x00030000 |
Definition at line 13 of file mb862xx_reg.h.
| #define MB862XX_GEO_BASE 0x00038000 |
Definition at line 14 of file mb862xx_reg.h.
| #define MB862XX_I2C_BASE 0x0000c000 |
Definition at line 10 of file mb862xx_reg.h.
| #define MB862XX_MMIO_BASE 0x01fc0000 |
Definition at line 8 of file mb862xx_reg.h.
| #define MB862XX_MMIO_HIGH_BASE 0x03fc0000 |
Definition at line 9 of file mb862xx_reg.h.
| #define MB862XX_MMIO_SIZE 0x40000 |
Definition at line 16 of file mb862xx_reg.h.
| #define MB862XX_PIO_BASE 0x00038000 |
Definition at line 15 of file mb862xx_reg.h.
1.8.2