Go to the documentation of this file.
12 #ifndef _ASM_MB86943A_H
13 #define _ASM_MB86943A_H
17 #define __reg_MB86943_sl_ctl *(volatile uint32_t *) (__region_CS1 + 0x00)
19 #define MB86943_SL_CTL_BUS_WIDTH_64 0x00000001
20 #define MB86943_SL_CTL_AS_HOST 0x00000002
21 #define MB86943_SL_CTL_DRCT_MASTER_SWAP 0x00000004
22 #define MB86943_SL_CTL_DRCT_SLAVE_SWAP 0x00000008
23 #define MB86943_SL_CTL_PCI_CONFIG_SWAP 0x00000010
24 #define MB86943_SL_CTL_ECS0_ENABLE 0x00000020
25 #define MB86943_SL_CTL_ECS1_ENABLE 0x00000040
26 #define MB86943_SL_CTL_ECS2_ENABLE 0x00000080
28 #define __reg_MB86943_ecs_ctl(N) *(volatile uint32_t *) (__region_CS1 + 0x08 + (0x08*(N)))
29 #define __reg_MB86943_ecs_range(N) *(volatile uint32_t *) (__region_CS1 + 0x20 + (0x10*(N)))
30 #define __reg_MB86943_ecs_base(N) *(volatile uint32_t *) (__region_CS1 + 0x28 + (0x10*(N)))
32 #define __reg_MB86943_sl_pci_io_range *(volatile uint32_t *) (__region_CS1 + 0x50)
33 #define __reg_MB86943_sl_pci_io_base *(volatile uint32_t *) (__region_CS1 + 0x58)
34 #define __reg_MB86943_sl_pci_mem_range *(volatile uint32_t *) (__region_CS1 + 0x60)
35 #define __reg_MB86943_sl_pci_mem_base *(volatile uint32_t *) (__region_CS1 + 0x68)
36 #define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70)
37 #define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78)
39 #define __reg_MB86943_pci_arbiter *(volatile uint32_t *) (__region_CS2 + 0x01300014)
40 #define MB86943_PCIARB_EN 0x00000001