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mce_amd.h
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1 #ifndef _EDAC_MCE_AMD_H
2 #define _EDAC_MCE_AMD_H
3 
4 #include <linux/notifier.h>
5 
6 #include <asm/mce.h>
7 
8 #define EC(x) ((x) & 0xffff)
9 #define XEC(x, mask) (((x) >> 16) & mask)
10 
11 #define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
12 #define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
13 
14 #define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
15 #define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
16 #define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
17 
18 #define TT(x) (((x) >> 2) & 0x3)
19 #define TT_MSG(x) tt_msgs[TT(x)]
20 #define II(x) (((x) >> 2) & 0x3)
21 #define II_MSG(x) ii_msgs[II(x)]
22 #define LL(x) ((x) & 0x3)
23 #define LL_MSG(x) ll_msgs[LL(x)]
24 #define TO(x) (((x) >> 8) & 0x1)
25 #define TO_MSG(x) to_msgs[TO(x)]
26 #define PP(x) (((x) >> 9) & 0x3)
27 #define PP_MSG(x) pp_msgs[PP(x)]
28 
29 #define R4(x) (((x) >> 4) & 0xf)
30 #define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
31 
32 /*
33  * F3x4C bits (MCi_STATUS' high half)
34  */
35 #define NBSH_ERR_CPU_VAL BIT(24)
36 
37 enum tt_ids {
38  TT_INSTR = 0,
42 };
43 
44 enum ll_ids {
45  LL_RESV = 0,
49 };
50 
51 enum ii_ids {
52  II_MEM = 0,
56 };
57 
58 enum rrrr_ids {
59  R4_GEN = 0,
68 };
69 
70 extern const char * const tt_msgs[];
71 extern const char * const ll_msgs[];
72 extern const char * const rrrr_msgs[];
73 extern const char * const pp_msgs[];
74 extern const char * const to_msgs[];
75 extern const char * const ii_msgs[];
76 
77 /*
78  * per-family decoder ops
79  */
81  bool (*dc_mce)(u16, u8);
82  bool (*ic_mce)(u16, u8);
83 };
84 
85 void amd_report_gart_errors(bool);
86 void amd_register_ecc_decoder(void (*f)(int, struct mce *));
87 void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
88 void amd_decode_nb_mce(struct mce *);
89 int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);
90 
91 #endif /* _EDAC_MCE_AMD_H */