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| #define MCFINTC_EINT1 1 /* External int #1 */ |
| #define MCFINTC_EINT2 2 /* External int #2 */ |
| #define MCFINTC_EINT3 3 /* External int #3 */ |
| #define MCFINTC_EINT4 4 /* External int #4 */ |
| #define MCFINTC_EINT5 5 /* External int #5 */ |
| #define MCFINTC_EINT6 6 /* External int #6 */ |
| #define MCFINTC_EINT7 7 /* External int #7 */ |
| #define MCFINTC_I2C 11 /* I2C / MBUS */ |
| #define MCFINTC_SWT 8 /* Software Watchdog */ |
| #define MCFINTC_TIMER2 10 |
| #define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ |
| #define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ |
| #define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ |
| #define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ |
| #define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ |
| #define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ |
| #define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ |
| #define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ |
| #define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ |
| #define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ |
| #define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ |
| #define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ |
| #define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ |
| unsigned char mcf_irq2imr[] |
1.8.2