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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | MCFDEBUG_CSR 0x0 /* Configuration status */ |
| #define | MCFDEBUG_BAAR 0x5 /* BDM address attribute */ |
| #define | MCFDEBUG_AATR 0x6 /* Address attribute trigger */ |
| #define | MCFDEBUG_TDR 0x7 /* Trigger definition */ |
| #define | MCFDEBUG_PBR 0x8 /* PC breakpoint */ |
| #define | MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */ |
| #define | MCFDEBUG_ABHR 0xc /* High address breakpoint */ |
| #define | MCFDEBUG_ABLR 0xd /* Low address breakpoint */ |
| #define | MCFDEBUG_DBR 0xe /* Data breakpoint */ |
| #define | MCFDEBUG_DBMR 0xf /* Data breakpoint mask */ |
| #define | MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */ |
| #define | MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */ |
| #define | MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */ |
| #define | MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */ |
| #define | MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */ |
| #define | MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */ |
| #define | MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */ |
| #define | MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */ |
| #define | MCFDEBUG_TDR_EDLW2 0x10000000 |
| #define | MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */ |
| #define | MCFDEBUG_TDR_EDWL2 0x08000000 |
| #define | MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */ |
| #define | MCFDEBUG_TDR_EDWU2 0x04000000 |
| #define | MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */ |
| #define | MCFDEBUG_TDR_EDLL2 0x02000000 |
| #define | MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */ |
| #define | MCFDEBUG_TDR_EDLM2 0x01000000 |
| #define | MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */ |
| #define | MCFDEBUG_TDR_EDUM2 0x00800000 |
| #define | MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */ |
| #define | MCFDEBUG_TDR_EDUU2 0x00400000 |
| #define | MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */ |
| #define | MCFDEBUG_TDR_DI2 0x00200000 |
| #define | MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */ |
| #define | MCFDEBUG_TDR_EAI2 0x00100000 |
| #define | MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */ |
| #define | MCFDEBUG_TDR_EAR2 0x00080000 |
| #define | MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */ |
| #define | MCFDEBUG_TDR_EAL2 0x00040000 |
| #define | MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */ |
| #define | MCFDEBUG_TDR_EPC2 0x00020000 |
| #define | MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */ |
| #define | MCFDEBUG_TDR_PCI2 0x00010000 |
| #define | MCFDEBUG_AAR_RESET 0x00000005 |
| #define | MCFDEBUG_CSR_RESET 0x00100000 |
| #define | MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */ |
| #define | MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */ |
| #define | MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */ |
| #define | MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */ |
| #define | MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */ |
| #define | MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */ |
| #define | MCFDEBUG_CSR_DDC_WRITE 0x00001000 |
| #define | MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */ |
| #define | MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */ |
| #define | MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */ |
| #define | MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */ |
| #define | MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */ |
| #define | MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */ |
| #define | MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */ |
| #define | MCFDEBUG_BAAR_RESET 0x00000005 |
| #define MCFDEBUG_AAR_RESET 0x00000005 |
Definition at line 62 of file mcfwdebug.h.
| #define MCFDEBUG_AATR 0x6 /* Address attribute trigger */ |
Definition at line 17 of file mcfwdebug.h.
| #define MCFDEBUG_ABHR 0xc /* High address breakpoint */ |
Definition at line 21 of file mcfwdebug.h.
| #define MCFDEBUG_ABLR 0xd /* Low address breakpoint */ |
Definition at line 22 of file mcfwdebug.h.
| #define MCFDEBUG_BAAR 0x5 /* BDM address attribute */ |
Definition at line 16 of file mcfwdebug.h.
| #define MCFDEBUG_BAAR_RESET 0x00000005 |
Definition at line 83 of file mcfwdebug.h.
| #define MCFDEBUG_CSR 0x0 /* Configuration status */ |
Definition at line 15 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */ |
Definition at line 75 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */ |
Definition at line 76 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */ |
Definition at line 77 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */ |
Definition at line 78 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */ |
Definition at line 72 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_DDC_WRITE 0x00001000 |
Definition at line 73 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */ |
Definition at line 71 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */ |
Definition at line 68 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */ |
Definition at line 69 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */ |
Definition at line 79 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */ |
Definition at line 67 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_RESET 0x00100000 |
Definition at line 66 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */ |
Definition at line 80 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */ |
Definition at line 70 of file mcfwdebug.h.
| #define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */ |
Definition at line 74 of file mcfwdebug.h.
| #define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */ |
Definition at line 24 of file mcfwdebug.h.
| #define MCFDEBUG_DBR 0xe /* Data breakpoint */ |
Definition at line 23 of file mcfwdebug.h.
| #define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */ |
Definition at line 20 of file mcfwdebug.h.
| #define MCFDEBUG_PBR 0x8 /* PC breakpoint */ |
Definition at line 19 of file mcfwdebug.h.
| #define MCFDEBUG_TDR 0x7 /* Trigger definition */ |
Definition at line 18 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */ |
Definition at line 48 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_DI2 0x00200000 |
Definition at line 49 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */ |
Definition at line 50 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EAI2 0x00100000 |
Definition at line 51 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */ |
Definition at line 54 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EAL2 0x00040000 |
Definition at line 55 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */ |
Definition at line 52 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EAR2 0x00080000 |
Definition at line 53 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */ |
Definition at line 32 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */ |
Definition at line 33 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */ |
Definition at line 40 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDLL2 0x02000000 |
Definition at line 41 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */ |
Definition at line 42 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDLM2 0x01000000 |
Definition at line 43 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */ |
Definition at line 34 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDLW2 0x10000000 |
Definition at line 35 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */ |
Definition at line 44 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDUM2 0x00800000 |
Definition at line 45 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */ |
Definition at line 46 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDUU2 0x00400000 |
Definition at line 47 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */ |
Definition at line 36 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDWL2 0x08000000 |
Definition at line 37 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */ |
Definition at line 38 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EDWU2 0x04000000 |
Definition at line 39 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */ |
Definition at line 56 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_EPC2 0x00020000 |
Definition at line 57 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */ |
Definition at line 30 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */ |
Definition at line 31 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */ |
Definition at line 58 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_PCI2 0x00010000 |
Definition at line 59 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */ |
Definition at line 27 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */ |
Definition at line 28 of file mcfwdebug.h.
| #define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */ |
Definition at line 29 of file mcfwdebug.h.
1.8.2