Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
interrupts.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2009 Cisco Systems, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17  */
18 
19 #ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_
20 #define _ASM_MACH_POWERTV_INTERRUPTS_H_
21 
22 /*
23  * Defines for all of the interrupt lines
24  */
25 
26 /* Definitions for backward compatibility */
27 #define kIrq_Uart1 irq_uart1
28 
29 #define ibase 0
30 
31 /*------------- Register: int_stat_3 */
32 /* 126 unused (bit 31) */
33 #define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */
34 #define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */
35 #define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */
36 #define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */
37 #define irq_fdma_gp (ibase+122) /* FDMA GP Output */
38 #define irq_mips_pic (ibase+121) /* MIPS Performance Counter
39  * Interrupt */
40 #define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */
41 #define irq_memory_protect (ibase+119) /* Memory Protection Interrupt
42  * -- Ored by glue logic inside
43  * SPARC ILC (see
44  * INT_MEM_PROT_STAT, below,
45  * for individual interrupts)
46  */
47 /* 118 unused (bit 22) */
48 #define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by
49  * glue logic inside SPARC ILC
50  * (see INT_SBAG_STAT, below,
51  * for individual interrupts) */
52 #define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */
53 #define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */
54 /* 114 unused (bit 18) */
55 #define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt --
56  * Ored by glue logic inside
57  * SPARC ILC (see
58  * INT_MAILBOX_STAT, below, for
59  * individual interrupts) */
60 #define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */
61 #define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */
62 #define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse
63  * Status 3 */
64 #define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse
65  * Status 3 */
66 #define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0
67  * Interrupt */
68 #define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1
69  * Interrupt */
70 #define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE
71  * Interrupt */
72 #define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0
73  * Interrupt */
74 #define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1
75  * Interrupt */
76 #define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE
77  * Interrupt */
78 #define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */
79 #define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA
80  * Interrupt */
81 #define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */
82 #define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */
83 #define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */
84 #define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */
85 #define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */
86 #define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */
87 /*------------- Register: int_stat_2 */
88 #define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */
89 #define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */
90 #define irq_timer2 (ibase+93) /* Programmable Timer
91  * Interrupt 2 */
92 #define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */
93 #define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */
94 #define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */
95 #define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */
96 #define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */
97 #define irq_afe1 (ibase+88) /* AFE 1 Interrupt */
98 #define irq_sata (ibase+87) /* SATA 1 Interrupt */
99 #define irq_sata1 (ibase+87) /* SATA 1 Interrupt */
100 #define irq_dtcp (ibase+86) /* DTCP Interrupt */
101 #define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */
102 /* 84 unused (bit 20) */
103 /* 83 unused (bit 19) */
104 /* 82 unused (bit 18) */
105 #define irq_sata2 (ibase+81) /* SATA2 Interrupt */
106 #define irq_uart2 (ibase+80) /* UART2 Interrupt */
107 #define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1
108  * Host module) */
109 #define irq_pod (ibase+78) /* POD Interrupt */
110 #define irq_slave_usb (ibase+77) /* Slave USB */
111 #define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */
112 #define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */
113 #define irq_afe2 (ibase+74) /* AFE 2 Interrupt */
114 #define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */
115 #define irq_asc2 (ibase+72) /* ASC #2 Interrupt */
116 #define irq_asc1 (ibase+71) /* ASC #1 Interrupt */
117 #define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */
118 #define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */
119 #define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */
120 /* 67 unused (bit 03) */
121 /* 66 unused (bit 02) */
122 /* 65 unused (bit 01) */
123 /* 64 unused (bit 00) */
124 /*------------- Register: int_stat_1 */
125 /* 63 unused (bit 31) */
126 /* 62 unused (bit 30) */
127 /* 61 unused (bit 29) */
128 /* 60 unused (bit 28) */
129 /* 59 unused (bit 27) */
130 /* 58 unused (bit 26) */
131 /* 57 unused (bit 25) */
132 /* 56 unused (bit 24) */
133 #define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory
134  * Interrupt */
135 #define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit
136  * Interrupt */
137 #define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
138  * Interrupt */
139 #define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error
140  * Interrupt */
141 #define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive
142  * Interrupt */
143 #define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive
144  * Interrupt */
145 #define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error
146  * Interrupt */
147 #define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play
148  * Interrupt */
149 #define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error
150  * Interrupt */
151 #define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High
152  * (Chans 63-32) */
153 #define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low
154  * (Chans 31-0) */
155 #define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High
156  * (Chans 63-32) */
157 #define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low
158  * (Chans 31-0) */
159 #define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error
160  * Interrupt */
161 #define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */
162 #define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready
163  * Interrupt */
164 #define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */
165 #define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O
166  * Module */
167 #define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O
168  * Module (ABE_intN) */
169 #define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or
170  * Discontinuity 1 */
171 #define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or
172  * Discontinuity 2 */
173 #define irq_parse_peierr (ibase+34) /* PID Parser Error Detect
174  * (PEI) */
175 #define irq_parse_cont_err (ibase+33) /* PID Parser continuity error
176  * detect */
177 #define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */
178 /*------------- Register: int_stat_0 */
179 #define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O
180  * Module */
181 #define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O
182  * Module */
183 #define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha
184  * (chan 3) Transmission
185  * Completed OK */
186 #define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2)
187  * Transmission Completed OK */
188 #define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation
189  * (chan 1) Transmission
190  * Completed OK */
191 #define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha
192  * (chan 3)Transmission
193  * completed with Errors. */
194 #define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2)
195  * Transmission completed with
196  * Errors. */
197 #define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation
198  * (chan 1) Transmission
199  * completed with Errors */
200 #define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha
201  * for N times. Aloha retry
202  * timeout for channel 3. */
203 #define irq_timer1 (ibase+22) /* Programmable Timer
204  * Interrupt */
205 #define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */
206 #define irq_i2c (ibase+20) /* I2C Module Interrupt */
207 #define irq_spi (ibase+19) /* SPI Module Interrupt */
208 #define irq_irblaster (ibase+18) /* IR Blaster Interrupt */
209 #define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or
210  * Splice Detect Interrupt */
211 #define irq_se_micro (ibase+16) /* Secure Micro I/F Module
212  * Interrupt */
213 #define irq_uart1 (ibase+15) /* UART Interrupt */
214 #define irq_irrecv (ibase+14) /* IR Receiver Interrupt */
215 #define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */
216 #define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */
217 #define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */
218 #define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error
219  * Interrupt */
220 /* 9 unused (bit 09) */
221 /* 8 unused (bit 08) */
222 #define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error
223  * Interrupt */
224 #define irq_psilength_err (ibase+6) /* QAM PSI Length Error
225  * Interrupt */
226 #define irq_esfforward (ibase+5) /* ESF Interrupt Mark From
227  * Forward Path Reference -
228  * every 3ms when forward Mbits
229  * and forward slot control
230  * bytes are updated. */
231 #define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from
232  * Reverse Path Reference -
233  * delayed from forward mark by
234  * the ranging delay plus a
235  * fixed amount. When reverse
236  * Mbits and reverse slot
237  * control bytes are updated.
238  * Occurs every 3ms for 3.0M and
239  * 1.554 M upstream rates and
240  * every 6 ms for 256K upstream
241  * rate. */
242 #define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on
243  * Channel 1. */
244 #define irq_reservation (ibase+2) /* Partial (or Incremental)
245  * Reservation Message Completed
246  * or Slotted aloha verify for
247  * channel 1. */
248 #define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify
249  * Interrupt or Reservation
250  * increment completed for
251  * channel 3. */
252 #define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */
253 #endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
Generated on Thu Jan 10 2013 13:09:36 for Linux Kernel by   doxygen 1.8.2