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Macros
interrupts.h File Reference

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Macros

#define kIrq_Uart1   irq_uart1
 
#define ibase   0
 
#define irq_asc2video   (ibase+126) /* ASC 2 Video Interrupt */
 
#define irq_asc1video   (ibase+125) /* ASC 1 Video Interrupt */
 
#define irq_comms_block_wd   (ibase+124) /* ASC 1 Video Interrupt */
 
#define irq_fdma_mailbox   (ibase+123) /* FDMA Mailbox Output */
 
#define irq_fdma_gp   (ibase+122) /* FDMA GP Output */
 
#define irq_mips_pic
 
#define irq_mips_timer   (ibase+120) /* MIPS Timer Interrupt */
 
#define irq_memory_protect
 
#define irq_sbag
 
#define irq_qam_b_fec   (ibase+116) /* QAM B FEC Interrupt */
 
#define irq_qam_a_fec   (ibase+115) /* QAM A FEC Interrupt */
 
#define irq_mailbox
 
#define irq_fuse_stat1   (ibase+112) /* Fuse Status 1 */
 
#define irq_fuse_stat2   (ibase+111) /* Fuse Status 2 */
 
#define irq_fuse_stat3
 
#define irq_blitter
 
#define irq_avc1_pp0
 
#define irq_avc1_pp1
 
#define irq_avc1_mbe
 
#define irq_avc2_pp0
 
#define irq_avc2_pp1
 
#define irq_avc2_mbe
 
#define irq_zbug_spi   (ibase+103) /* Zbug SPI Slave Interrupt */
 
#define irq_qam_mod2
 
#define irq_ir_rx   (ibase+101) /* IR RX 2 Interrupt */
 
#define irq_aud_dsp2   (ibase+100) /* Audio DSP #2 Interrupt */
 
#define irq_aud_dsp1   (ibase+99) /* Audio DSP #1 Interrupt */
 
#define irq_docsis   (ibase+98) /* DOCSIS Debug Interrupt */
 
#define irq_sd_dvp1   (ibase+97) /* SD DVP #1 Interrupt */
 
#define irq_sd_dvp2   (ibase+96) /* SD DVP #2 Interrupt */
 
#define irq_hd_dvp   (ibase+95) /* HD DVP Interrupt */
 
#define kIrq_Prewatchdog   (ibase+94) /* watchdog Pre-Interrupt */
 
#define irq_timer2
 
#define irq_1394   (ibase+92) /* 1394 Firewire Interrupt */
 
#define irq_usbohci   (ibase+91) /* USB 2.0 OHCI Interrupt */
 
#define irq_usbehci   (ibase+90) /* USB 2.0 EHCI Interrupt */
 
#define irq_pciexp   (ibase+89) /* PCI Express 0 Interrupt */
 
#define irq_pciexp0   (ibase+89) /* PCI Express 0 Interrupt */
 
#define irq_afe1   (ibase+88) /* AFE 1 Interrupt */
 
#define irq_sata   (ibase+87) /* SATA 1 Interrupt */
 
#define irq_sata1   (ibase+87) /* SATA 1 Interrupt */
 
#define irq_dtcp   (ibase+86) /* DTCP Interrupt */
 
#define irq_pciexp1   (ibase+85) /* PCI Express 1 Interrupt */
 
#define irq_sata2   (ibase+81) /* SATA2 Interrupt */
 
#define irq_uart2   (ibase+80) /* UART2 Interrupt */
 
#define irq_legacy_usb
 
#define irq_pod   (ibase+78) /* POD Interrupt */
 
#define irq_slave_usb   (ibase+77) /* Slave USB */
 
#define irq_denc1   (ibase+76) /* DENC #1 VTG Interrupt */
 
#define irq_vbi_vtg   (ibase+75) /* VBI VTG Interrupt */
 
#define irq_afe2   (ibase+74) /* AFE 2 Interrupt */
 
#define irq_denc2   (ibase+73) /* DENC #2 VTG Interrupt */
 
#define irq_asc2   (ibase+72) /* ASC #2 Interrupt */
 
#define irq_asc1   (ibase+71) /* ASC #1 Interrupt */
 
#define irq_mod_dma   (ibase+70) /* Modulator DMA Interrupt */
 
#define irq_byte_eng1   (ibase+69) /* Byte Engine Interrupt [1] */
 
#define irq_byte_eng0   (ibase+68) /* Byte Engine Interrupt [0] */
 
#define irq_buf_dma_mem2mem
 
#define irq_buf_dma_usbtransmit
 
#define irq_buf_dma_qpskpodtransmit
 
#define irq_buf_dma_transmit_error
 
#define irq_buf_dma_usbrecv
 
#define irq_buf_dma_qpskpodrecv
 
#define irq_buf_dma_recv_error
 
#define irq_qamdma_transmit_play
 
#define irq_qamdma_transmit_error
 
#define irq_qamdma_recv2high
 
#define irq_qamdma_recv2low
 
#define irq_qamdma_recv1high
 
#define irq_qamdma_recv1low
 
#define irq_qamdma_recv_error
 
#define irq_mpegsplice   (ibase+41) /* MPEG Splice Interrupt */
 
#define irq_deinterlace_rdy
 
#define irq_ext_in0   (ibase+39) /* External Interrupt irq_in0 */
 
#define irq_gpio3
 
#define irq_gpio2
 
#define irq_pcrcmplt1
 
#define irq_pcrcmplt2
 
#define irq_parse_peierr
 
#define irq_parse_cont_err
 
#define irq_ds1framer   (ibase+32) /* DS1 Framer Interrupt */
 
#define irq_gpio1
 
#define irq_gpio0
 
#define irq_qpsk_out_aloha
 
#define irq_qpsk_out_tdma
 
#define irq_qpsk_out_reserve
 
#define irq_qpsk_out_aloha_err
 
#define irq_qpsk_out_tdma_err
 
#define irq_qpsk_out_rsrv_err
 
#define irq_aloha_fail
 
#define irq_timer1
 
#define irq_keyboard   (ibase+21) /* Keyboard Module Interrupt */
 
#define irq_i2c   (ibase+20) /* I2C Module Interrupt */
 
#define irq_spi   (ibase+19) /* SPI Module Interrupt */
 
#define irq_irblaster   (ibase+18) /* IR Blaster Interrupt */
 
#define irq_splice_detect
 
#define irq_se_micro
 
#define irq_uart1   (ibase+15) /* UART Interrupt */
 
#define irq_irrecv   (ibase+14) /* IR Receiver Interrupt */
 
#define irq_host_int1   (ibase+13) /* Host-to-Host Interrupt 1 */
 
#define irq_host_int0   (ibase+12) /* Host-to-Host Interrupt 0 */
 
#define irq_qpsk_hecerr   (ibase+11) /* QPSK HEC Error Interrupt */
 
#define irq_qpsk_crcerr
 
#define irq_psicrcerr
 
#define irq_psilength_err
 
#define irq_esfforward
 
#define irq_esfreverse
 
#define irq_aloha_timeout
 
#define irq_reservation
 
#define irq_aloha3
 
#define irq_mpeg_d   (ibase+0) /* MPEG Decoder Interrupt */
 

Macro Definition Documentation

#define ibase   0

Definition at line 29 of file interrupts.h.

#define irq_1394   (ibase+92) /* 1394 Firewire Interrupt */

Definition at line 69 of file interrupts.h.

#define irq_afe1   (ibase+88) /* AFE 1 Interrupt */

Definition at line 74 of file interrupts.h.

#define irq_afe2   (ibase+74) /* AFE 2 Interrupt */

Definition at line 89 of file interrupts.h.

#define irq_aloha3
Value:
(ibase+1) /* Slotted-Aloha Message Verify
* Interrupt or Reservation
* increment completed for
* channel 3. */

Definition at line 164 of file interrupts.h.

#define irq_aloha_fail
Value:
(ibase+23) /* Unsuccessful Resend of Aloha
* for N times. Aloha retry
* timeout for channel 3. */

Definition at line 142 of file interrupts.h.

#define irq_aloha_timeout
Value:
(ibase+3) /* Slotted-Aloha timeout on
* Channel 1. */

Definition at line 162 of file interrupts.h.

#define irq_asc1   (ibase+71) /* ASC #1 Interrupt */

Definition at line 92 of file interrupts.h.

#define irq_asc1video   (ibase+125) /* ASC 1 Video Interrupt */

Definition at line 34 of file interrupts.h.

#define irq_asc2   (ibase+72) /* ASC #2 Interrupt */

Definition at line 91 of file interrupts.h.

#define irq_asc2video   (ibase+126) /* ASC 2 Video Interrupt */

Definition at line 33 of file interrupts.h.

#define irq_aud_dsp1   (ibase+99) /* Audio DSP #1 Interrupt */

Definition at line 61 of file interrupts.h.

#define irq_aud_dsp2   (ibase+100) /* Audio DSP #2 Interrupt */

Definition at line 60 of file interrupts.h.

#define irq_avc1_mbe
Value:
(ibase+107) /* AVC Decoder #1 MBE
* Interrupt */

Definition at line 53 of file interrupts.h.

#define irq_avc1_pp0
Value:
(ibase+109) /* AVC Decoder #1 PP0
* Interrupt */

Definition at line 51 of file interrupts.h.

#define irq_avc1_pp1
Value:
(ibase+108) /* AVC Decoder #1 PP1
* Interrupt */

Definition at line 52 of file interrupts.h.

#define irq_avc2_mbe
Value:
(ibase+104) /* AVC Decoder #2 MBE
* Interrupt */

Definition at line 56 of file interrupts.h.

#define irq_avc2_pp0
Value:
(ibase+106) /* AVC Decoder #2 PP0
* Interrupt */

Definition at line 54 of file interrupts.h.

#define irq_avc2_pp1
Value:
(ibase+105) /* AVC Decoder #2 PP1
* Interrupt */

Definition at line 55 of file interrupts.h.

#define irq_blitter
Value:
(ibase+110) /* Blitter Interrupt / Fuse
* Status 3 */

Definition at line 50 of file interrupts.h.

#define irq_buf_dma_mem2mem
Value:
(ibase+55) /* BufDMA Memory to Memory
* Interrupt */

Definition at line 109 of file interrupts.h.

#define irq_buf_dma_qpskpodrecv
Value:
(ibase+50) /* BufDMA QPSK/POD Receive
* Interrupt */

Definition at line 114 of file interrupts.h.

#define irq_buf_dma_qpskpodtransmit
Value:
(ibase+53) /* BufDMA QPSK/POD Tramsit
* Interrupt */

Definition at line 111 of file interrupts.h.

#define irq_buf_dma_recv_error
Value:
(ibase+49) /* BufDMA Receive Error
* Interrupt */

Definition at line 115 of file interrupts.h.

#define irq_buf_dma_transmit_error
Value:
(ibase+52) /* BufDMA Transmit Error
* Interrupt */

Definition at line 112 of file interrupts.h.

#define irq_buf_dma_usbrecv
Value:
(ibase+51) /* BufDMA USB Receive
* Interrupt */

Definition at line 113 of file interrupts.h.

#define irq_buf_dma_usbtransmit
Value:
(ibase+54) /* BufDMA USB Transmit
* Interrupt */

Definition at line 110 of file interrupts.h.

#define irq_byte_eng0   (ibase+68) /* Byte Engine Interrupt [0] */

Definition at line 95 of file interrupts.h.

#define irq_byte_eng1   (ibase+69) /* Byte Engine Interrupt [1] */

Definition at line 94 of file interrupts.h.

#define irq_comms_block_wd   (ibase+124) /* ASC 1 Video Interrupt */

Definition at line 35 of file interrupts.h.

#define irq_deinterlace_rdy
Value:
(ibase+40) /* Deinterlacer Frame Ready
* Interrupt */

Definition at line 124 of file interrupts.h.

#define irq_denc1   (ibase+76) /* DENC #1 VTG Interrupt */

Definition at line 87 of file interrupts.h.

#define irq_denc2   (ibase+73) /* DENC #2 VTG Interrupt */

Definition at line 90 of file interrupts.h.

#define irq_docsis   (ibase+98) /* DOCSIS Debug Interrupt */

Definition at line 62 of file interrupts.h.

#define irq_ds1framer   (ibase+32) /* DS1 Framer Interrupt */

Definition at line 132 of file interrupts.h.

#define irq_dtcp   (ibase+86) /* DTCP Interrupt */

Definition at line 77 of file interrupts.h.

#define irq_esfforward
Value:
(ibase+5) /* ESF Interrupt Mark From
* Forward Path Reference -
* every 3ms when forward Mbits
* and forward slot control
* bytes are updated. */

Definition at line 160 of file interrupts.h.

#define irq_esfreverse
Value:
(ibase+4) /* ESF Interrupt Mark from
* Reverse Path Reference -
* delayed from forward mark by
* the ranging delay plus a
* fixed amount. When reverse
* Mbits and reverse slot
* control bytes are updated.
* Occurs every 3ms for 3.0M and
* 1.554 M upstream rates and
* every 6 ms for 256K upstream
* rate. */

Definition at line 161 of file interrupts.h.

#define irq_ext_in0   (ibase+39) /* External Interrupt irq_in0 */

Definition at line 125 of file interrupts.h.

#define irq_fdma_gp   (ibase+122) /* FDMA GP Output */

Definition at line 37 of file interrupts.h.

#define irq_fdma_mailbox   (ibase+123) /* FDMA Mailbox Output */

Definition at line 36 of file interrupts.h.

#define irq_fuse_stat1   (ibase+112) /* Fuse Status 1 */

Definition at line 47 of file interrupts.h.

#define irq_fuse_stat2   (ibase+111) /* Fuse Status 2 */

Definition at line 48 of file interrupts.h.

#define irq_fuse_stat3
Value:
(ibase+110) /* Blitter Interrupt / Fuse
* Status 3 */

Definition at line 49 of file interrupts.h.

#define irq_gpio0
Value:
(ibase+30) /* GP I/O IRQ 0 - From GP I/O
* Module */

Definition at line 135 of file interrupts.h.

#define irq_gpio1
Value:
(ibase+31) /* GP I/O IRQ 1 - From GP I/O
* Module */

Definition at line 134 of file interrupts.h.

#define irq_gpio2
Value:
(ibase+37) /* GP I/O IRQ 2 - From GP I/O
* Module (ABE_intN) */

Definition at line 127 of file interrupts.h.

#define irq_gpio3
Value:
(ibase+38) /* GP I/O IRQ 3 - From GP I/O
* Module */

Definition at line 126 of file interrupts.h.

#define irq_hd_dvp   (ibase+95) /* HD DVP Interrupt */

Definition at line 66 of file interrupts.h.

#define irq_host_int0   (ibase+12) /* Host-to-Host Interrupt 0 */

Definition at line 153 of file interrupts.h.

#define irq_host_int1   (ibase+13) /* Host-to-Host Interrupt 1 */

Definition at line 152 of file interrupts.h.

#define irq_i2c   (ibase+20) /* I2C Module Interrupt */

Definition at line 145 of file interrupts.h.

#define irq_ir_rx   (ibase+101) /* IR RX 2 Interrupt */

Definition at line 59 of file interrupts.h.

#define irq_irblaster   (ibase+18) /* IR Blaster Interrupt */

Definition at line 147 of file interrupts.h.

#define irq_irrecv   (ibase+14) /* IR Receiver Interrupt */

Definition at line 151 of file interrupts.h.

#define irq_keyboard   (ibase+21) /* Keyboard Module Interrupt */

Definition at line 144 of file interrupts.h.

#define irq_legacy_usb
Value:
(ibase+79) /* Legacy USB Host ISR (1.1
* Host module) */

Definition at line 84 of file interrupts.h.

#define irq_mailbox
Value:
(ibase+113) /* Mailbox Debug Interrupt --
* Ored by glue logic inside
* SPARC ILC (see
* INT_MAILBOX_STAT, below, for
* individual interrupts) */

Definition at line 46 of file interrupts.h.

#define irq_memory_protect
Value:
(ibase+119) /* Memory Protection Interrupt
* -- Ored by glue logic inside
* SPARC ILC (see
* INT_MEM_PROT_STAT, below,
* for individual interrupts)
*/

Definition at line 40 of file interrupts.h.

#define irq_mips_pic
Value:
(ibase+121) /* MIPS Performance Counter
* Interrupt */

Definition at line 38 of file interrupts.h.

#define irq_mips_timer   (ibase+120) /* MIPS Timer Interrupt */

Definition at line 39 of file interrupts.h.

#define irq_mod_dma   (ibase+70) /* Modulator DMA Interrupt */

Definition at line 93 of file interrupts.h.

#define irq_mpeg_d   (ibase+0) /* MPEG Decoder Interrupt */

Definition at line 165 of file interrupts.h.

#define irq_mpegsplice   (ibase+41) /* MPEG Splice Interrupt */

Definition at line 123 of file interrupts.h.

#define irq_parse_cont_err
Value:
(ibase+33) /* PID Parser continuity error
* detect */

Definition at line 131 of file interrupts.h.

#define irq_parse_peierr
Value:
(ibase+34) /* PID Parser Error Detect
* (PEI) */

Definition at line 130 of file interrupts.h.

#define irq_pciexp   (ibase+89) /* PCI Express 0 Interrupt */

Definition at line 72 of file interrupts.h.

#define irq_pciexp0   (ibase+89) /* PCI Express 0 Interrupt */

Definition at line 73 of file interrupts.h.

#define irq_pciexp1   (ibase+85) /* PCI Express 1 Interrupt */

Definition at line 78 of file interrupts.h.

#define irq_pcrcmplt1
Value:
(ibase+36) /* PCR Capture Complete or
* Discontinuity 1 */

Definition at line 128 of file interrupts.h.

#define irq_pcrcmplt2
Value:
(ibase+35) /* PCR Capture Complete or
* Discontinuity 2 */

Definition at line 129 of file interrupts.h.

#define irq_pod   (ibase+78) /* POD Interrupt */

Definition at line 85 of file interrupts.h.

#define irq_psicrcerr
Value:
(ibase+7) /* QAM PSI CRC Error
* Interrupt */

Definition at line 158 of file interrupts.h.

#define irq_psilength_err
Value:
(ibase+6) /* QAM PSI Length Error
* Interrupt */

Definition at line 159 of file interrupts.h.

#define irq_qam_a_fec   (ibase+115) /* QAM A FEC Interrupt */

Definition at line 44 of file interrupts.h.

#define irq_qam_b_fec   (ibase+116) /* QAM B FEC Interrupt */

Definition at line 43 of file interrupts.h.

#define irq_qam_mod2
Value:
(ibase+102) /* QAM Modulator 2 DMA
* Interrupt */

Definition at line 58 of file interrupts.h.

#define irq_qamdma_recv1high
Value:
(ibase+44) /* QAMDMA Receive 1 High
* (Chans 63-32) */

Definition at line 120 of file interrupts.h.

#define irq_qamdma_recv1low
Value:
(ibase+43) /* QAMDMA Receive 1 Low
* (Chans 31-0) */

Definition at line 121 of file interrupts.h.

#define irq_qamdma_recv2high
Value:
(ibase+46) /* QAMDMA Receive 2 High
* (Chans 63-32) */

Definition at line 118 of file interrupts.h.

#define irq_qamdma_recv2low
Value:
(ibase+45) /* QAMDMA Receive 2 Low
* (Chans 31-0) */

Definition at line 119 of file interrupts.h.

#define irq_qamdma_recv_error
Value:
(ibase+42) /* QAMDMA Receive Error
* Interrupt */

Definition at line 122 of file interrupts.h.

#define irq_qamdma_transmit_error
Value:
(ibase+47) /* QAMDMA Transmit Error
* Interrupt */

Definition at line 117 of file interrupts.h.

#define irq_qamdma_transmit_play
Value:
(ibase+48) /* QAMDMA Transmit/Play
* Interrupt */

Definition at line 116 of file interrupts.h.

#define irq_qpsk_crcerr
Value:
(ibase+10) /* QPSK AAL-5 CRC Error
* Interrupt */

Definition at line 155 of file interrupts.h.

#define irq_qpsk_hecerr   (ibase+11) /* QPSK HEC Error Interrupt */

Definition at line 154 of file interrupts.h.

#define irq_qpsk_out_aloha
Value:
(ibase+29) /* QPSK Output Slotted Aloha
* (chan 3) Transmission
* Completed OK */

Definition at line 136 of file interrupts.h.

#define irq_qpsk_out_aloha_err
Value:
(ibase+26) /* QPSK Output Slotted Aloha
* (chan 3)Transmission
* completed with Errors. */

Definition at line 139 of file interrupts.h.

#define irq_qpsk_out_reserve
Value:
(ibase+27) /* QPSK Output Reservation
* (chan 1) Transmission
* Completed OK */

Definition at line 138 of file interrupts.h.

#define irq_qpsk_out_rsrv_err
Value:
(ibase+24) /* QPSK Output Reservation
* (chan 1) Transmission
* completed with Errors */

Definition at line 141 of file interrupts.h.

#define irq_qpsk_out_tdma
Value:
(ibase+28) /* QPSK Output TDMA (chan 2)
* Transmission Completed OK */

Definition at line 137 of file interrupts.h.

#define irq_qpsk_out_tdma_err
Value:
(ibase+25) /* QPSK Output TDMA (chan 2)
* Transmission completed with
* Errors. */

Definition at line 140 of file interrupts.h.

#define irq_reservation
Value:
(ibase+2) /* Partial (or Incremental)
* Reservation Message Completed
* or Slotted aloha verify for
* channel 1. */

Definition at line 163 of file interrupts.h.

#define irq_sata   (ibase+87) /* SATA 1 Interrupt */

Definition at line 75 of file interrupts.h.

#define irq_sata1   (ibase+87) /* SATA 1 Interrupt */

Definition at line 76 of file interrupts.h.

#define irq_sata2   (ibase+81) /* SATA2 Interrupt */

Definition at line 82 of file interrupts.h.

#define irq_sbag
Value:
(ibase+117) /* SBAG Interrupt -- Ored by
* glue logic inside SPARC ILC
* (see INT_SBAG_STAT, below,
* for individual interrupts) */

Definition at line 42 of file interrupts.h.

#define irq_sd_dvp1   (ibase+97) /* SD DVP #1 Interrupt */

Definition at line 63 of file interrupts.h.

#define irq_sd_dvp2   (ibase+96) /* SD DVP #2 Interrupt */

Definition at line 64 of file interrupts.h.

#define irq_se_micro
Value:
(ibase+16) /* Secure Micro I/F Module
* Interrupt */

Definition at line 149 of file interrupts.h.

#define irq_slave_usb   (ibase+77) /* Slave USB */

Definition at line 86 of file interrupts.h.

#define irq_spi   (ibase+19) /* SPI Module Interrupt */

Definition at line 146 of file interrupts.h.

#define irq_splice_detect
Value:
(ibase+17) /* PID Key Change Interrupt or
* Splice Detect Interrupt */

Definition at line 148 of file interrupts.h.

#define irq_timer1
Value:
(ibase+22) /* Programmable Timer
* Interrupt */

Definition at line 143 of file interrupts.h.

#define irq_timer2
Value:
(ibase+93) /* Programmable Timer
* Interrupt 2 */

Definition at line 68 of file interrupts.h.

#define irq_uart1   (ibase+15) /* UART Interrupt */

Definition at line 150 of file interrupts.h.

#define irq_uart2   (ibase+80) /* UART2 Interrupt */

Definition at line 83 of file interrupts.h.

#define irq_usbehci   (ibase+90) /* USB 2.0 EHCI Interrupt */

Definition at line 71 of file interrupts.h.

#define irq_usbohci   (ibase+91) /* USB 2.0 OHCI Interrupt */

Definition at line 70 of file interrupts.h.

#define irq_vbi_vtg   (ibase+75) /* VBI VTG Interrupt */

Definition at line 88 of file interrupts.h.

#define irq_zbug_spi   (ibase+103) /* Zbug SPI Slave Interrupt */

Definition at line 57 of file interrupts.h.

#define kIrq_Prewatchdog   (ibase+94) /* watchdog Pre-Interrupt */

Definition at line 67 of file interrupts.h.

#define kIrq_Uart1   irq_uart1

Definition at line 27 of file interrupts.h.

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