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| #define CTL_CLK_AND_WAIT_CTL 0x138 |
| #define CTL_DMA_ENABLE 0xd8 |
| #define CTL_IRQ_MASK 0x20 |
| #define CTL_RESET_SD 0xe0 |
| #define CTL_RESET_SDIO 0x1e0 |
| #define CTL_RESPONSE 0x0c |
| #define CTL_SD_CARD_CLK_CTL 0x24 |
| #define CTL_SD_DATA_PORT 0x30 |
| #define CTL_SD_ERROR_DETAIL_STATUS 0x2c |
| #define CTL_SD_MEM_CARD_OPT 0x28 |
| #define CTL_SD_XFER_LEN 0x26 |
| #define CTL_SDIO_IRQ_MASK 0x38 |
| #define CTL_SDIO_REGS 0x100 |
| #define CTL_SDIO_STATUS 0x36 |
| #define CTL_STOP_INTERNAL_ACTION 0x08 |
| #define CTL_TRANSACTION_CTL 0x34 |
| #define CTL_XFER_BLK_COUNT 0xa |
| #define TMIO_STAT_CARD_INSERT 0x00000010 |
| #define TMIO_STAT_CARD_INSERT_A 0x00000200 |
| #define TMIO_STAT_CARD_REMOVE 0x00000008 |
| #define TMIO_STAT_CARD_REMOVE_A 0x00000100 |
| #define TMIO_STAT_CMD_BUSY 0x40000000 |
| #define TMIO_STAT_CMD_IDX_ERR 0x00010000 |
| #define TMIO_STAT_CMDRESPEND 0x00000001 |
| #define TMIO_STAT_CMDTIMEOUT 0x00400000 |
| #define TMIO_STAT_CRCFAIL 0x00020000 |
| #define TMIO_STAT_DATAEND 0x00000004 |
| #define TMIO_STAT_DATATIMEOUT 0x00080000 |
| #define TMIO_STAT_ILL_ACCESS 0x80000000 |
| #define TMIO_STAT_ILL_FUNC 0x20000000 |
| #define TMIO_STAT_RXOVERFLOW 0x00100000 |
| #define TMIO_STAT_RXRDY 0x01000000 |
| #define TMIO_STAT_SIGSTATE 0x00000020 |
| #define TMIO_STAT_SIGSTATE_A 0x00000400 |
| #define TMIO_STAT_STOPBIT_ERR 0x00040000 |
| #define TMIO_STAT_TXRQ 0x02000000 |
| #define TMIO_STAT_TXUNDERRUN 0x00200000 |
| #define TMIO_STAT_WRPROTECT 0x00000080 |
1.8.2