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| #define mmu_linear_psize MMU_PAGE_256M |
| #define mmu_virtual_psize MMU_PAGE_4K |
| #define PPC40X_TLB_SIZE 64 |
| #define TLB_ATTR_MASK 0x0000000F |
| #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ |
| #define TLB_EX 0x00000200 /* Instruction execution allowed */ |
| #define TLB_G 0x00000001 /* Memory is guarded from prefetch */ |
| #define TLB_I 0x00000004 /* Caching is inhibited */ |
| #define TLB_M 0x00000002 /* Memory is coherent */ |
| #define TLB_PAGESZ |
( |
|
x | ) |
(((x) & 0x7) << 7) |
| #define TLB_PAGESZ_MASK 0x00000380 |
| #define TLB_PERM_MASK 0x00000300 |
| #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ |
| #define TLB_VALID 0x00000040 /* Entry is valid */ |
| #define TLB_W 0x00000008 /* Caching is write-through */ |
| #define TLB_WR 0x00000100 /* Writes permitted */ |
| #define TLB_ZSEL |
( |
|
x | ) |
(((x) & 0xF) << 4) |
| #define TLB_ZSEL_MASK 0x000000F0 |
1.8.2