Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Data Structures | Macros | Variables
mmu-44x.h File Reference
#include <asm/page.h>

Go to the source code of this file.

Data Structures

struct  mm_context_t
 

Macros

#define PPC44x_MMUCR_TID   0x000000ff
 
#define PPC44x_MMUCR_STS   0x00010000
 
#define PPC44x_TLB_PAGEID   0
 
#define PPC44x_TLB_XLAT   1
 
#define PPC44x_TLB_ATTRIB   2
 
#define PPC44x_TLB_EPN_MASK   0xfffffc00 /* Effective Page Number */
 
#define PPC44x_TLB_VALID   0x00000200 /* Valid flag */
 
#define PPC44x_TLB_TS   0x00000100 /* Translation address space */
 
#define PPC44x_TLB_1K   0x00000000 /* Page sizes */
 
#define PPC44x_TLB_4K   0x00000010
 
#define PPC44x_TLB_16K   0x00000020
 
#define PPC44x_TLB_64K   0x00000030
 
#define PPC44x_TLB_256K   0x00000040
 
#define PPC44x_TLB_1M   0x00000050
 
#define PPC44x_TLB_16M   0x00000070
 
#define PPC44x_TLB_256M   0x00000090
 
#define PPC44x_TLB_RPN_MASK   0xfffffc00 /* Real Page Number */
 
#define PPC44x_TLB_ERPN_MASK   0x0000000f
 
#define PPC44x_TLB_ATTR_MASK   0x0000ff80
 
#define PPC44x_TLB_U0   0x00008000 /* User 0 */
 
#define PPC44x_TLB_U1   0x00004000 /* User 1 */
 
#define PPC44x_TLB_U2   0x00002000 /* User 2 */
 
#define PPC44x_TLB_U3   0x00001000 /* User 3 */
 
#define PPC44x_TLB_W   0x00000800 /* Caching is write-through */
 
#define PPC44x_TLB_I   0x00000400 /* Caching is inhibited */
 
#define PPC44x_TLB_M   0x00000200 /* Memory is coherent */
 
#define PPC44x_TLB_G   0x00000100 /* Memory is guarded */
 
#define PPC44x_TLB_E   0x00000080 /* Memory is little endian */
 
#define PPC44x_TLB_PERM_MASK   0x0000003f
 
#define PPC44x_TLB_UX   0x00000020 /* User execution */
 
#define PPC44x_TLB_UW   0x00000010 /* User write */
 
#define PPC44x_TLB_UR   0x00000008 /* User read */
 
#define PPC44x_TLB_SX   0x00000004 /* Super execution */
 
#define PPC44x_TLB_SW   0x00000002 /* Super write */
 
#define PPC44x_TLB_SR   0x00000001 /* Super read */
 
#define PPC44x_TLB_SIZE   64
 
#define PPC47x_MMUCR_TID   0x0000ffff
 
#define PPC47x_MMUCR_STS   0x00010000
 
#define PPC47x_TLB0_EPN_MASK   0xfffff000 /* Effective Page Number */
 
#define PPC47x_TLB0_VALID   0x00000800 /* Valid flag */
 
#define PPC47x_TLB0_TS   0x00000400 /* Translation address space */
 
#define PPC47x_TLB0_4K   0x00000000
 
#define PPC47x_TLB0_16K   0x00000010
 
#define PPC47x_TLB0_64K   0x00000030
 
#define PPC47x_TLB0_1M   0x00000070
 
#define PPC47x_TLB0_16M   0x000000f0
 
#define PPC47x_TLB0_256M   0x000001f0
 
#define PPC47x_TLB0_1G   0x000003f0
 
#define PPC47x_TLB0_BOLTED_R   0x00000008 /* tlbre only */
 
#define PPC47x_TLB1_RPN_MASK   0xfffff000 /* Real Page Number */
 
#define PPC47x_TLB1_ERPN_MASK   0x000003ff
 
#define PPC47x_TLB2_ATTR_MASK   0x0003ff80
 
#define PPC47x_TLB2_IL1I   0x00020000 /* Memory is guarded */
 
#define PPC47x_TLB2_IL1D   0x00010000 /* Memory is guarded */
 
#define PPC47x_TLB2_U0   0x00008000 /* User 0 */
 
#define PPC47x_TLB2_U1   0x00004000 /* User 1 */
 
#define PPC47x_TLB2_U2   0x00002000 /* User 2 */
 
#define PPC47x_TLB2_U3   0x00001000 /* User 3 */
 
#define PPC47x_TLB2_W   0x00000800 /* Caching is write-through */
 
#define PPC47x_TLB2_I   0x00000400 /* Caching is inhibited */
 
#define PPC47x_TLB2_M   0x00000200 /* Memory is coherent */
 
#define PPC47x_TLB2_G   0x00000100 /* Memory is guarded */
 
#define PPC47x_TLB2_E   0x00000080 /* Memory is little endian */
 
#define PPC47x_TLB2_PERM_MASK   0x0000003f
 
#define PPC47x_TLB2_UX   0x00000020 /* User execution */
 
#define PPC47x_TLB2_UW   0x00000010 /* User write */
 
#define PPC47x_TLB2_UR   0x00000008 /* User read */
 
#define PPC47x_TLB2_SX   0x00000004 /* Super execution */
 
#define PPC47x_TLB2_SW   0x00000002 /* Super write */
 
#define PPC47x_TLB2_SR   0x00000001 /* Super read */
 
#define PPC47x_TLB2_U_RWX   (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
 
#define PPC47x_TLB2_S_RWX   (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
 
#define PPC47x_TLB2_S_RW   (PPC47x_TLB2_SW | PPC47x_TLB2_SR)
 
#define PPC47x_TLB2_IMG   (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
 
#define PPC44x_EARLY_TLBS   1
 
#define PPC_PIN_SIZE   (1 << 28) /* 256M */
 
#define mmu_linear_psize   MMU_PAGE_256M
 
#define PPC44x_PGD_OFF_SHIFT   (32 - PGDIR_SHIFT + PGD_T_LOG2)
 
#define PPC44x_PGD_OFF_MASK_BIT   (PGDIR_SHIFT - PGD_T_LOG2)
 
#define PPC44x_PTE_ADD_SHIFT   (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
 
#define PPC44x_PTE_ADD_MASK_BIT   (32 - PTE_T_LOG2 - PTE_SHIFT)
 

Variables

unsigned int tlb_44x_hwater
 
unsigned int tlb_44x_index
 

Macro Definition Documentation

#define mmu_linear_psize   MMU_PAGE_256M

Definition at line 145 of file mmu-44x.h.

#define PPC44x_EARLY_TLBS   1

Definition at line 116 of file mmu-44x.h.

#define PPC44x_MMUCR_STS   0x00010000

Definition at line 10 of file mmu-44x.h.

#define PPC44x_MMUCR_TID   0x000000ff

Definition at line 9 of file mmu-44x.h.

#define PPC44x_PGD_OFF_MASK_BIT   (PGDIR_SHIFT - PGD_T_LOG2)

Definition at line 148 of file mmu-44x.h.

#define PPC44x_PGD_OFF_SHIFT   (32 - PGDIR_SHIFT + PGD_T_LOG2)

Definition at line 147 of file mmu-44x.h.

#define PPC44x_PTE_ADD_MASK_BIT   (32 - PTE_T_LOG2 - PTE_SHIFT)

Definition at line 150 of file mmu-44x.h.

#define PPC44x_PTE_ADD_SHIFT   (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)

Definition at line 149 of file mmu-44x.h.

#define PPC44x_TLB_16K   0x00000020

Definition at line 22 of file mmu-44x.h.

#define PPC44x_TLB_16M   0x00000070

Definition at line 26 of file mmu-44x.h.

#define PPC44x_TLB_1K   0x00000000 /* Page sizes */

Definition at line 20 of file mmu-44x.h.

#define PPC44x_TLB_1M   0x00000050

Definition at line 25 of file mmu-44x.h.

#define PPC44x_TLB_256K   0x00000040

Definition at line 24 of file mmu-44x.h.

#define PPC44x_TLB_256M   0x00000090

Definition at line 27 of file mmu-44x.h.

#define PPC44x_TLB_4K   0x00000010

Definition at line 21 of file mmu-44x.h.

#define PPC44x_TLB_64K   0x00000030

Definition at line 23 of file mmu-44x.h.

#define PPC44x_TLB_ATTR_MASK   0x0000ff80

Definition at line 34 of file mmu-44x.h.

#define PPC44x_TLB_ATTRIB   2

Definition at line 14 of file mmu-44x.h.

#define PPC44x_TLB_E   0x00000080 /* Memory is little endian */

Definition at line 43 of file mmu-44x.h.

#define PPC44x_TLB_EPN_MASK   0xfffffc00 /* Effective Page Number */

Definition at line 17 of file mmu-44x.h.

#define PPC44x_TLB_ERPN_MASK   0x0000000f

Definition at line 31 of file mmu-44x.h.

#define PPC44x_TLB_G   0x00000100 /* Memory is guarded */

Definition at line 42 of file mmu-44x.h.

#define PPC44x_TLB_I   0x00000400 /* Caching is inhibited */

Definition at line 40 of file mmu-44x.h.

#define PPC44x_TLB_M   0x00000200 /* Memory is coherent */

Definition at line 41 of file mmu-44x.h.

#define PPC44x_TLB_PAGEID   0

Definition at line 12 of file mmu-44x.h.

#define PPC44x_TLB_PERM_MASK   0x0000003f

Definition at line 45 of file mmu-44x.h.

#define PPC44x_TLB_RPN_MASK   0xfffffc00 /* Real Page Number */

Definition at line 30 of file mmu-44x.h.

#define PPC44x_TLB_SIZE   64

Definition at line 54 of file mmu-44x.h.

#define PPC44x_TLB_SR   0x00000001 /* Super read */

Definition at line 51 of file mmu-44x.h.

#define PPC44x_TLB_SW   0x00000002 /* Super write */

Definition at line 50 of file mmu-44x.h.

#define PPC44x_TLB_SX   0x00000004 /* Super execution */

Definition at line 49 of file mmu-44x.h.

#define PPC44x_TLB_TS   0x00000100 /* Translation address space */

Definition at line 19 of file mmu-44x.h.

#define PPC44x_TLB_U0   0x00008000 /* User 0 */

Definition at line 35 of file mmu-44x.h.

#define PPC44x_TLB_U1   0x00004000 /* User 1 */

Definition at line 36 of file mmu-44x.h.

#define PPC44x_TLB_U2   0x00002000 /* User 2 */

Definition at line 37 of file mmu-44x.h.

#define PPC44x_TLB_U3   0x00001000 /* User 3 */

Definition at line 38 of file mmu-44x.h.

#define PPC44x_TLB_UR   0x00000008 /* User read */

Definition at line 48 of file mmu-44x.h.

#define PPC44x_TLB_UW   0x00000010 /* User write */

Definition at line 47 of file mmu-44x.h.

#define PPC44x_TLB_UX   0x00000020 /* User execution */

Definition at line 46 of file mmu-44x.h.

#define PPC44x_TLB_VALID   0x00000200 /* Valid flag */

Definition at line 18 of file mmu-44x.h.

#define PPC44x_TLB_W   0x00000800 /* Caching is write-through */

Definition at line 39 of file mmu-44x.h.

#define PPC44x_TLB_XLAT   1

Definition at line 13 of file mmu-44x.h.

#define PPC47x_MMUCR_STS   0x00010000

Definition at line 58 of file mmu-44x.h.

#define PPC47x_MMUCR_TID   0x0000ffff

Definition at line 57 of file mmu-44x.h.

#define PPC47x_TLB0_16K   0x00000010

Definition at line 65 of file mmu-44x.h.

#define PPC47x_TLB0_16M   0x000000f0

Definition at line 68 of file mmu-44x.h.

#define PPC47x_TLB0_1G   0x000003f0

Definition at line 70 of file mmu-44x.h.

#define PPC47x_TLB0_1M   0x00000070

Definition at line 67 of file mmu-44x.h.

#define PPC47x_TLB0_256M   0x000001f0

Definition at line 69 of file mmu-44x.h.

#define PPC47x_TLB0_4K   0x00000000

Definition at line 64 of file mmu-44x.h.

#define PPC47x_TLB0_64K   0x00000030

Definition at line 66 of file mmu-44x.h.

#define PPC47x_TLB0_BOLTED_R   0x00000008 /* tlbre only */

Definition at line 71 of file mmu-44x.h.

#define PPC47x_TLB0_EPN_MASK   0xfffff000 /* Effective Page Number */

Definition at line 61 of file mmu-44x.h.

#define PPC47x_TLB0_TS   0x00000400 /* Translation address space */

Definition at line 63 of file mmu-44x.h.

#define PPC47x_TLB0_VALID   0x00000800 /* Valid flag */

Definition at line 62 of file mmu-44x.h.

#define PPC47x_TLB1_ERPN_MASK   0x000003ff

Definition at line 75 of file mmu-44x.h.

#define PPC47x_TLB1_RPN_MASK   0xfffff000 /* Real Page Number */

Definition at line 74 of file mmu-44x.h.

#define PPC47x_TLB2_ATTR_MASK   0x0003ff80

Definition at line 78 of file mmu-44x.h.

#define PPC47x_TLB2_E   0x00000080 /* Memory is little endian */

Definition at line 89 of file mmu-44x.h.

#define PPC47x_TLB2_G   0x00000100 /* Memory is guarded */

Definition at line 88 of file mmu-44x.h.

#define PPC47x_TLB2_I   0x00000400 /* Caching is inhibited */

Definition at line 86 of file mmu-44x.h.

#define PPC47x_TLB2_IL1D   0x00010000 /* Memory is guarded */

Definition at line 80 of file mmu-44x.h.

#define PPC47x_TLB2_IL1I   0x00020000 /* Memory is guarded */

Definition at line 79 of file mmu-44x.h.

#define PPC47x_TLB2_IMG   (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)

Definition at line 100 of file mmu-44x.h.

#define PPC47x_TLB2_M   0x00000200 /* Memory is coherent */

Definition at line 87 of file mmu-44x.h.

#define PPC47x_TLB2_PERM_MASK   0x0000003f

Definition at line 90 of file mmu-44x.h.

#define PPC47x_TLB2_S_RW   (PPC47x_TLB2_SW | PPC47x_TLB2_SR)

Definition at line 99 of file mmu-44x.h.

#define PPC47x_TLB2_S_RWX   (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)

Definition at line 98 of file mmu-44x.h.

#define PPC47x_TLB2_SR   0x00000001 /* Super read */

Definition at line 96 of file mmu-44x.h.

#define PPC47x_TLB2_SW   0x00000002 /* Super write */

Definition at line 95 of file mmu-44x.h.

#define PPC47x_TLB2_SX   0x00000004 /* Super execution */

Definition at line 94 of file mmu-44x.h.

#define PPC47x_TLB2_U0   0x00008000 /* User 0 */

Definition at line 81 of file mmu-44x.h.

#define PPC47x_TLB2_U1   0x00004000 /* User 1 */

Definition at line 82 of file mmu-44x.h.

#define PPC47x_TLB2_U2   0x00002000 /* User 2 */

Definition at line 83 of file mmu-44x.h.

#define PPC47x_TLB2_U3   0x00001000 /* User 3 */

Definition at line 84 of file mmu-44x.h.

#define PPC47x_TLB2_U_RWX   (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)

Definition at line 97 of file mmu-44x.h.

#define PPC47x_TLB2_UR   0x00000008 /* User read */

Definition at line 93 of file mmu-44x.h.

#define PPC47x_TLB2_UW   0x00000010 /* User write */

Definition at line 92 of file mmu-44x.h.

#define PPC47x_TLB2_UX   0x00000020 /* User execution */

Definition at line 91 of file mmu-44x.h.

#define PPC47x_TLB2_W   0x00000800 /* Caching is write-through */

Definition at line 85 of file mmu-44x.h.

#define PPC_PIN_SIZE   (1 << 28) /* 256M */

Definition at line 124 of file mmu-44x.h.

Variable Documentation

unsigned int tlb_44x_hwater

Definition at line 39 of file 44x_mmu.c.

unsigned int tlb_44x_index

Definition at line 38 of file 44x_mmu.c.