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| #define | SPRN_MI_CTR 784 /* Instruction TLB control register */ |
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| #define | MI_GPM 0x80000000 /* Set domain manager mode */ |
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| #define | MI_PPM 0x40000000 /* Set subpage protection */ |
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| #define | MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ |
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| #define | MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ |
| |
| #define | MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ |
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| #define | MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ |
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| #define | MI_RESETVAL 0x00000000 /* Value of register at reset */ |
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| #define | SPRN_MI_AP 786 |
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| #define | MI_Ks 0x80000000 /* Should not be set */ |
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| #define | MI_Kp 0x40000000 /* Should always be set */ |
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| #define | SPRN_MI_EPN 787 |
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| #define | MI_EPNMASK 0xfffff000 /* Effective page number for entry */ |
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| #define | MI_EVALID 0x00000200 /* Entry is valid */ |
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| #define | MI_ASIDMASK 0x0000000f /* ASID match value */ |
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| #define | SPRN_MI_TWC 789 |
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| #define | MI_APG 0x000001e0 /* Access protection group (0) */ |
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| #define | MI_GUARDED 0x00000010 /* Guarded storage */ |
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| #define | MI_PSMASK 0x0000000c /* Mask of page size bits */ |
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| #define | MI_PS8MEG 0x0000000c /* 8M page size */ |
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| #define | MI_PS512K 0x00000004 /* 512K page size */ |
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| #define | MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ |
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| #define | MI_SVALID 0x00000001 /* Segment entry is valid */ |
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| #define | SPRN_MI_RPN 790 |
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| #define | MI_BOOTINIT 0x000001fd |
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| #define | SPRN_MD_CTR 792 /* Data TLB control register */ |
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| #define | MD_GPM 0x80000000 /* Set domain manager mode */ |
| |
| #define | MD_PPM 0x40000000 /* Set subpage protection */ |
| |
| #define | MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ |
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| #define | MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ |
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| #define | MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ |
| |
| #define | MD_TWAM 0x04000000 /* Use 4K page hardware assist */ |
| |
| #define | MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ |
| |
| #define | MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ |
| |
| #define | MD_RESETVAL 0x04000000 /* Value of register at reset */ |
| |
| #define | SPRN_M_CASID 793 /* Address space ID (context) to match */ |
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| #define | MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ |
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| #define | SPRN_MD_AP 794 |
| |
| #define | MD_Ks 0x80000000 /* Should not be set */ |
| |
| #define | MD_Kp 0x40000000 /* Should always be set */ |
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| #define | SPRN_MD_EPN 795 |
| |
| #define | MD_EPNMASK 0xfffff000 /* Effective page number for entry */ |
| |
| #define | MD_EVALID 0x00000200 /* Entry is valid */ |
| |
| #define | MD_ASIDMASK 0x0000000f /* ASID match value */ |
| |
| #define | SPRN_M_TWB 796 |
| |
| #define | M_L1TB 0xfffff000 /* Level 1 table base address */ |
| |
| #define | M_L1INDX 0x00000ffc /* Level 1 index, when read */ |
| |
| #define | SPRN_MD_TWC 797 |
| |
| #define | MD_L2TB 0xfffff000 /* Level 2 table base address */ |
| |
| #define | MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ |
| |
| #define | MD_APG 0x000001e0 /* Access protection group (0) */ |
| |
| #define | MD_GUARDED 0x00000010 /* Guarded storage */ |
| |
| #define | MD_PSMASK 0x0000000c /* Mask of page size bits */ |
| |
| #define | MD_PS8MEG 0x0000000c /* 8M page size */ |
| |
| #define | MD_PS512K 0x00000004 /* 512K page size */ |
| |
| #define | MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ |
| |
| #define | MD_WT 0x00000002 /* Use writethrough page attribute */ |
| |
| #define | MD_SVALID 0x00000001 /* Segment entry is valid */ |
| |
| #define | SPRN_MD_RPN 798 |
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| #define | SPRN_M_TW 799 |
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| #define | mmu_virtual_psize MMU_PAGE_4K |
| |
| #define | mmu_linear_psize MMU_PAGE_8M |
| |
1.8.2