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mmu-book3e.h
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1 #ifndef _ASM_POWERPC_MMU_BOOK3E_H_
2 #define _ASM_POWERPC_MMU_BOOK3E_H_
3 /*
4  * Freescale Book-E/Book-3e (ISA 2.06+) MMU support
5  */
6 
7 /* Book-3e defined page sizes */
8 #define BOOK3E_PAGESZ_1K 0
9 #define BOOK3E_PAGESZ_2K 1
10 #define BOOK3E_PAGESZ_4K 2
11 #define BOOK3E_PAGESZ_8K 3
12 #define BOOK3E_PAGESZ_16K 4
13 #define BOOK3E_PAGESZ_32K 5
14 #define BOOK3E_PAGESZ_64K 6
15 #define BOOK3E_PAGESZ_128K 7
16 #define BOOK3E_PAGESZ_256K 8
17 #define BOOK3E_PAGESZ_512K 9
18 #define BOOK3E_PAGESZ_1M 10
19 #define BOOK3E_PAGESZ_2M 11
20 #define BOOK3E_PAGESZ_4M 12
21 #define BOOK3E_PAGESZ_8M 13
22 #define BOOK3E_PAGESZ_16M 14
23 #define BOOK3E_PAGESZ_32M 15
24 #define BOOK3E_PAGESZ_64M 16
25 #define BOOK3E_PAGESZ_128M 17
26 #define BOOK3E_PAGESZ_256M 18
27 #define BOOK3E_PAGESZ_512M 19
28 #define BOOK3E_PAGESZ_1GB 20
29 #define BOOK3E_PAGESZ_2GB 21
30 #define BOOK3E_PAGESZ_4GB 22
31 #define BOOK3E_PAGESZ_8GB 23
32 #define BOOK3E_PAGESZ_16GB 24
33 #define BOOK3E_PAGESZ_32GB 25
34 #define BOOK3E_PAGESZ_64GB 26
35 #define BOOK3E_PAGESZ_128GB 27
36 #define BOOK3E_PAGESZ_256GB 28
37 #define BOOK3E_PAGESZ_512GB 29
38 #define BOOK3E_PAGESZ_1TB 30
39 #define BOOK3E_PAGESZ_2TB 31
40 
41 /* MAS registers bit definitions */
42 
43 #define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000)
44 #define MAS0_ESEL_MASK 0x0FFF0000
45 #define MAS0_ESEL_SHIFT 16
46 #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK)
47 #define MAS0_NV(x) ((x) & 0x00000FFF)
48 #define MAS0_HES 0x00004000
49 #define MAS0_WQ_ALLWAYS 0x00000000
50 #define MAS0_WQ_COND 0x00001000
51 #define MAS0_WQ_CLR_RSRV 0x00002000
52 
53 #define MAS1_VALID 0x80000000
54 #define MAS1_IPROT 0x40000000
55 #define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
56 #define MAS1_IND 0x00002000
57 #define MAS1_TS 0x00001000
58 #define MAS1_TSIZE_MASK 0x00000f80
59 #define MAS1_TSIZE_SHIFT 7
60 #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
61 
62 #define MAS2_EPN 0xFFFFF000
63 #define MAS2_X0 0x00000040
64 #define MAS2_X1 0x00000020
65 #define MAS2_W 0x00000010
66 #define MAS2_I 0x00000008
67 #define MAS2_M 0x00000004
68 #define MAS2_G 0x00000002
69 #define MAS2_E 0x00000001
70 #define MAS2_WIMGE_MASK 0x0000001f
71 #define MAS2_EPN_MASK(size) (~0 << (size + 10))
72 #define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
73 
74 #define MAS3_RPN 0xFFFFF000
75 #define MAS3_U0 0x00000200
76 #define MAS3_U1 0x00000100
77 #define MAS3_U2 0x00000080
78 #define MAS3_U3 0x00000040
79 #define MAS3_UX 0x00000020
80 #define MAS3_SX 0x00000010
81 #define MAS3_UW 0x00000008
82 #define MAS3_SW 0x00000004
83 #define MAS3_UR 0x00000002
84 #define MAS3_SR 0x00000001
85 #define MAS3_BAP_MASK 0x0000003f
86 #define MAS3_SPSIZE 0x0000003e
87 #define MAS3_SPSIZE_SHIFT 1
88 
89 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
90 #define MAS4_INDD 0x00008000 /* Default IND */
91 #define MAS4_TSIZED(x) MAS1_TSIZE(x)
92 #define MAS4_X0D 0x00000040
93 #define MAS4_X1D 0x00000020
94 #define MAS4_WD 0x00000010
95 #define MAS4_ID 0x00000008
96 #define MAS4_MD 0x00000004
97 #define MAS4_GD 0x00000002
98 #define MAS4_ED 0x00000001
99 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
100 #define MAS4_WIMGED_SHIFT 0
101 #define MAS4_VLED MAS4_X1D /* Default VLE */
102 #define MAS4_ACMD 0x000000c0 /* Default ACM */
103 #define MAS4_ACMD_SHIFT 6
104 #define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */
105 #define MAS4_TSIZED_SHIFT 7
106 
107 #define MAS5_SGS 0x80000000
108 
109 #define MAS6_SPID0 0x3FFF0000
110 #define MAS6_SPID1 0x00007FFE
111 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
112 #define MAS6_SAS 0x00000001
113 #define MAS6_SPID MAS6_SPID0
114 #define MAS6_SIND 0x00000002 /* Indirect page */
115 #define MAS6_SIND_SHIFT 1
116 #define MAS6_SPID_MASK 0x3fff0000
117 #define MAS6_SPID_SHIFT 16
118 #define MAS6_ISIZE_MASK 0x00000f80
119 #define MAS6_ISIZE_SHIFT 7
120 
121 #define MAS7_RPN 0xFFFFFFFF
122 
123 #define MAS8_TGS 0x80000000 /* Guest space */
124 #define MAS8_VF 0x40000000 /* Virtualization Fault */
125 #define MAS8_TLPID 0x000000ff
126 
127 /* Bit definitions for MMUCFG */
128 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
129 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
130 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
131 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
132 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
133 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
134 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
135 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
136 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
137 
138 /* Bit definitions for MMUCSR0 */
139 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
140 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
141 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
142 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
143 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
144  MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
145 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
146 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
147 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
148 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
149 
150 /* MMUCFG bits */
151 #define MMUCFG_MAVN_NASK 0x00000003
152 #define MMUCFG_MAVN_V1_0 0x00000000
153 #define MMUCFG_MAVN_V2_0 0x00000001
154 #define MMUCFG_NTLB_MASK 0x0000000c
155 #define MMUCFG_NTLB_SHIFT 2
156 #define MMUCFG_PIDSIZE_MASK 0x000007c0
157 #define MMUCFG_PIDSIZE_SHIFT 6
158 #define MMUCFG_TWC 0x00008000
159 #define MMUCFG_LRAT 0x00010000
160 #define MMUCFG_RASIZE_MASK 0x00fe0000
161 #define MMUCFG_RASIZE_SHIFT 17
162 #define MMUCFG_LPIDSIZE_MASK 0x0f000000
163 #define MMUCFG_LPIDSIZE_SHIFT 24
164 
165 /* TLBnCFG encoding */
166 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
167 #define TLBnCFG_HES 0x00002000 /* HW select supported */
168 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
169 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
170 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
171 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
172 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
173 #define TLBnCFG_MINSIZE_SHIFT 20
174 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
175 #define TLBnCFG_MAXSIZE_SHIFT 16
176 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
177 #define TLBnCFG_ASSOC_SHIFT 24
178 
179 /* TLBnPS encoding */
180 #define TLBnPS_4K 0x00000004
181 #define TLBnPS_8K 0x00000008
182 #define TLBnPS_16K 0x00000010
183 #define TLBnPS_32K 0x00000020
184 #define TLBnPS_64K 0x00000040
185 #define TLBnPS_128K 0x00000080
186 #define TLBnPS_256K 0x00000100
187 #define TLBnPS_512K 0x00000200
188 #define TLBnPS_1M 0x00000400
189 #define TLBnPS_2M 0x00000800
190 #define TLBnPS_4M 0x00001000
191 #define TLBnPS_8M 0x00002000
192 #define TLBnPS_16M 0x00004000
193 #define TLBnPS_32M 0x00008000
194 #define TLBnPS_64M 0x00010000
195 #define TLBnPS_128M 0x00020000
196 #define TLBnPS_256M 0x00040000
197 #define TLBnPS_512M 0x00080000
198 #define TLBnPS_1G 0x00100000
199 #define TLBnPS_2G 0x00200000
200 #define TLBnPS_4G 0x00400000
201 #define TLBnPS_8G 0x00800000
202 #define TLBnPS_16G 0x01000000
203 #define TLBnPS_32G 0x02000000
204 #define TLBnPS_64G 0x04000000
205 #define TLBnPS_128G 0x08000000
206 #define TLBnPS_256G 0x10000000
207 
208 /* tlbilx action encoding */
209 #define TLBILX_T_ALL 0
210 #define TLBILX_T_TID 1
211 #define TLBILX_T_FULLMATCH 3
212 #define TLBILX_T_CLASS0 4
213 #define TLBILX_T_CLASS1 5
214 #define TLBILX_T_CLASS2 6
215 #define TLBILX_T_CLASS3 7
216 
217 #ifndef __ASSEMBLY__
218 
219 extern unsigned int tlbcam_index;
220 
221 typedef struct {
222  unsigned int id;
223  unsigned int active;
224  unsigned long vdso_base;
225 #ifdef CONFIG_PPC_ICSWX
226  struct spinlock *cop_lockp; /* guard cop related stuff */
227  unsigned long acop; /* mask of enabled coprocessor types */
228 #endif /* CONFIG_PPC_ICSWX */
229 #ifdef CONFIG_PPC_MM_SLICES
230  u64 low_slices_psize; /* SLB page size encodings */
231  u64 high_slices_psize; /* 4 bits per slice for now */
232  u16 user_psize; /* page size index */
233 #endif
234 } mm_context_t;
235 
236 /* Page size definitions, common between 32 and 64-bit
237  *
238  * shift : is the "PAGE_SHIFT" value for that page size
239  * penc : is the pte encoding mask
240  *
241  */
243 {
244  unsigned int shift; /* number of bits */
245  unsigned int enc; /* PTE encoding */
246  unsigned int ind; /* Corresponding indirect page size shift */
247  unsigned int flags;
248 #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */
249 #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */
250 };
251 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
252 
253 /* The page sizes use the same names as 64-bit hash but are
254  * constants
255  */
256 #if defined(CONFIG_PPC_4K_PAGES)
257 #define mmu_virtual_psize MMU_PAGE_4K
258 #elif defined(CONFIG_PPC_64K_PAGES)
259 #define mmu_virtual_psize MMU_PAGE_64K
260 #else
261 #error Unsupported page size
262 #endif
263 
264 extern int mmu_linear_psize;
265 extern int mmu_vmemmap_psize;
266 
267 #ifdef CONFIG_PPC64
268 extern unsigned long linear_map_top;
269 
270 /*
271  * 64-bit booke platforms don't load the tlb in the tlb miss handler code.
272  * HUGETLB_NEED_PRELOAD handles this - it causes huge_ptep_set_access_flags to
273  * return 1, indicating that the tlb requires preloading.
274  */
275 #define HUGETLB_NEED_PRELOAD
276 #endif
277 
278 #endif /* !__ASSEMBLY__ */
279 
280 #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */