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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/slab.h>#include <linux/tty.h>#include <linux/tty_driver.h>#include <linux/tty_flip.h>#include <linux/module.h>#include <linux/serial.h>#include <linux/usb.h>#include <linux/usb/serial.h>#include <linux/uaccess.h>Go to the source code of this file.
Data Structures | |
| struct | moschip_port |
Macros | |
| #define | DRIVER_VERSION "1.3.2" |
| #define | DRIVER_DESC "Moschip 7840/7820 USB Serial Driver" |
| #define | LCR_BITS_5 0x00 /* 5 bits/char */ |
| #define | LCR_BITS_6 0x01 /* 6 bits/char */ |
| #define | LCR_BITS_7 0x02 /* 7 bits/char */ |
| #define | LCR_BITS_8 0x03 /* 8 bits/char */ |
| #define | LCR_BITS_MASK 0x03 /* Mask for bits/char field */ |
| #define | LCR_STOP_1 0x00 /* 1 stop bit */ |
| #define | LCR_STOP_1_5 0x04 /* 1.5 stop bits (if 5 bits/char) */ |
| #define | LCR_STOP_2 0x04 /* 2 stop bits (if 6-8 bits/char) */ |
| #define | LCR_STOP_MASK 0x04 /* Mask for stop bits field */ |
| #define | LCR_PAR_NONE 0x00 /* No parity */ |
| #define | LCR_PAR_ODD 0x08 /* Odd parity */ |
| #define | LCR_PAR_EVEN 0x18 /* Even parity */ |
| #define | LCR_PAR_MARK 0x28 /* Force parity bit to 1 */ |
| #define | LCR_PAR_SPACE 0x38 /* Force parity bit to 0 */ |
| #define | LCR_PAR_MASK 0x38 /* Mask for parity field */ |
| #define | LCR_SET_BREAK 0x40 /* Set Break condition */ |
| #define | LCR_DL_ENABLE 0x80 /* Enable access to divisor latch */ |
| #define | MCR_DTR 0x01 /* Assert DTR */ |
| #define | MCR_RTS 0x02 /* Assert RTS */ |
| #define | MCR_OUT1 0x04 /* Loopback only: Sets state of RI */ |
| #define | MCR_MASTER_IE 0x08 /* Enable interrupt outputs */ |
| #define | MCR_LOOPBACK 0x10 /* Set internal (digital) loopback mode */ |
| #define | MCR_XON_ANY 0x20 /* Enable any char to exit XOFF mode */ |
| #define | MOS7840_MSR_CTS 0x10 /* Current state of CTS */ |
| #define | MOS7840_MSR_DSR 0x20 /* Current state of DSR */ |
| #define | MOS7840_MSR_RI 0x40 /* Current state of RI */ |
| #define | MOS7840_MSR_CD 0x80 /* Current state of CD */ |
| #define | MOS_WDR_TIMEOUT 5000 /* default urb timeout */ |
| #define | MOS_PORT1 0x0200 |
| #define | MOS_PORT2 0x0300 |
| #define | MOS_VENREG 0x0000 |
| #define | MOS_MAX_PORT 0x02 |
| #define | MOS_WRITE 0x0E |
| #define | MOS_READ 0x0D |
| #define | MCS_RD_RTYPE 0xC0 |
| #define | MCS_WR_RTYPE 0x40 |
| #define | MCS_RDREQ 0x0D |
| #define | MCS_WRREQ 0x0E |
| #define | MCS_CTRL_TIMEOUT 500 |
| #define | VENDOR_READ_LENGTH (0x01) |
| #define | MAX_NAME_LEN 64 |
| #define | ZLP_REG1 0x3A /* Zero_Flag_Reg1 58 */ |
| #define | ZLP_REG5 0x3E /* Zero_Flag_Reg5 62 */ |
| #define | TIOCEXBAUD 0x5462 |
| #define | USB_VENDOR_ID_MOSCHIP 0x9710 |
| #define | MOSCHIP_DEVICE_ID_7840 0x7840 |
| #define | MOSCHIP_DEVICE_ID_7820 0x7820 |
| #define | MOSCHIP_DEVICE_ID_7810 0x7810 |
| #define | USB_VENDOR_ID_BANDB 0x0856 |
| #define | BANDB_DEVICE_ID_USO9ML2_2 0xAC22 |
| #define | BANDB_DEVICE_ID_USO9ML2_2P 0xBC00 |
| #define | BANDB_DEVICE_ID_USO9ML2_4 0xAC24 |
| #define | BANDB_DEVICE_ID_USO9ML2_4P 0xBC01 |
| #define | BANDB_DEVICE_ID_US9ML2_2 0xAC29 |
| #define | BANDB_DEVICE_ID_US9ML2_4 0xAC30 |
| #define | BANDB_DEVICE_ID_USPTL4_2 0xAC31 |
| #define | BANDB_DEVICE_ID_USPTL4_4 0xAC32 |
| #define | BANDB_DEVICE_ID_USOPTL4_2 0xAC42 |
| #define | BANDB_DEVICE_ID_USOPTL4_2P 0xBC02 |
| #define | BANDB_DEVICE_ID_USOPTL4_4 0xAC44 |
| #define | BANDB_DEVICE_ID_USOPTL4_4P 0xBC03 |
| #define | BANDB_DEVICE_ID_USOPTL2_4 0xAC24 |
| #define | USB_VENDOR_ID_ATENINTL 0x0557 |
| #define | ATENINTL_DEVICE_ID_UC2324 0x2011 |
| #define | ATENINTL_DEVICE_ID_UC2322 0x7820 |
| #define | SERIAL_IIR_RLS 0x06 |
| #define | SERIAL_IIR_MS 0x00 |
| #define | SERIAL_LSR_DR 0x0001 |
| #define | SERIAL_LSR_OE 0x0002 |
| #define | SERIAL_LSR_PE 0x0004 |
| #define | SERIAL_LSR_FE 0x0008 |
| #define | SERIAL_LSR_BI 0x0010 |
| #define | MOS_MSR_DELTA_CTS 0x10 |
| #define | MOS_MSR_DELTA_DSR 0x20 |
| #define | MOS_MSR_DELTA_RI 0x40 |
| #define | MOS_MSR_DELTA_CD 0x80 |
| #define | INTERRUPT_ENABLE_REGISTER ((__u16)(0x01)) |
| #define | FIFO_CONTROL_REGISTER ((__u16)(0x02)) |
| #define | LINE_CONTROL_REGISTER ((__u16)(0x03)) |
| #define | MODEM_CONTROL_REGISTER ((__u16)(0x04)) |
| #define | LINE_STATUS_REGISTER ((__u16)(0x05)) |
| #define | MODEM_STATUS_REGISTER ((__u16)(0x06)) |
| #define | SCRATCH_PAD_REGISTER ((__u16)(0x07)) |
| #define | DIVISOR_LATCH_LSB ((__u16)(0x00)) |
| #define | DIVISOR_LATCH_MSB ((__u16)(0x01)) |
| #define | CLK_MULTI_REGISTER ((__u16)(0x02)) |
| #define | CLK_START_VALUE_REGISTER ((__u16)(0x03)) |
| #define | GPIO_REGISTER ((__u16)(0x07)) |
| #define | SERIAL_LCR_DLAB ((__u16)(0x0080)) |
| #define | NUM_URBS 16 /* URB Count */ |
| #define | URB_TRANSFER_BUFFER_SIZE 32 /* URB Size */ |
| #define | LED_ON_MS 500 |
| #define | LED_OFF_MS 500 |
Functions | |
| MODULE_DEVICE_TABLE (usb, id_table) | |
| module_usb_serial_driver (serial_drivers, id_table) | |
| MODULE_DESCRIPTION (DRIVER_DESC) | |
| MODULE_LICENSE ("GPL") | |
| #define LCR_DL_ENABLE 0x80 /* Enable access to divisor latch */ |
| #define LCR_STOP_1_5 0x04 /* 1.5 stop bits (if 5 bits/char) */ |
| #define LCR_STOP_2 0x04 /* 2 stop bits (if 6-8 bits/char) */ |
| #define MCR_LOOPBACK 0x10 /* Set internal (digital) loopback mode */ |
| #define MCR_OUT1 0x04 /* Loopback only: Sets state of RI */ |
| #define MCR_XON_ANY 0x20 /* Enable any char to exit XOFF mode */ |
| MODULE_DESCRIPTION | ( | DRIVER_DESC | ) |
| MODULE_DEVICE_TABLE | ( | usb | , |
| id_table | |||
| ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_usb_serial_driver | ( | serial_drivers | , |
| id_table | |||
| ) |
1.8.2