#include <asm/addrspace.h>
#include <linux/types.h>

Macros
#define	MSP_SLP_BASE 0x1c000000

#define	MSP_RST_BASE (MSP_SLP_BASE + 0x10)

#define	MSP_RST_SIZE 0x0C /* System reset register space */

#define	MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)

#define	MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)

#define	MSP_UART0_BASE (MSP_SLP_BASE + 0x100)

#define	MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)

#define	MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)

#define	MSP_PCI_BASE 0x19000000

#define	MSP_MSB_BASE 0x18000000

#define	MSP_PER_BASE (MSP_MSB_BASE + 0x400000)

#define	MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)

#define	MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)

#define	MSP_MAC_SIZE 0xE0 /* MAC register space */

#define	MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)

#define	MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)

#define	MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)

#define	MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)

#define	MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)

#define	MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)

#define	MSP_UART1_BASE (MSP_PER_BASE + 0x030)

#define	MSP_SPI_BASE (MSP_PER_BASE + 0x058)

#define	MSP_TWI_BASE (MSP_PER_BASE + 0x090)

#define	MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)

#define	MSP_MEM_CFG_BASE 0x17f00000

#define	MSP_MEM_INDIRECT_CTL_10 0x10

#define	regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))

#define	DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)

#define	FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)

#define	SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)

#define	SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)

#define	RST_STS_REG regptr(MSP_SLP_BASE + 0x10)

#define	RST_SET_REG regptr(MSP_SLP_BASE + 0x14)

#define	RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)

#define	PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)

#define	URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)

#define	PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)

#define	PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)

#define	MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)

#define	VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)

#define	MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)

#define	SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)

#define	PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)

#define	SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)

#define	SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)

#define	SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)

#define	VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)

#define	CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)

#define	CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)

#define	CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)

#define	CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)

#define	CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)

#define	CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)

#define	CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)

#define	CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)

#define	CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)

#define	CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)

#define	CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)

#define	CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)

#define	CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)

#define	CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)

#define	CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)

#define	CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)

#define	CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)

#define	CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)

#define	CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)

#define	CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)

#define	CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)

#define	CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)

#define	CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)

#define	CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)

#define	ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)

#define	ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)

#define	UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)

#define	UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)

#define	PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)

#define	PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)

#define	PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)

#define	PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)

#define	SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)

#define	SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)

#define	SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)

#define	SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)

#define	VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)

#define	CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)

#define	CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)

#define	EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)

#define	EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)

#define	EXTENDED_GPIO_REG EXTENDED_GPIO1_REG

#define	SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)

#define	SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)

#define	SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)

#define	SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)

#define	CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)

#define	CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)

#define	CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)

#define	CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)

#define	CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)

#define	PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)

#define	PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)

#define	PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)

#define	PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)

#define	PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)

#define	PER_STS_REG regptr(MSP_PER_BASE + 0x54)

#define	SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)

#define	SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)

#define	SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)

#define	SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)

#define	SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)

#define	SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)

#define	SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)

#define	SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)

#define	SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)

#define	PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)

#define	PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)

#define	PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)

#define	PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)

#define	PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)

#define	PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)

#define	GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)

#define	GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)

#define	POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)

#define	POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)

#define	POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)

#define	POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)

#define	POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)

#define	POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)

#define	POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)

#define	POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)

#define	POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)

#define	POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)

#define	POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)

#define	POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)

#define	POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)

#define	POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)

#define	POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)

#define	POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)

#define	GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)

#define	GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)

#define	GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)

#define	GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)

#define	GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)

#define	GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)

#define	GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)

#define	GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)

#define	GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)

#define	PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)

#define	OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)

#define	OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)

#define	OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)

#define	CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)

#define	CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)

#define	MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)

#define	CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)

#define	CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)

#define	CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)

#define	CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)

#define	CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)

#define	CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)

#define	CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)

#define	CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)

#define	CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)

#define	CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)

#define	CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)

#define	CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)

#define	CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)

#define	MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)

#define	MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)

#define	MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)

#define	MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)

#define	PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)

#define	PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)

#define	PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)

#define	DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */

#define	DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */

#define	DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */

#define	DEV_ID_FAMILY (0xff << 8) /* family ID code */

#define	POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */

#define	MSPFPGA_ID (0x00 << 8) /* you are on your own here */

#define	MSP5000_ID (0x50 << 8)

#define	MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */

#define	MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */

#define	MSP4200_ID (0x42 << 8)

#define	MSP4000_ID (0x40 << 8)

#define	MSP2XXX_ID (0x20 << 8)

#define	MSPZEUS_ID (0x10 << 8)

#define	MSP2004_SUB_ID (0x0 << 16)

#define	MSP2005_SUB_ID (0x1 << 16)

#define	MSP2006_SUB_ID (0x1 << 16)

#define	MSP2007_SUB_ID (0x2 << 16)

#define	MSP2010_SUB_ID (0x3 << 16)

#define	MSP2015_SUB_ID (0x4 << 16)

#define	MSP2020_SUB_ID (0x5 << 16)

#define	MSP2100_SUB_ID (0x6 << 16)

#define	MSP_GR_RST (0x01 << 0) /* Global reset bit */

#define	MSP_MR_RST (0x01 << 1) /* MIPS reset bit */

#define	MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */

#define	MSP_PP_RST (0x01 << 3) /* PVC reset bit */

#define	MSP_EA_RST (0x01 << 6) /* Mac A reset bit */

#define	MSP_EB_RST (0x01 << 7) /* Mac B reset bit */

#define	MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */

#define	MSP_PB_RST (0x01 << 9) /* Per block reset bit */

#define	MSP_EC_RST (0x01 << 10) /* Mac C reset bit */

#define	MSP_TW_RST (0x01 << 11) /* TWI reset bit */

#define	MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */

#define	MSP_U1_RST (0x01 << 13) /* UART1 reset bit */

#define	MSP_U0_RST (0x01 << 14) /* UART0 reset bit */

#define	MSP_BASE_BAUD 25000000

#define	MSP_UART_REG_LEN 0x20

#define	PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */

#define	SINGLE_PCCARD 0x01 /* Set to enable single PC card */

#define	EXT_INT_POL(eirq) (1 << (eirq + 8))

#define	EXT_INT_EDGE(eirq) (1 << eirq)

#define	CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq))

#define	CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg \|= EXT_INT_EDGE(eirq))

#define	CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg \|= EXT_INT_POL(eirq))

#define	CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq))

#define	CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI

#define	CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO

#define	CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) ((reg & EXT_INT_EDGE(eirq)) == 0)

#define	CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq))

#define	CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq))

#define	CIC_EXT_IS_ACTIVE_LO(reg, eirq) ((reg & EXT_INT_POL(eirq)) == 0)

#define	CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI

#define	CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO

#define	DDRC_CFG(n) (n)

#define	DDRC_DEBUG(n) (0x04 + n)

#define	DDRC_CTL(n) (0x40 + n)

#define	DDRC_INDIRECT_WRITE(reg, mask, value)

#define	SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */

#define	SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */

#define	SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */

#define	SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */

#define	SPI_MPI_RX_START 0x00000004 /* Start receive command */

#define	SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */

#define	SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */

Macro Definition Documentation

#define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00)

Definition at line 486 of file msp_regs.h.

#define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO

Definition at line 624 of file msp_regs.h.

#define CIC_EXT_IS_ACTIVE_HI	(	reg,
		eirq
	)	(reg & EXT_INT_POL(eirq))

Definition at line 620 of file msp_regs.h.

#define CIC_EXT_IS_ACTIVE_LO	(	reg,
		eirq
	)	((reg & EXT_INT_POL(eirq)) == 0)

Definition at line 621 of file msp_regs.h.

#define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI

Definition at line 623 of file msp_regs.h.

#define CIC_EXT_IS_TRIGGER_EDGE	(	reg,
		eirq
	)	(reg & EXT_INT_EDGE(eirq))

Definition at line 619 of file msp_regs.h.

#define CIC_EXT_IS_TRIGGER_LEVEL	(	reg,
		eirq
	)	((reg & EXT_INT_EDGE(eirq)) == 0)

Definition at line 617 of file msp_regs.h.

#define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO

Definition at line 615 of file msp_regs.h.

#define CIC_EXT_SET_ACTIVE_HI	(	reg,
		eirq
	)	(reg \|= EXT_INT_POL(eirq))

Definition at line 612 of file msp_regs.h.

#define CIC_EXT_SET_ACTIVE_LO	(	reg,
		eirq
	)	(reg &= ~EXT_INT_POL(eirq))

Definition at line 613 of file msp_regs.h.

#define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI

Definition at line 614 of file msp_regs.h.

#define CIC_EXT_SET_TRIGGER_EDGE	(	reg,
		eirq
	)	(reg \|= EXT_INT_EDGE(eirq))

Definition at line 611 of file msp_regs.h.

#define CIC_EXT_SET_TRIGGER_LEVEL	(	reg,
		eirq
	)	(reg &= ~EXT_INT_EDGE(eirq))

Definition at line 610 of file msp_regs.h.

#define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18)

Definition at line 506 of file msp_regs.h.

#define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18)

Definition at line 505 of file msp_regs.h.

#define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18)

Definition at line 504 of file msp_regs.h.

#define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04)

Definition at line 488 of file msp_regs.h.

#define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10)

Definition at line 494 of file msp_regs.h.

#define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14)

Definition at line 496 of file msp_regs.h.

#define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18)

Definition at line 498 of file msp_regs.h.

#define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18)

Definition at line 500 of file msp_regs.h.

#define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18)

Definition at line 502 of file msp_regs.h.

#define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08)

Definition at line 490 of file msp_regs.h.

#define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08)

Definition at line 507 of file msp_regs.h.

#define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C)

Definition at line 492 of file msp_regs.h.

#define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)

Definition at line 315 of file msp_regs.h.

#define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)

Definition at line 317 of file msp_regs.h.

#define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10)

Definition at line 480 of file msp_regs.h.

#define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10)

Definition at line 478 of file msp_regs.h.

#define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)

Definition at line 228 of file msp_regs.h.

#define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)

Definition at line 224 of file msp_regs.h.

#define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)

Definition at line 222 of file msp_regs.h.

#define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)

Definition at line 337 of file msp_regs.h.

#define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)

Definition at line 226 of file msp_regs.h.

#define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)

Definition at line 237 of file msp_regs.h.

#define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)

Definition at line 233 of file msp_regs.h.

#define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)

Definition at line 231 of file msp_regs.h.

#define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)

Definition at line 339 of file msp_regs.h.

#define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)

Definition at line 235 of file msp_regs.h.

#define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)

Definition at line 246 of file msp_regs.h.

#define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)

Definition at line 242 of file msp_regs.h.

#define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)

Definition at line 240 of file msp_regs.h.

#define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)

Definition at line 341 of file msp_regs.h.

#define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)

Definition at line 244 of file msp_regs.h.

#define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)

Definition at line 255 of file msp_regs.h.

#define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)

Definition at line 251 of file msp_regs.h.

#define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)

Definition at line 249 of file msp_regs.h.

#define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)

Definition at line 343 of file msp_regs.h.

#define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)

Definition at line 253 of file msp_regs.h.

#define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)

Definition at line 264 of file msp_regs.h.

#define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)

Definition at line 260 of file msp_regs.h.

#define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)

Definition at line 258 of file msp_regs.h.

#define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)

Definition at line 262 of file msp_regs.h.

#define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)

Definition at line 273 of file msp_regs.h.

#define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)

Definition at line 269 of file msp_regs.h.

#define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)

Definition at line 267 of file msp_regs.h.

#define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)

Definition at line 346 of file msp_regs.h.

#define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)

Definition at line 271 of file msp_regs.h.

#define DDRC_CFG ( n ) (n)

Definition at line 633 of file msp_regs.h.

#define DDRC_CTL ( n ) (0x40 + n)

Definition at line 635 of file msp_regs.h.

#define DDRC_DEBUG ( n ) (0x04 + n)

Definition at line 634 of file msp_regs.h.

#define DDRC_INDIRECT_WRITE	(	reg,
		mask,
		value
	)

Value:

({ \
    *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
    *MEM_SS_DATA = (value); \
    *MEM_SS_WRITE = 1; \
})

Definition at line 638 of file msp_regs.h.

#define DEV_ID_FAMILY (0xff << 8) /* family ID code */

Definition at line 543 of file msp_regs.h.

#define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */

Definition at line 540 of file msp_regs.h.

#define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */

Definition at line 541 of file msp_regs.h.

#define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)

Definition at line 171 of file msp_regs.h.

#define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */

Definition at line 542 of file msp_regs.h.

#define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)

Definition at line 277 of file msp_regs.h.

#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)

Definition at line 281 of file msp_regs.h.

#define EXT_INT_EDGE ( eirq ) (1 << eirq)

Definition at line 608 of file msp_regs.h.

#define EXT_INT_POL ( eirq ) (1 << (eirq + 8))

Definition at line 607 of file msp_regs.h.

#define EXTENDED_GPIO1_REG regptr(MSP_SLP_BASE + 0x188)

Definition at line 321 of file msp_regs.h.

#define EXTENDED_GPIO2_REG regptr(MSP_SLP_BASE + 0x18c)

Definition at line 322 of file msp_regs.h.

#define EXTENDED_GPIO_REG EXTENDED_GPIO1_REG

Definition at line 323 of file msp_regs.h.

#define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)

Definition at line 173 of file msp_regs.h.

#define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180)

Definition at line 454 of file msp_regs.h.

#define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184)

Definition at line 456 of file msp_regs.h.

#define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188)

Definition at line 458 of file msp_regs.h.

#define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)

Definition at line 460 of file msp_regs.h.

#define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170)

Definition at line 446 of file msp_regs.h.

#define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174)

Definition at line 448 of file msp_regs.h.

#define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178)

Definition at line 450 of file msp_regs.h.

#define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C)

Definition at line 452 of file msp_regs.h.

#define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C)

Definition at line 408 of file msp_regs.h.

#define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88)

Definition at line 406 of file msp_regs.h.

#define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190)

Definition at line 462 of file msp_regs.h.

#define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00)

Definition at line 515 of file msp_regs.h.

#define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00)

Definition at line 516 of file msp_regs.h.

#define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04)

Definition at line 517 of file msp_regs.h.

#define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08)

Definition at line 518 of file msp_regs.h.

#define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)

Definition at line 199 of file msp_regs.h.

#define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)

Definition at line 204 of file msp_regs.h.

#define MSP2004_SUB_ID (0x0 << 16)

Definition at line 555 of file msp_regs.h.

#define MSP2005_SUB_ID (0x1 << 16)

Definition at line 556 of file msp_regs.h.

#define MSP2006_SUB_ID (0x1 << 16)

Definition at line 557 of file msp_regs.h.

#define MSP2007_SUB_ID (0x2 << 16)

Definition at line 558 of file msp_regs.h.

#define MSP2010_SUB_ID (0x3 << 16)

Definition at line 559 of file msp_regs.h.

#define MSP2015_SUB_ID (0x4 << 16)

Definition at line 560 of file msp_regs.h.

#define MSP2020_SUB_ID (0x5 << 16)

Definition at line 561 of file msp_regs.h.

#define MSP2100_SUB_ID (0x6 << 16)

Definition at line 562 of file msp_regs.h.

#define MSP2XXX_ID (0x20 << 8)

Definition at line 552 of file msp_regs.h.

#define MSP4000_ID (0x40 << 8)

Definition at line 551 of file msp_regs.h.

#define MSP4200_ID (0x42 << 8)

Definition at line 550 of file msp_regs.h.

#define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */

Definition at line 549 of file msp_regs.h.

#define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */

Definition at line 548 of file msp_regs.h.

#define MSP5000_ID (0x50 << 8)

Definition at line 547 of file msp_regs.h.

#define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000)

Definition at line 92 of file msp_regs.h.

#define MSP_BASE_BAUD 25000000

Definition at line 589 of file msp_regs.h.

#define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)

Definition at line 61 of file msp_regs.h.

#define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)

Definition at line 63 of file msp_regs.h.

#define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000)

Definition at line 484 of file msp_regs.h.

#define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000)

Definition at line 98 of file msp_regs.h.

#define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */

Definition at line 574 of file msp_regs.h.

#define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */

Definition at line 575 of file msp_regs.h.

#define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */

Definition at line 578 of file msp_regs.h.

#define MSP_GR_RST (0x01 << 0) /* Global reset bit */

Definition at line 569 of file msp_regs.h.

#define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)

Definition at line 57 of file msp_regs.h.

#define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000)

Definition at line 82 of file msp_regs.h.

#define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000)

Definition at line 84 of file msp_regs.h.

#define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000)

Definition at line 90 of file msp_regs.h.

#define MSP_MAC_SIZE 0xE0 /* MAC register space */

Definition at line 86 of file msp_regs.h.

#define MSP_MEM_CFG_BASE 0x17f00000

Definition at line 116 of file msp_regs.h.

#define MSP_MEM_INDIRECT_CTL_10 0x10

Definition at line 118 of file msp_regs.h.

#define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */

Definition at line 570 of file msp_regs.h.

#define MSP_MSB_BASE 0x18000000

Definition at line 78 of file msp_regs.h.

#define MSP_PB_RST (0x01 << 9) /* Per block reset bit */

Definition at line 577 of file msp_regs.h.

#define MSP_PCI_BASE 0x19000000

Definition at line 71 of file msp_regs.h.

#define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */

Definition at line 571 of file msp_regs.h.

#define MSP_PER_BASE (MSP_MSB_BASE + 0x400000)

Definition at line 80 of file msp_regs.h.

#define MSP_PP_RST (0x01 << 3) /* PVC reset bit */

Definition at line 572 of file msp_regs.h.

#define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0)

Definition at line 108 of file msp_regs.h.

#define MSP_RST_BASE (MSP_SLP_BASE + 0x10)

Definition at line 51 of file msp_regs.h.

#define MSP_RST_SIZE 0x0C /* System reset register space */

Definition at line 53 of file msp_regs.h.

#define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */

Definition at line 576 of file msp_regs.h.

#define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000)

Definition at line 88 of file msp_regs.h.

#define MSP_SLP_BASE 0x1c000000

Definition at line 49 of file msp_regs.h.

#define MSP_SPI_BASE (MSP_PER_BASE + 0x058)

Definition at line 104 of file msp_regs.h.

#define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */

Definition at line 580 of file msp_regs.h.

#define MSP_TW_RST (0x01 << 11) /* TWI reset bit */

Definition at line 579 of file msp_regs.h.

#define MSP_TWI_BASE (MSP_PER_BASE + 0x090)

Definition at line 106 of file msp_regs.h.

#define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */

Definition at line 582 of file msp_regs.h.

#define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */

Definition at line 581 of file msp_regs.h.

#define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)

Definition at line 59 of file msp_regs.h.

#define MSP_UART1_BASE (MSP_PER_BASE + 0x030)

Definition at line 102 of file msp_regs.h.

#define MSP_UART_REG_LEN 0x20

Definition at line 590 of file msp_regs.h.

#define MSP_USB0_BASE (MSP_MSB_BASE + 0xB00000)

Definition at line 94 of file msp_regs.h.

#define MSP_USB1_BASE (MSP_MSB_BASE + 0x300000)

Definition at line 96 of file msp_regs.h.

#define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)

Definition at line 55 of file msp_regs.h.

#define MSPFPGA_ID (0x00 << 8) /* you are on your own here */

Definition at line 546 of file msp_regs.h.

#define MSPZEUS_ID (0x10 << 8)

Definition at line 553 of file msp_regs.h.

#define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04)

Definition at line 472 of file msp_regs.h.

#define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08)

Definition at line 474 of file msp_regs.h.

#define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C)

Definition at line 476 of file msp_regs.h.

#define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */

Definition at line 597 of file msp_regs.h.

#define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00)

Definition at line 525 of file msp_regs.h.

#define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800)

Definition at line 526 of file msp_regs.h.

#define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00)

Definition at line 470 of file msp_regs.h.

#define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)

Definition at line 527 of file msp_regs.h.

#define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)

Definition at line 189 of file msp_regs.h.

#define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50)

Definition at line 366 of file msp_regs.h.

#define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74)

Definition at line 394 of file msp_regs.h.

#define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70)

Definition at line 392 of file msp_regs.h.

#define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78)

Definition at line 396 of file msp_regs.h.

#define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C)

Definition at line 398 of file msp_regs.h.

#define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84)

Definition at line 404 of file msp_regs.h.

#define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80)

Definition at line 402 of file msp_regs.h.

#define PER_STS_REG regptr(MSP_PER_BASE + 0x54)

Definition at line 368 of file msp_regs.h.

#define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)

Definition at line 293 of file msp_regs.h.

#define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)

Definition at line 295 of file msp_regs.h.

#define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)

Definition at line 297 of file msp_regs.h.

#define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)

Definition at line 291 of file msp_regs.h.

#define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)

Definition at line 208 of file msp_regs.h.

#define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)

Definition at line 354 of file msp_regs.h.

#define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)

Definition at line 197 of file msp_regs.h.

#define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)

Definition at line 356 of file msp_regs.h.

#define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)

Definition at line 195 of file msp_regs.h.

#define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)

Definition at line 352 of file msp_regs.h.

#define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)

Definition at line 350 of file msp_regs.h.

#define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4)

Definition at line 414 of file msp_regs.h.

#define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8)

Definition at line 416 of file msp_regs.h.

#define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170)

Definition at line 420 of file msp_regs.h.

#define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C)

Definition at line 434 of file msp_regs.h.

#define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190)

Definition at line 436 of file msp_regs.h.

#define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194)

Definition at line 438 of file msp_regs.h.

#define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198)

Definition at line 440 of file msp_regs.h.

#define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0)

Definition at line 412 of file msp_regs.h.

#define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174)

Definition at line 422 of file msp_regs.h.

#define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178)

Definition at line 424 of file msp_regs.h.

#define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C)

Definition at line 426 of file msp_regs.h.

#define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180)

Definition at line 428 of file msp_regs.h.

#define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184)

Definition at line 430 of file msp_regs.h.

#define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188)

Definition at line 432 of file msp_regs.h.

#define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC)

Definition at line 418 of file msp_regs.h.

#define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C)

Definition at line 442 of file msp_regs.h.

#define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */

Definition at line 544 of file msp_regs.h.

#define regptr ( addr ) ((volatile u32 *const)(KSEG1ADDR(addr)))

Definition at line 161 of file msp_regs.h.

#define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)

Definition at line 185 of file msp_regs.h.

#define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)

Definition at line 183 of file msp_regs.h.

#define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)

Definition at line 181 of file msp_regs.h.

#define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)

Definition at line 216 of file msp_regs.h.

#define SINGLE_PCCARD 0x01 /* Set to enable single PC card */

Definition at line 598 of file msp_regs.h.

#define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)

Definition at line 333 of file msp_regs.h.

#define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)

Definition at line 331 of file msp_regs.h.

#define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)

Definition at line 329 of file msp_regs.h.

#define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)

Definition at line 327 of file msp_regs.h.

#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)

Definition at line 214 of file msp_regs.h.

#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)

Definition at line 212 of file msp_regs.h.

#define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)

Definition at line 206 of file msp_regs.h.

#define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4)

Definition at line 382 of file msp_regs.h.

#define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0)

Definition at line 380 of file msp_regs.h.

#define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC)

Definition at line 386 of file msp_regs.h.

#define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8)

Definition at line 384 of file msp_regs.h.

#define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60)

Definition at line 376 of file msp_regs.h.

#define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0)

Definition at line 388 of file msp_regs.h.

#define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64)

Definition at line 378 of file msp_regs.h.

#define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C)

Definition at line 374 of file msp_regs.h.

#define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58)

Definition at line 372 of file msp_regs.h.

#define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */

Definition at line 651 of file msp_regs.h.

#define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */

Definition at line 653 of file msp_regs.h.

#define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */

Definition at line 661 of file msp_regs.h.

#define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */

Definition at line 650 of file msp_regs.h.

#define SPI_MPI_RX_START 0x00000004 /* Start receive command */

Definition at line 660 of file msp_regs.h.

#define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */

Definition at line 652 of file msp_regs.h.

#define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */

Definition at line 662 of file msp_regs.h.

#define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)

Definition at line 301 of file msp_regs.h.

#define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)

Definition at line 303 of file msp_regs.h.

#define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)

Definition at line 305 of file msp_regs.h.

#define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)

Definition at line 175 of file msp_regs.h.

#define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)

Definition at line 177 of file msp_regs.h.

#define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)

Definition at line 307 of file msp_regs.h.

#define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0)

Definition at line 285 of file msp_regs.h.

#define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170)

Definition at line 287 of file msp_regs.h.

#define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)

Definition at line 191 of file msp_regs.h.

#define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)

Definition at line 218 of file msp_regs.h.

#define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)

Definition at line 311 of file msp_regs.h.

#define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)

Definition at line 201 of file msp_regs.h.

Macros

Macro Definition Documentation