| enum | hw_registers {
MVS_GBL_CTL = 0x04,
MVS_GBL_INT_STAT = 0x08,
MVS_GBL_PI = 0x0C,
MVS_PHY_CTL = 0x40,
MVS_PORTS_IMP = 0x9C,
MVS_GBL_PORT_TYPE = 0xa0,
MVS_CTL = 0x100,
MVS_PCS = 0x104,
MVS_CMD_LIST_LO = 0x108,
MVS_CMD_LIST_HI = 0x10C,
MVS_RX_FIS_LO = 0x110,
MVS_RX_FIS_HI = 0x114,
MVS_TX_CFG = 0x120,
MVS_TX_LO = 0x124,
MVS_TX_HI = 0x128,
MVS_TX_PROD_IDX = 0x12C,
MVS_TX_CONS_IDX = 0x130,
MVS_RX_CFG = 0x134,
MVS_RX_LO = 0x138,
MVS_RX_HI = 0x13C,
MVS_RX_CONS_IDX = 0x140,
MVS_INT_COAL = 0x148,
MVS_INT_COAL_TMOUT = 0x14C,
MVS_INT_STAT = 0x150,
MVS_INT_MASK = 0x154,
MVS_INT_STAT_SRS_0 = 0x158,
MVS_INT_MASK_SRS_0 = 0x15C,
MVS_P0_INT_STAT = 0x160,
MVS_P0_INT_MASK = 0x164,
MVS_P4_INT_STAT = 0x200,
MVS_P4_INT_MASK = 0x204,
MVS_P0_SER_CTLSTAT = 0x180,
MVS_P4_SER_CTLSTAT = 0x220,
MVS_CMD_ADDR = 0x1B8,
MVS_CMD_DATA = 0x1BC,
MVS_P0_CFG_ADDR = 0x1C0,
MVS_P0_CFG_DATA = 0x1C4,
MVS_P4_CFG_ADDR = 0x230,
MVS_P4_CFG_DATA = 0x234,
MVS_P0_VSR_ADDR = 0x1E0,
MVS_P0_VSR_DATA = 0x1E4,
MVS_P4_VSR_ADDR = 0x250,
MVS_P4_VSR_DATA = 0x254,
MVS_GBL_CTL = 0x04,
MVS_GBL_INT_STAT = 0x00,
MVS_GBL_PI = 0x0C,
MVS_PHY_CTL = 0x40,
MVS_PORTS_IMP = 0x9C,
MVS_GBL_PORT_TYPE = 0xa0,
MVS_CTL = 0x100,
MVS_PCS = 0x104,
MVS_CMD_LIST_LO = 0x108,
MVS_CMD_LIST_HI = 0x10C,
MVS_RX_FIS_LO = 0x110,
MVS_RX_FIS_HI = 0x114,
MVS_STP_REG_SET_0 = 0x118,
MVS_STP_REG_SET_1 = 0x11C,
MVS_TX_CFG = 0x120,
MVS_TX_LO = 0x124,
MVS_TX_HI = 0x128,
MVS_TX_PROD_IDX = 0x12C,
MVS_TX_CONS_IDX = 0x130,
MVS_RX_CFG = 0x134,
MVS_RX_LO = 0x138,
MVS_RX_HI = 0x13C,
MVS_RX_CONS_IDX = 0x140,
MVS_INT_COAL = 0x148,
MVS_INT_COAL_TMOUT = 0x14C,
MVS_INT_STAT = 0x150,
MVS_INT_MASK = 0x154,
MVS_INT_STAT_SRS_0 = 0x158,
MVS_INT_MASK_SRS_0 = 0x15C,
MVS_INT_STAT_SRS_1 = 0x160,
MVS_INT_MASK_SRS_1 = 0x164,
MVS_NON_NCQ_ERR_0 = 0x168,
MVS_NON_NCQ_ERR_1 = 0x16C,
MVS_CMD_ADDR = 0x170,
MVS_CMD_DATA = 0x174,
MVS_MEM_PARITY_ERR = 0x178,
MVS_P0_INT_STAT = 0x180,
MVS_P0_INT_MASK = 0x184,
MVS_P4_INT_STAT = 0x1A0,
MVS_P4_INT_MASK = 0x1A4,
MVS_P0_SER_CTLSTAT = 0x1D0,
MVS_P4_SER_CTLSTAT = 0x1E0,
MVS_P0_CFG_ADDR = 0x200,
MVS_P0_CFG_DATA = 0x204,
MVS_P4_CFG_ADDR = 0x220,
MVS_P4_CFG_DATA = 0x224,
MVS_P0_VSR_ADDR = 0x250,
MVS_P0_VSR_DATA = 0x254,
MVS_P4_VSR_ADDR = 0x250,
MVS_P4_VSR_DATA = 0x254,
MVS_PA_VSR_ADDR = 0x290,
MVS_PA_VSR_PORT = 0x294,
MVS_COMMAND_ACTIVE = 0x300
} |
| enum | sas_sata_vsp_regs {
VSR_PHY_STAT = 0x00,
VSR_PHY_MODE1 = 0x01,
VSR_PHY_MODE2 = 0x02,
VSR_PHY_MODE3 = 0x03,
VSR_PHY_MODE4 = 0x04,
VSR_PHY_MODE5 = 0x05,
VSR_PHY_MODE6 = 0x06,
VSR_PHY_MODE7 = 0x07,
VSR_PHY_MODE8 = 0x08,
VSR_PHY_MODE9 = 0x09,
VSR_PHY_MODE10 = 0x0A,
VSR_PHY_MODE11 = 0x0B,
VSR_PHY_VS0 = 0x0C,
VSR_PHY_VS1 = 0x0D,
VSR_PHY_STAT = 0x00 * 4,
VSR_PHY_MODE1 = 0x01 * 4,
VSR_PHY_MODE2 = 0x02 * 4,
VSR_PHY_MODE3 = 0x03 * 4,
VSR_PHY_MODE4 = 0x04 * 4,
VSR_PHY_MODE5 = 0x05 * 4,
VSR_PHY_MODE6 = 0x06 * 4,
VSR_PHY_MODE7 = 0x07 * 4,
VSR_PHY_MODE8 = 0x08 * 4,
VSR_PHY_MODE9 = 0x09 * 4,
VSR_PHY_MODE10 = 0x0A * 4,
VSR_PHY_MODE11 = 0x0B * 4,
VSR_PHY_ACT_LED = 0x0C * 4,
VSR_PHY_FFE_CONTROL = 0x10C,
VSR_PHY_DFE_UPDATE_CRTL = 0x110,
VSR_REF_CLOCK_CRTL = 0x1A0
} |
1.8.2