mx25.h File Reference

#include <asm/irq.h>

Go to the source code of this file.

Macros
#define	MX25_AIPS1_BASE_ADDR   0x43f00000
#define	MX25_AIPS1_SIZE   SZ_1M
#define	MX25_AIPS2_BASE_ADDR   0x53f00000
#define	MX25_AIPS2_SIZE   SZ_1M
#define	MX25_AVIC_BASE_ADDR   0x68000000
#define	MX25_AVIC_SIZE   SZ_1M
#define	MX25_I2C1_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x80000)
#define	MX25_I2C3_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x84000)
#define	MX25_CAN1_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x88000)
#define	MX25_CAN2_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x8c000)
#define	MX25_I2C2_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x98000)
#define	MX25_CSPI1_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0xa4000)
#define	MX25_IOMUXC_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0xac000)
#define	MX25_CRM_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0x80000)
#define	MX25_GPT1_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0x90000)
#define	MX25_GPIO4_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0x9c000)
#define	MX25_PWM2_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xa0000)
#define	MX25_GPIO3_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xa4000)
#define	MX25_PWM3_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xa8000)
#define	MX25_PWM4_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xc8000)
#define	MX25_GPIO1_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xcc000)
#define	MX25_GPIO2_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xd0000)
#define	MX25_WDOG_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xdc000)
#define	MX25_PWM1_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xe0000)
#define	MX25_UART1_BASE_ADDR   0x43f90000
#define	MX25_UART2_BASE_ADDR   0x43f94000
#define	MX25_AUDMUX_BASE_ADDR   0x43fb0000
#define	MX25_UART3_BASE_ADDR   0x5000c000
#define	MX25_UART4_BASE_ADDR   0x50008000
#define	MX25_UART5_BASE_ADDR   0x5002c000
#define	MX25_CSPI3_BASE_ADDR   0x50004000
#define	MX25_CSPI2_BASE_ADDR   0x50010000
#define	MX25_FEC_BASE_ADDR   0x50038000
#define	MX25_SSI2_BASE_ADDR   0x50014000
#define	MX25_SSI1_BASE_ADDR   0x50034000
#define	MX25_NFC_BASE_ADDR   0xbb000000
#define	MX25_IIM_BASE_ADDR   0x53ff0000
#define	MX25_DRYICE_BASE_ADDR   0x53ffc000
#define	MX25_ESDHC1_BASE_ADDR   0x53fb4000
#define	MX25_ESDHC2_BASE_ADDR   0x53fb8000
#define	MX25_LCDC_BASE_ADDR   0x53fbc000
#define	MX25_KPP_BASE_ADDR   0x43fa8000
#define	MX25_SDMA_BASE_ADDR   0x53fd4000
#define	MX25_USB_BASE_ADDR   0x53ff4000
#define	MX25_USB_OTG_BASE_ADDR   (MX25_USB_BASE_ADDR + 0x0000)
#define	MX25_USB_HS_BASE_ADDR   (MX25_USB_BASE_ADDR + 0x0400)
#define	MX25_CSI_BASE_ADDR   0x53ff8000
#define	MX25_IO_P2V(x)   IMX_IO_P2V(x)
#define	MX25_IO_ADDRESS(x)   IOMEM(MX25_IO_P2V(x))
#define	MX25_INT_CSPI3   (NR_IRQS_LEGACY + 0)
#define	MX25_INT_I2C1   (NR_IRQS_LEGACY + 3)
#define	MX25_INT_I2C2   (NR_IRQS_LEGACY + 4)
#define	MX25_INT_UART4   (NR_IRQS_LEGACY + 5)
#define	MX25_INT_ESDHC2   (NR_IRQS_LEGACY + 8)
#define	MX25_INT_ESDHC1   (NR_IRQS_LEGACY + 9)
#define	MX25_INT_I2C3   (NR_IRQS_LEGACY + 10)
#define	MX25_INT_SSI2   (NR_IRQS_LEGACY + 11)
#define	MX25_INT_SSI1   (NR_IRQS_LEGACY + 12)
#define	MX25_INT_CSPI2   (NR_IRQS_LEGACY + 13)
#define	MX25_INT_CSPI1   (NR_IRQS_LEGACY + 14)
#define	MX25_INT_GPIO3   (NR_IRQS_LEGACY + 16)
#define	MX25_INT_CSI   (NR_IRQS_LEGACY + 17)
#define	MX25_INT_UART3   (NR_IRQS_LEGACY + 18)
#define	MX25_INT_GPIO4   (NR_IRQS_LEGACY + 23)
#define	MX25_INT_KPP   (NR_IRQS_LEGACY + 24)
#define	MX25_INT_DRYICE   (NR_IRQS_LEGACY + 25)
#define	MX25_INT_PWM1   (NR_IRQS_LEGACY + 26)
#define	MX25_INT_UART2   (NR_IRQS_LEGACY + 32)
#define	MX25_INT_NFC   (NR_IRQS_LEGACY + 33)
#define	MX25_INT_SDMA   (NR_IRQS_LEGACY + 34)
#define	MX25_INT_USB_HS   (NR_IRQS_LEGACY + 35)
#define	MX25_INT_PWM2   (NR_IRQS_LEGACY + 36)
#define	MX25_INT_USB_OTG   (NR_IRQS_LEGACY + 37)
#define	MX25_INT_LCDC   (NR_IRQS_LEGACY + 39)
#define	MX25_INT_UART5   (NR_IRQS_LEGACY + 40)
#define	MX25_INT_PWM3   (NR_IRQS_LEGACY + 41)
#define	MX25_INT_PWM4   (NR_IRQS_LEGACY + 42)
#define	MX25_INT_CAN1   (NR_IRQS_LEGACY + 43)
#define	MX25_INT_CAN2   (NR_IRQS_LEGACY + 44)
#define	MX25_INT_UART1   (NR_IRQS_LEGACY + 45)
#define	MX25_INT_GPIO2   (NR_IRQS_LEGACY + 51)
#define	MX25_INT_GPIO1   (NR_IRQS_LEGACY + 52)
#define	MX25_INT_GPT1   (NR_IRQS_LEGACY + 54)
#define	MX25_INT_FEC   (NR_IRQS_LEGACY + 57)
#define	MX25_DMA_REQ_SSI2_RX1   22
#define	MX25_DMA_REQ_SSI2_TX1   23
#define	MX25_DMA_REQ_SSI2_RX0   24
#define	MX25_DMA_REQ_SSI2_TX0   25
#define	MX25_DMA_REQ_SSI1_RX1   26
#define	MX25_DMA_REQ_SSI1_TX1   27
#define	MX25_DMA_REQ_SSI1_RX0   28
#define	MX25_DMA_REQ_SSI1_TX0   29

Functions
int	mx25_revision (void)

Macro Definition Documentation

#define MX25_AIPS1_BASE_ADDR   0x43f00000

Definition at line 4 of file mx25.h.

#define MX25_AIPS1_SIZE   SZ_1M

Definition at line 5 of file mx25.h.

#define MX25_AIPS2_BASE_ADDR   0x53f00000

Definition at line 6 of file mx25.h.

#define MX25_AIPS2_SIZE   SZ_1M

Definition at line 7 of file mx25.h.

#define MX25_AUDMUX_BASE_ADDR   0x43fb0000

Definition at line 33 of file mx25.h.

#define MX25_AVIC_BASE_ADDR   0x68000000

Definition at line 8 of file mx25.h.

#define MX25_AVIC_SIZE   SZ_1M

Definition at line 9 of file mx25.h.

#define MX25_CAN1_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x88000)

Definition at line 13 of file mx25.h.

#define MX25_CAN2_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x8c000)

Definition at line 14 of file mx25.h.

#define MX25_CRM_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0x80000)

Definition at line 19 of file mx25.h.

#define MX25_CSI_BASE_ADDR   0x53ff8000

Definition at line 59 of file mx25.h.

#define MX25_CSPI1_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0xa4000)

Definition at line 16 of file mx25.h.

#define MX25_CSPI2_BASE_ADDR   0x50010000

Definition at line 39 of file mx25.h.

#define MX25_CSPI3_BASE_ADDR   0x50004000

Definition at line 38 of file mx25.h.

#define MX25_DMA_REQ_SSI1_RX0   28

Definition at line 110 of file mx25.h.

#define MX25_DMA_REQ_SSI1_RX1   26

Definition at line 108 of file mx25.h.

#define MX25_DMA_REQ_SSI1_TX0   29

Definition at line 111 of file mx25.h.

#define MX25_DMA_REQ_SSI1_TX1   27

Definition at line 109 of file mx25.h.

#define MX25_DMA_REQ_SSI2_RX0   24

Definition at line 106 of file mx25.h.

#define MX25_DMA_REQ_SSI2_RX1   22

Definition at line 104 of file mx25.h.

#define MX25_DMA_REQ_SSI2_TX0   25

Definition at line 107 of file mx25.h.

#define MX25_DMA_REQ_SSI2_TX1   23

Definition at line 105 of file mx25.h.

#define MX25_DRYICE_BASE_ADDR   0x53ffc000

Definition at line 45 of file mx25.h.

#define MX25_ESDHC1_BASE_ADDR   0x53fb4000

Definition at line 46 of file mx25.h.

#define MX25_ESDHC2_BASE_ADDR   0x53fb8000

Definition at line 47 of file mx25.h.

#define MX25_FEC_BASE_ADDR   0x50038000

Definition at line 40 of file mx25.h.

#define MX25_GPIO1_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xcc000)

Definition at line 26 of file mx25.h.

#define MX25_GPIO2_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xd0000)

Definition at line 27 of file mx25.h.

#define MX25_GPIO3_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xa4000)

Definition at line 23 of file mx25.h.

#define MX25_GPIO4_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0x9c000)

Definition at line 21 of file mx25.h.

#define MX25_GPT1_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0x90000)

Definition at line 20 of file mx25.h.

#define MX25_I2C1_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x80000)

Definition at line 11 of file mx25.h.

#define MX25_I2C2_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x98000)

Definition at line 15 of file mx25.h.

#define MX25_I2C3_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0x84000)

Definition at line 12 of file mx25.h.

#define MX25_IIM_BASE_ADDR   0x53ff0000

Definition at line 44 of file mx25.h.

#define MX25_INT_CAN1   (NR_IRQS_LEGACY + 43)

Definition at line 96 of file mx25.h.

#define MX25_INT_CAN2   (NR_IRQS_LEGACY + 44)

Definition at line 97 of file mx25.h.

#define MX25_INT_CSI   (NR_IRQS_LEGACY + 17)

Definition at line 80 of file mx25.h.

#define MX25_INT_CSPI1   (NR_IRQS_LEGACY + 14)

Definition at line 78 of file mx25.h.

#define MX25_INT_CSPI2   (NR_IRQS_LEGACY + 13)

Definition at line 77 of file mx25.h.

#define MX25_INT_CSPI3   (NR_IRQS_LEGACY + 0)

Definition at line 68 of file mx25.h.

#define MX25_INT_DRYICE   (NR_IRQS_LEGACY + 25)

Definition at line 84 of file mx25.h.

#define MX25_INT_ESDHC1   (NR_IRQS_LEGACY + 9)

Definition at line 73 of file mx25.h.

#define MX25_INT_ESDHC2   (NR_IRQS_LEGACY + 8)

Definition at line 72 of file mx25.h.

#define MX25_INT_FEC   (NR_IRQS_LEGACY + 57)

Definition at line 102 of file mx25.h.

#define MX25_INT_GPIO1   (NR_IRQS_LEGACY + 52)

Definition at line 100 of file mx25.h.

#define MX25_INT_GPIO2   (NR_IRQS_LEGACY + 51)

Definition at line 99 of file mx25.h.

#define MX25_INT_GPIO3   (NR_IRQS_LEGACY + 16)

Definition at line 79 of file mx25.h.

#define MX25_INT_GPIO4   (NR_IRQS_LEGACY + 23)

Definition at line 82 of file mx25.h.

#define MX25_INT_GPT1   (NR_IRQS_LEGACY + 54)

Definition at line 101 of file mx25.h.

#define MX25_INT_I2C1   (NR_IRQS_LEGACY + 3)

Definition at line 69 of file mx25.h.

#define MX25_INT_I2C2   (NR_IRQS_LEGACY + 4)

Definition at line 70 of file mx25.h.

#define MX25_INT_I2C3   (NR_IRQS_LEGACY + 10)

Definition at line 74 of file mx25.h.

#define MX25_INT_KPP   (NR_IRQS_LEGACY + 24)

Definition at line 83 of file mx25.h.

#define MX25_INT_LCDC   (NR_IRQS_LEGACY + 39)

Definition at line 92 of file mx25.h.

#define MX25_INT_NFC   (NR_IRQS_LEGACY + 33)

Definition at line 87 of file mx25.h.

#define MX25_INT_PWM1   (NR_IRQS_LEGACY + 26)

Definition at line 85 of file mx25.h.

#define MX25_INT_PWM2   (NR_IRQS_LEGACY + 36)

Definition at line 90 of file mx25.h.

#define MX25_INT_PWM3   (NR_IRQS_LEGACY + 41)

Definition at line 94 of file mx25.h.

#define MX25_INT_PWM4   (NR_IRQS_LEGACY + 42)

Definition at line 95 of file mx25.h.

#define MX25_INT_SDMA   (NR_IRQS_LEGACY + 34)

Definition at line 88 of file mx25.h.

#define MX25_INT_SSI1   (NR_IRQS_LEGACY + 12)

Definition at line 76 of file mx25.h.

#define MX25_INT_SSI2   (NR_IRQS_LEGACY + 11)

Definition at line 75 of file mx25.h.

#define MX25_INT_UART1   (NR_IRQS_LEGACY + 45)

Definition at line 98 of file mx25.h.

#define MX25_INT_UART2   (NR_IRQS_LEGACY + 32)

Definition at line 86 of file mx25.h.

#define MX25_INT_UART3   (NR_IRQS_LEGACY + 18)

Definition at line 81 of file mx25.h.

#define MX25_INT_UART4   (NR_IRQS_LEGACY + 5)

Definition at line 71 of file mx25.h.

#define MX25_INT_UART5   (NR_IRQS_LEGACY + 40)

Definition at line 93 of file mx25.h.

#define MX25_INT_USB_HS   (NR_IRQS_LEGACY + 35)

Definition at line 89 of file mx25.h.

#define MX25_INT_USB_OTG   (NR_IRQS_LEGACY + 37)

Definition at line 91 of file mx25.h.

#define MX25_IO_ADDRESS

(

x

)

IOMEM(MX25_IO_P2V(x))

Definition at line 62 of file mx25.h.

#define MX25_IO_P2V

(

x

)

IMX_IO_P2V(x)

Definition at line 61 of file mx25.h.

#define MX25_IOMUXC_BASE_ADDR   (MX25_AIPS1_BASE_ADDR + 0xac000)

Definition at line 17 of file mx25.h.

#define MX25_KPP_BASE_ADDR   0x43fa8000

Definition at line 49 of file mx25.h.

#define MX25_LCDC_BASE_ADDR   0x53fbc000

Definition at line 48 of file mx25.h.

#define MX25_NFC_BASE_ADDR   0xbb000000

Definition at line 43 of file mx25.h.

#define MX25_PWM1_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xe0000)

Definition at line 29 of file mx25.h.

#define MX25_PWM2_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xa0000)

Definition at line 22 of file mx25.h.

#define MX25_PWM3_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xa8000)

Definition at line 24 of file mx25.h.

#define MX25_PWM4_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xc8000)

Definition at line 25 of file mx25.h.

#define MX25_SDMA_BASE_ADDR   0x53fd4000

Definition at line 50 of file mx25.h.

#define MX25_SSI1_BASE_ADDR   0x50034000

Definition at line 42 of file mx25.h.

#define MX25_SSI2_BASE_ADDR   0x50014000

Definition at line 41 of file mx25.h.

#define MX25_UART1_BASE_ADDR   0x43f90000

Definition at line 31 of file mx25.h.

#define MX25_UART2_BASE_ADDR   0x43f94000

Definition at line 32 of file mx25.h.

#define MX25_UART3_BASE_ADDR   0x5000c000

Definition at line 34 of file mx25.h.

#define MX25_UART4_BASE_ADDR   0x50008000

Definition at line 35 of file mx25.h.

#define MX25_UART5_BASE_ADDR   0x5002c000

Definition at line 36 of file mx25.h.

#define MX25_USB_BASE_ADDR   0x53ff4000

Definition at line 51 of file mx25.h.

#define MX25_USB_HS_BASE_ADDR   (MX25_USB_BASE_ADDR + 0x0400)

Definition at line 58 of file mx25.h.

#define MX25_USB_OTG_BASE_ADDR   (MX25_USB_BASE_ADDR + 0x0000)

Definition at line 52 of file mx25.h.

#define MX25_WDOG_BASE_ADDR   (MX25_AIPS2_BASE_ADDR + 0xdc000)

Definition at line 28 of file mx25.h.

Function Documentation

int mx25_revision

(

void

)

Definition at line 34 of file cpu-imx25.c.