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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/module.h>#include <linux/kernel.h>#include <linux/platform_device.h>#include <linux/sched.h>#include <linux/errno.h>#include <linux/string.h>#include <linux/interrupt.h>#include <linux/slab.h>#include <linux/fb.h>#include <linux/delay.h>#include <linux/init.h>#include <linux/ioport.h>#include <linux/dma-mapping.h>#include <linux/dmaengine.h>#include <linux/console.h>#include <linux/clk.h>#include <linux/mutex.h>#include <linux/platform_data/dma-imx.h>#include <mach/hardware.h>#include <mach/ipu.h>#include <linux/platform_data/video-mx3fb.h>#include <asm/io.h>#include <asm/uaccess.h>Go to the source code of this file.
Data Structures | |
| struct | ipu_di_signal_cfg |
| struct | mx3fb_data |
| struct | dma_chan_request |
| struct | mx3fb_info |
| struct | di_mapping |
Macros | |
| #define | MX3FB_NAME "mx3_sdc_fb" |
| #define | MX3FB_REG_OFFSET 0xB4 |
| #define | SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET) |
| #define | SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET) |
| #define | SDC_FG_POS (0xBC - MX3FB_REG_OFFSET) |
| #define | SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET) |
| #define | SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET) |
| #define | SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET) |
| #define | SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET) |
| #define | SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET) |
| #define | SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET) |
| #define | SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET) |
| #define | SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET) |
| #define | SDC_COM_TFT_COLOR 0x00000001UL |
| #define | SDC_COM_FG_EN 0x00000010UL |
| #define | SDC_COM_GWSEL 0x00000020UL |
| #define | SDC_COM_GLB_A 0x00000040UL |
| #define | SDC_COM_KEY_COLOR_G 0x00000080UL |
| #define | SDC_COM_BG_EN 0x00000200UL |
| #define | SDC_COM_SHARP 0x00001000UL |
| #define | SDC_V_SYNC_WIDTH_L 0x00000001UL |
| #define | DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET) |
| #define | DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET) |
| #define | DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET) |
| #define | DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET) |
| #define | DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET) |
| #define | DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET) |
| #define | DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET) |
| #define | DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET) |
| #define | DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET) |
| #define | DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET) |
| #define | DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET) |
| #define | DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET) |
| #define | DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET) |
| #define | DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET) |
| #define | DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET) |
| #define | DI_D3_VSYNC_POL_SHIFT 28 |
| #define | DI_D3_HSYNC_POL_SHIFT 27 |
| #define | DI_D3_DRDY_SHARP_POL_SHIFT 26 |
| #define | DI_D3_CLK_POL_SHIFT 25 |
| #define | DI_D3_DATA_POL_SHIFT 24 |
| #define | DI_D3_CLK_IDLE_SHIFT 26 |
| #define | DI_D3_CLK_SEL_SHIFT 25 |
| #define | DI_D3_DATAMSK_SHIFT 24 |
| #define | mx3fb_suspend NULL |
| #define | mx3fb_resume NULL |
Enumerations | |
| enum | ipu_panel { IPU_PANEL_SHARP_TFT, IPU_PANEL_TFT } |
Functions | |
| module_init (mx3fb_init) | |
| module_exit (mx3fb_exit) | |
| MODULE_AUTHOR ("Freescale Semiconductor, Inc.") | |
| MODULE_DESCRIPTION ("MX3 framebuffer driver") | |
| MODULE_ALIAS ("platform:"MX3FB_NAME) | |
| MODULE_LICENSE ("GPL v2") | |
| enum ipu_panel |
| MODULE_ALIAS | ( | "platform:" | MX3FB_NAME | ) |
| MODULE_AUTHOR | ( | "Freescale | Semiconductor, |
| Inc." | |||
| ) |
| MODULE_DESCRIPTION | ( | "MX3 framebuffer driver" | ) |
| module_exit | ( | mx3fb_exit | ) |
| module_init | ( | mx3fb_init | ) |
| MODULE_LICENSE | ( | "GPL v2" | ) |
1.8.2