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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <asm/irq.h>Go to the source code of this file.
| #define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000) |
| #define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000) |
| #define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000) |
| #define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000) |
| #define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000) |
| #define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000) |
| #define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000) |
| #define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000) |
| #define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000) |
| #define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000) |
| #define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000) |
| #define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000) |
| #define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000) |
| #define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000) |
| #define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000) |
| #define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000) |
| #define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00) |
| #define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000) |
| #define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000) |
| #define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000) |
| #define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000) |
| #define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000) |
| #define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000) |
| #define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000) |
| #define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000) |
| #define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000) |
| #define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000) |
| #define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000) |
| #define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000) |
| #define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000) |
| #define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000) |
| #define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) |
| #define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) |
| #define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000) |
| #define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000) |
| #define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000) |
| #define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) |
| #define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000) |
| #define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000) |
| #define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000) |
| #define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000) |
| #define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000) |
| #define MX53_INT_ASRC (NR_IRQS_LEGACY + 66) |
| #define MX53_INT_ATA (NR_IRQS_LEGACY + 70) |
| #define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82) |
| #define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83) |
| #define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71) |
| #define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72) |
| #define MX53_INT_CSPI (NR_IRQS_LEGACY + 38) |
| #define MX53_INT_CSU (NR_IRQS_LEGACY + 27) |
| #define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79) |
| #define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80) |
| #define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89) |
| #define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98) |
| #define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78) |
| #define MX53_INT_DAP (NR_IRQS_LEGACY + 5) |
| #define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36) |
| #define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37) |
| #define MX53_INT_EMI (NR_IRQS_LEGACY + 15) |
| #define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97) |
| #define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101) |
| #define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40) |
| #define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41) |
| #define MX53_INT_ESAI (NR_IRQS_LEGACY + 81) |
| #define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1) |
| #define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2) |
| #define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3) |
| #define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4) |
| #define MX53_INT_FEC (NR_IRQS_LEGACY + 87) |
| #define MX53_INT_FIRI (NR_IRQS_LEGACY + 93) |
| #define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73) |
| #define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74) |
| #define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51) |
| #define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49) |
| #define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48) |
| #define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47) |
| #define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46) |
| #define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45) |
| #define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44) |
| #define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43) |
| #define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42) |
| #define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50) |
| #define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53) |
| #define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52) |
| #define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55) |
| #define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54) |
| #define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57) |
| #define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56) |
| #define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104) |
| #define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103) |
| #define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106) |
| #define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105) |
| #define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108) |
| #define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107) |
| #define MX53_INT_GPT (NR_IRQS_LEGACY + 39) |
| #define MX53_INT_GPU (NR_IRQS_LEGACY + 12) |
| #define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85) |
| #define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84) |
| #define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102) |
| #define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62) |
| #define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63) |
| #define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64) |
| #define MX53_INT_IIM (NR_IRQS_LEGACY + 69) |
| #define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7) |
| #define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10) |
| #define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11) |
| #define MX53_INT_KPP (NR_IRQS_LEGACY + 60) |
| #define MX53_INT_MLB (NR_IRQS_LEGACY + 65) |
| #define MX53_INT_NFC (NR_IRQS_LEGACY + 8) |
| #define MX53_INT_NM (NR_IRQS_LEGACY + 76) |
| #define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88) |
| #define MX53_INT_PMU (NR_IRQS_LEGACY + 77) |
| #define MX53_INT_PTP (NR_IRQS_LEGACY + 35) |
| #define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61) |
| #define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94) |
| #define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0) |
| #define MX53_INT_RTC (NR_IRQS_LEGACY + 34) |
| #define MX53_INT_RTIC (NR_IRQS_LEGACY + 26) |
| #define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19) |
| #define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20) |
| #define MX53_INT_SATA (NR_IRQS_LEGACY + 28) |
| #define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23) |
| #define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21) |
| #define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22) |
| #define MX53_INT_SDMA (NR_IRQS_LEGACY + 6) |
| #define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68) |
| #define MX53_INT_SJC (NR_IRQS_LEGACY + 90) |
| #define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95) |
| #define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99) |
| #define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67) |
| #define MX53_INT_SRC (NR_IRQS_LEGACY + 75) |
| #define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24) |
| #define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25) |
| #define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29) |
| #define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30) |
| #define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96) |
| #define MX53_INT_TVE (NR_IRQS_LEGACY + 92) |
| #define MX53_INT_UART1 (NR_IRQS_LEGACY + 31) |
| #define MX53_INT_UART2 (NR_IRQS_LEGACY + 32) |
| #define MX53_INT_UART3 (NR_IRQS_LEGACY + 33) |
| #define MX53_INT_UART4 (NR_IRQS_LEGACY + 13) |
| #define MX53_INT_UART5 (NR_IRQS_LEGACY + 86) |
| #define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14) |
| #define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16) |
| #define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17) |
| #define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18) |
| #define MX53_INT_VPU (NR_IRQS_LEGACY + 9) |
| #define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100) |
| #define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58) |
| #define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59) |
| #define MX53_IO_P2V | ( | x | ) | IMX_IO_P2V(x) |
| #define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000) |
| #define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */ |
| #define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) |
| #define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000) |
| #define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000) |
| #define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000) |
| #define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */ |
| #define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000) |
| #define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000) |
| #define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000) |
| #define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000) |
| #define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000) |
| #define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000) |
| #define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000) |
| #define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000) |
| #define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000) |
| #define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000) |
| #define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000) |
| #define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000) |
| #define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000) |
| #define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000) |
| #define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000) |
| #define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000) |
| #define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000) |
| #define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000) |
| #define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000) |
| #define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000) |
| #define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) |
| #define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000) |
| #define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000) |
| #define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000) |
| #define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000) |
| #define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000) |
| #define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000) |
| #define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000) |
| #define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000) |
| #define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000) |
| #define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000) |
| #define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000) |
| #define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) |
| #define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) |
| #define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000) |
1.8.2