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n2_core.h
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1 #ifndef _N2_CORE_H
2 #define _N2_CORE_H
3 
4 #ifndef __ASSEMBLY__
5 
6 struct ino_blob {
7  u64 intr;
8  u64 ino;
9 };
10 
11 struct spu_mdesc_info {
12  u64 cfg_handle;
13  struct ino_blob *ino_table;
14  int num_intrs;
15 };
16 
17 struct n2_crypto {
18  struct spu_mdesc_info cwq_info;
19  struct list_head cwq_list;
20 };
21 
22 struct n2_mau {
23  struct spu_mdesc_info mau_info;
24  struct list_head mau_list;
25 };
26 
27 #define CWQ_ENTRY_SIZE 64
28 #define CWQ_NUM_ENTRIES 64
29 
30 #define MAU_ENTRY_SIZE 64
31 #define MAU_NUM_ENTRIES 64
32 
33 struct cwq_initial_entry {
34  u64 control;
35  u64 src_addr;
36  u64 auth_key_addr;
37  u64 auth_iv_addr;
38  u64 final_auth_state_addr;
39  u64 enc_key_addr;
40  u64 enc_iv_addr;
41  u64 dest_addr;
42 };
43 
44 struct cwq_ext_entry {
45  u64 len;
46  u64 src_addr;
47  u64 resv1;
48  u64 resv2;
49  u64 resv3;
50  u64 resv4;
51  u64 resv5;
52  u64 resv6;
53 };
54 
55 struct cwq_final_entry {
56  u64 control;
57  u64 src_addr;
58  u64 resv1;
59  u64 resv2;
60  u64 resv3;
61  u64 resv4;
62  u64 resv5;
63  u64 resv6;
64 };
65 
66 #define CONTROL_LEN 0x000000000000ffffULL
67 #define CONTROL_LEN_SHIFT 0
68 #define CONTROL_HMAC_KEY_LEN 0x0000000000ff0000ULL
69 #define CONTROL_HMAC_KEY_LEN_SHIFT 16
70 #define CONTROL_ENC_TYPE 0x00000000ff000000ULL
71 #define CONTROL_ENC_TYPE_SHIFT 24
72 #define ENC_TYPE_ALG_RC4_STREAM 0x00ULL
73 #define ENC_TYPE_ALG_RC4_NOSTREAM 0x04ULL
74 #define ENC_TYPE_ALG_DES 0x08ULL
75 #define ENC_TYPE_ALG_3DES 0x0cULL
76 #define ENC_TYPE_ALG_AES128 0x10ULL
77 #define ENC_TYPE_ALG_AES192 0x14ULL
78 #define ENC_TYPE_ALG_AES256 0x18ULL
79 #define ENC_TYPE_ALG_RESERVED 0x1cULL
80 #define ENC_TYPE_ALG_MASK 0x1cULL
81 #define ENC_TYPE_CHAINING_ECB 0x00ULL
82 #define ENC_TYPE_CHAINING_CBC 0x01ULL
83 #define ENC_TYPE_CHAINING_CFB 0x02ULL
84 #define ENC_TYPE_CHAINING_COUNTER 0x03ULL
85 #define ENC_TYPE_CHAINING_MASK 0x03ULL
86 #define CONTROL_AUTH_TYPE 0x0000001f00000000ULL
87 #define CONTROL_AUTH_TYPE_SHIFT 32
88 #define AUTH_TYPE_RESERVED 0x00ULL
89 #define AUTH_TYPE_MD5 0x01ULL
90 #define AUTH_TYPE_SHA1 0x02ULL
91 #define AUTH_TYPE_SHA256 0x03ULL
92 #define AUTH_TYPE_CRC32 0x04ULL
93 #define AUTH_TYPE_HMAC_MD5 0x05ULL
94 #define AUTH_TYPE_HMAC_SHA1 0x06ULL
95 #define AUTH_TYPE_HMAC_SHA256 0x07ULL
96 #define AUTH_TYPE_TCP_CHECKSUM 0x08ULL
97 #define AUTH_TYPE_SSL_HMAC_MD5 0x09ULL
98 #define AUTH_TYPE_SSL_HMAC_SHA1 0x0aULL
99 #define AUTH_TYPE_SSL_HMAC_SHA256 0x0bULL
100 #define CONTROL_STRAND 0x000000e000000000ULL
101 #define CONTROL_STRAND_SHIFT 37
102 #define CONTROL_HASH_LEN 0x0000ff0000000000ULL
103 #define CONTROL_HASH_LEN_SHIFT 40
104 #define CONTROL_INTERRUPT 0x0001000000000000ULL
105 #define CONTROL_STORE_FINAL_AUTH_STATE 0x0002000000000000ULL
106 #define CONTROL_RESERVED 0x001c000000000000ULL
107 #define CONTROL_HV_DONE 0x0004000000000000ULL
108 #define CONTROL_HV_PROTOCOL_ERROR 0x0008000000000000ULL
109 #define CONTROL_HV_HARDWARE_ERROR 0x0010000000000000ULL
110 #define CONTROL_END_OF_BLOCK 0x0020000000000000ULL
111 #define CONTROL_START_OF_BLOCK 0x0040000000000000ULL
112 #define CONTROL_ENCRYPT 0x0080000000000000ULL
113 #define CONTROL_OPCODE 0xff00000000000000ULL
114 #define CONTROL_OPCODE_SHIFT 56
115 #define OPCODE_INPLACE_BIT 0x80ULL
116 #define OPCODE_SSL_KEYBLOCK 0x10ULL
117 #define OPCODE_COPY 0x20ULL
118 #define OPCODE_ENCRYPT 0x40ULL
119 #define OPCODE_AUTH_MAC 0x41ULL
120 
121 #endif /* !(__ASSEMBLY__) */
122 
123 /* NCS v2.0 hypervisor interfaces */
124 #define HV_NCS_QTYPE_MAU 0x01
125 #define HV_NCS_QTYPE_CWQ 0x02
126 
127 /* ncs_qconf()
128  * TRAP: HV_FAST_TRAP
129  * FUNCTION: HV_FAST_NCS_QCONF
130  * ARG0: Queue type (HV_NCS_QTYPE_{MAU,CWQ})
131  * ARG1: Real address of queue, or handle for unconfigure
132  * ARG2: Number of entries in queue, zero for unconfigure
133  * RET0: status
134  * RET1: queue handle
135  *
136  * Configure a queue in the stream processing unit.
137  *
138  * The real address given as the base must be 64-byte
139  * aligned.
140  *
141  * The queue size can range from a minimum of 2 to a maximum
142  * of 64. The queue size must be a power of two.
143  *
144  * To unconfigure a queue, specify a length of zero and place
145  * the queue handle into ARG1.
146  *
147  * On configure success the hypervisor will set the FIRST, HEAD,
148  * and TAIL registers to the address of the first entry in the
149  * queue. The LAST register will be set to point to the last
150  * entry in the queue.
151  */
152 #define HV_FAST_NCS_QCONF 0x111
153 
154 /* ncs_qinfo()
155  * TRAP: HV_FAST_TRAP
156  * FUNCTION: HV_FAST_NCS_QINFO
157  * ARG0: Queue handle
158  * RET0: status
159  * RET1: Queue type (HV_NCS_QTYPE_{MAU,CWQ})
160  * RET2: Queue base address
161  * RET3: Number of entries
162  */
163 #define HV_FAST_NCS_QINFO 0x112
164 
165 /* ncs_gethead()
166  * TRAP: HV_FAST_TRAP
167  * FUNCTION: HV_FAST_NCS_GETHEAD
168  * ARG0: Queue handle
169  * RET0: status
170  * RET1: queue head offset
171  */
172 #define HV_FAST_NCS_GETHEAD 0x113
173 
174 /* ncs_gettail()
175  * TRAP: HV_FAST_TRAP
176  * FUNCTION: HV_FAST_NCS_GETTAIL
177  * ARG0: Queue handle
178  * RET0: status
179  * RET1: queue tail offset
180  */
181 #define HV_FAST_NCS_GETTAIL 0x114
182 
183 /* ncs_settail()
184  * TRAP: HV_FAST_TRAP
185  * FUNCTION: HV_FAST_NCS_SETTAIL
186  * ARG0: Queue handle
187  * ARG1: New tail offset
188  * RET0: status
189  */
190 #define HV_FAST_NCS_SETTAIL 0x115
191 
192 /* ncs_qhandle_to_devino()
193  * TRAP: HV_FAST_TRAP
194  * FUNCTION: HV_FAST_NCS_QHANDLE_TO_DEVINO
195  * ARG0: Queue handle
196  * RET0: status
197  * RET1: devino
198  */
199 #define HV_FAST_NCS_QHANDLE_TO_DEVINO 0x116
200 
201 /* ncs_sethead_marker()
202  * TRAP: HV_FAST_TRAP
203  * FUNCTION: HV_FAST_NCS_SETHEAD_MARKER
204  * ARG0: Queue handle
205  * ARG1: New head offset
206  * RET0: status
207  */
208 #define HV_FAST_NCS_SETHEAD_MARKER 0x117
209 
210 #ifndef __ASSEMBLY__
211 extern unsigned long sun4v_ncs_qconf(unsigned long queue_type,
212  unsigned long queue_ra,
213  unsigned long num_entries,
214  unsigned long *qhandle);
215 extern unsigned long sun4v_ncs_qinfo(unsigned long qhandle,
216  unsigned long *queue_type,
217  unsigned long *queue_ra,
218  unsigned long *num_entries);
219 extern unsigned long sun4v_ncs_gethead(unsigned long qhandle,
220  unsigned long *head);
221 extern unsigned long sun4v_ncs_gettail(unsigned long qhandle,
222  unsigned long *tail);
223 extern unsigned long sun4v_ncs_settail(unsigned long qhandle,
224  unsigned long tail);
225 extern unsigned long sun4v_ncs_qhandle_to_devino(unsigned long qhandle,
226  unsigned long *devino);
227 extern unsigned long sun4v_ncs_sethead_marker(unsigned long qhandle,
228  unsigned long head);
229 #endif /* !(__ASSEMBLY__) */
230 
231 #endif /* _N2_CORE_H */
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