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Macros
nand-regs.h File Reference

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Macros

#define FCOMMAND_0   __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */
 
#define FCOMMAND_1   __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */
 
#define FCOMMAND_2   __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */
 
#define FCOMMAND_3   __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */
 
#define FCOMMAND2_0   __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */
 
#define FCOMMAND2_1   __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */
 
#define FCOMMAND2_2   __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */
 
#define FCOMMAND2_3   __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */
 
#define FCOMMAND_FIEN   0x80 /* nand flash I/F enable */
 
#define FCOMMAND_BW_8BIT   0x00 /* 8bit bus width */
 
#define FCOMMAND_BW_16BIT   0x40 /* 16bit bus width */
 
#define FCOMMAND_BLOCKSZ_SMALL   0x00 /* small block */
 
#define FCOMMAND_BLOCKSZ_LARGE   0x20 /* large block */
 
#define FCOMMAND_DMASTART   0x10 /* dma start */
 
#define FCOMMAND_RYBY   0x08 /* ready/busy flag */
 
#define FCOMMAND_RYBYINTMSK   0x04 /* mask ready/busy interrupt */
 
#define FCOMMAND_XFWP   0x02 /* write protect enable */
 
#define FCOMMAND_XFCE   0x01 /* flash device disable */
 
#define FCOMMAND_SEQKILL   0x10 /* stop seq-read */
 
#define FCOMMAND_ANUM   0x07 /* address cycle */
 
#define FCOMMAND_ANUM_NONE   0x00 /* address cycle none */
 
#define FCOMMAND_ANUM_1CYC   0x01 /* address cycle 1cycle */
 
#define FCOMMAND_ANUM_2CYC   0x02 /* address cycle 2cycle */
 
#define FCOMMAND_ANUM_3CYC   0x03 /* address cycle 3cycle */
 
#define FCOMMAND_ANUM_4CYC   0x04 /* address cycle 4cycle */
 
#define FCOMMAND_ANUM_5CYC   0x05 /* address cycle 5cycle */
 
#define FCOMMAND_FCMD_READ0   0x00 /* read1 command */
 
#define FCOMMAND_FCMD_SEQIN   0x80 /* page program 1st command */
 
#define FCOMMAND_FCMD_PAGEPROG   0x10 /* page program 2nd command */
 
#define FCOMMAND_FCMD_RESET   0xff /* reset command */
 
#define FCOMMAND_FCMD_ERASE1   0x60 /* erase 1st command */
 
#define FCOMMAND_FCMD_ERASE2   0xd0 /* erase 2nd command */
 
#define FCOMMAND_FCMD_STATUS   0x70 /* read status command */
 
#define FCOMMAND_FCMD_READID   0x90 /* read id command */
 
#define FCOMMAND_FCMD_READOOB   0x50 /* read3 command */
 
#define FADD   __SYSREG(0xd8f00004, u32)
 
#define FADD2   __SYSREG(0xd8f00008, u32)
 
#define FJUDGE   __SYSREG(0xd8f0000c, u32)
 
#define FJUDGE_NOERR   0x0 /* no error */
 
#define FJUDGE_1BITERR   0x1 /* 1bit error in data area */
 
#define FJUDGE_PARITYERR   0x2 /* parity error */
 
#define FJUDGE_UNCORRECTABLE   0x3 /* uncorrectable error */
 
#define FJUDGE_ERRJDG_MSK   0x3 /* mask of judgement result */
 
#define FECC11   __SYSREG(0xd8f00010, u32)
 
#define FECC12   __SYSREG(0xd8f00014, u32)
 
#define FECC21   __SYSREG(0xd8f00018, u32)
 
#define FECC22   __SYSREG(0xd8f0001c, u32)
 
#define FECC31   __SYSREG(0xd8f00020, u32)
 
#define FECC32   __SYSREG(0xd8f00024, u32)
 
#define FECC41   __SYSREG(0xd8f00028, u32)
 
#define FECC42   __SYSREG(0xd8f0002c, u32)
 
#define FDATA   __SYSREG(0xd8f00030, u32)
 
#define FPWS   __SYSREG(0xd8f00100, u32)
 
#define FPWS_PWS1W_2CLK   0x00000000 /* write pulse width 1clock */
 
#define FPWS_PWS1W_3CLK   0x01000000 /* write pulse width 2clock */
 
#define FPWS_PWS1W_4CLK   0x02000000 /* write pulse width 4clock */
 
#define FPWS_PWS1W_5CLK   0x03000000 /* write pulse width 5clock */
 
#define FPWS_PWS1W_6CLK   0x04000000 /* write pulse width 6clock */
 
#define FPWS_PWS1W_7CLK   0x05000000 /* write pulse width 7clock */
 
#define FPWS_PWS1W_8CLK   0x06000000 /* write pulse width 8clock */
 
#define FPWS_PWS1R_3CLK   0x00010000 /* read pulse width 3clock */
 
#define FPWS_PWS1R_4CLK   0x00020000 /* read pulse width 4clock */
 
#define FPWS_PWS1R_5CLK   0x00030000 /* read pulse width 5clock */
 
#define FPWS_PWS1R_6CLK   0x00040000 /* read pulse width 6clock */
 
#define FPWS_PWS1R_7CLK   0x00050000 /* read pulse width 7clock */
 
#define FPWS_PWS1R_8CLK   0x00060000 /* read pulse width 8clock */
 
#define FPWS_PWS2W_2CLK   0x00000100 /* write pulse interval 2clock */
 
#define FPWS_PWS2W_3CLK   0x00000200 /* write pulse interval 3clock */
 
#define FPWS_PWS2W_4CLK   0x00000300 /* write pulse interval 4clock */
 
#define FPWS_PWS2W_5CLK   0x00000400 /* write pulse interval 5clock */
 
#define FPWS_PWS2W_6CLK   0x00000500 /* write pulse interval 6clock */
 
#define FPWS_PWS2R_2CLK   0x00000001 /* read pulse interval 2clock */
 
#define FPWS_PWS2R_3CLK   0x00000002 /* read pulse interval 3clock */
 
#define FPWS_PWS2R_4CLK   0x00000003 /* read pulse interval 4clock */
 
#define FPWS_PWS2R_5CLK   0x00000004 /* read pulse interval 5clock */
 
#define FPWS_PWS2R_6CLK   0x00000005 /* read pulse interval 6clock */
 
#define FCOMMAND2   __SYSREG(0xd8f00110, u32)
 
#define FNUM   __SYSREG(0xd8f00114, u32)
 
#define FSDATA_ADDR   0xd8f00400
 
#define FSDATA   __SYSREG(FSDATA_ADDR, u32)
 

Macro Definition Documentation

#define FADD   __SYSREG(0xd8f00004, u32)

Definition at line 59 of file nand-regs.h.

#define FADD2   __SYSREG(0xd8f00008, u32)

Definition at line 61 of file nand-regs.h.

#define FCOMMAND2   __SYSREG(0xd8f00110, u32)

Definition at line 113 of file nand-regs.h.

#define FCOMMAND2_0   __SYSREG(0xd8f00110, u8) /* fcommand2[24:31] */

Definition at line 26 of file nand-regs.h.

#define FCOMMAND2_1   __SYSREG(0xd8f00111, u8) /* fcommand2[16:23] */

Definition at line 27 of file nand-regs.h.

#define FCOMMAND2_2   __SYSREG(0xd8f00112, u8) /* fcommand2[8:15] */

Definition at line 28 of file nand-regs.h.

#define FCOMMAND2_3   __SYSREG(0xd8f00113, u8) /* fcommand2[0:7] */

Definition at line 29 of file nand-regs.h.

#define FCOMMAND_0   __SYSREG(0xd8f00000, u8) /* fcommand[24:31] */

Definition at line 20 of file nand-regs.h.

#define FCOMMAND_1   __SYSREG(0xd8f00001, u8) /* fcommand[16:23] */

Definition at line 21 of file nand-regs.h.

#define FCOMMAND_2   __SYSREG(0xd8f00002, u8) /* fcommand[8:15] */

Definition at line 22 of file nand-regs.h.

#define FCOMMAND_3   __SYSREG(0xd8f00003, u8) /* fcommand[0:7] */

Definition at line 23 of file nand-regs.h.

#define FCOMMAND_ANUM   0x07 /* address cycle */

Definition at line 42 of file nand-regs.h.

#define FCOMMAND_ANUM_1CYC   0x01 /* address cycle 1cycle */

Definition at line 44 of file nand-regs.h.

#define FCOMMAND_ANUM_2CYC   0x02 /* address cycle 2cycle */

Definition at line 45 of file nand-regs.h.

#define FCOMMAND_ANUM_3CYC   0x03 /* address cycle 3cycle */

Definition at line 46 of file nand-regs.h.

#define FCOMMAND_ANUM_4CYC   0x04 /* address cycle 4cycle */

Definition at line 47 of file nand-regs.h.

#define FCOMMAND_ANUM_5CYC   0x05 /* address cycle 5cycle */

Definition at line 48 of file nand-regs.h.

#define FCOMMAND_ANUM_NONE   0x00 /* address cycle none */

Definition at line 43 of file nand-regs.h.

#define FCOMMAND_BLOCKSZ_LARGE   0x20 /* large block */

Definition at line 35 of file nand-regs.h.

#define FCOMMAND_BLOCKSZ_SMALL   0x00 /* small block */

Definition at line 34 of file nand-regs.h.

#define FCOMMAND_BW_16BIT   0x40 /* 16bit bus width */

Definition at line 33 of file nand-regs.h.

#define FCOMMAND_BW_8BIT   0x00 /* 8bit bus width */

Definition at line 32 of file nand-regs.h.

#define FCOMMAND_DMASTART   0x10 /* dma start */

Definition at line 36 of file nand-regs.h.

#define FCOMMAND_FCMD_ERASE1   0x60 /* erase 1st command */

Definition at line 53 of file nand-regs.h.

#define FCOMMAND_FCMD_ERASE2   0xd0 /* erase 2nd command */

Definition at line 54 of file nand-regs.h.

#define FCOMMAND_FCMD_PAGEPROG   0x10 /* page program 2nd command */

Definition at line 51 of file nand-regs.h.

#define FCOMMAND_FCMD_READ0   0x00 /* read1 command */

Definition at line 49 of file nand-regs.h.

#define FCOMMAND_FCMD_READID   0x90 /* read id command */

Definition at line 56 of file nand-regs.h.

#define FCOMMAND_FCMD_READOOB   0x50 /* read3 command */

Definition at line 57 of file nand-regs.h.

#define FCOMMAND_FCMD_RESET   0xff /* reset command */

Definition at line 52 of file nand-regs.h.

#define FCOMMAND_FCMD_SEQIN   0x80 /* page program 1st command */

Definition at line 50 of file nand-regs.h.

#define FCOMMAND_FCMD_STATUS   0x70 /* read status command */

Definition at line 55 of file nand-regs.h.

#define FCOMMAND_FIEN   0x80 /* nand flash I/F enable */

Definition at line 31 of file nand-regs.h.

#define FCOMMAND_RYBY   0x08 /* ready/busy flag */

Definition at line 37 of file nand-regs.h.

#define FCOMMAND_RYBYINTMSK   0x04 /* mask ready/busy interrupt */

Definition at line 38 of file nand-regs.h.

#define FCOMMAND_SEQKILL   0x10 /* stop seq-read */

Definition at line 41 of file nand-regs.h.

#define FCOMMAND_XFCE   0x01 /* flash device disable */

Definition at line 40 of file nand-regs.h.

#define FCOMMAND_XFWP   0x02 /* write protect enable */

Definition at line 39 of file nand-regs.h.

#define FDATA   __SYSREG(0xd8f00030, u32)

Definition at line 86 of file nand-regs.h.

#define FECC11   __SYSREG(0xd8f00010, u32)

Definition at line 70 of file nand-regs.h.

#define FECC12   __SYSREG(0xd8f00014, u32)

Definition at line 72 of file nand-regs.h.

#define FECC21   __SYSREG(0xd8f00018, u32)

Definition at line 74 of file nand-regs.h.

#define FECC22   __SYSREG(0xd8f0001c, u32)

Definition at line 76 of file nand-regs.h.

#define FECC31   __SYSREG(0xd8f00020, u32)

Definition at line 78 of file nand-regs.h.

#define FECC32   __SYSREG(0xd8f00024, u32)

Definition at line 80 of file nand-regs.h.

#define FECC41   __SYSREG(0xd8f00028, u32)

Definition at line 82 of file nand-regs.h.

#define FECC42   __SYSREG(0xd8f0002c, u32)

Definition at line 84 of file nand-regs.h.

#define FJUDGE   __SYSREG(0xd8f0000c, u32)

Definition at line 63 of file nand-regs.h.

#define FJUDGE_1BITERR   0x1 /* 1bit error in data area */

Definition at line 65 of file nand-regs.h.

#define FJUDGE_ERRJDG_MSK   0x3 /* mask of judgement result */

Definition at line 68 of file nand-regs.h.

#define FJUDGE_NOERR   0x0 /* no error */

Definition at line 64 of file nand-regs.h.

#define FJUDGE_PARITYERR   0x2 /* parity error */

Definition at line 66 of file nand-regs.h.

#define FJUDGE_UNCORRECTABLE   0x3 /* uncorrectable error */

Definition at line 67 of file nand-regs.h.

#define FNUM   __SYSREG(0xd8f00114, u32)

Definition at line 115 of file nand-regs.h.

#define FPWS   __SYSREG(0xd8f00100, u32)

Definition at line 88 of file nand-regs.h.

#define FPWS_PWS1R_3CLK   0x00010000 /* read pulse width 3clock */

Definition at line 96 of file nand-regs.h.

#define FPWS_PWS1R_4CLK   0x00020000 /* read pulse width 4clock */

Definition at line 97 of file nand-regs.h.

#define FPWS_PWS1R_5CLK   0x00030000 /* read pulse width 5clock */

Definition at line 98 of file nand-regs.h.

#define FPWS_PWS1R_6CLK   0x00040000 /* read pulse width 6clock */

Definition at line 99 of file nand-regs.h.

#define FPWS_PWS1R_7CLK   0x00050000 /* read pulse width 7clock */

Definition at line 100 of file nand-regs.h.

#define FPWS_PWS1R_8CLK   0x00060000 /* read pulse width 8clock */

Definition at line 101 of file nand-regs.h.

#define FPWS_PWS1W_2CLK   0x00000000 /* write pulse width 1clock */

Definition at line 89 of file nand-regs.h.

#define FPWS_PWS1W_3CLK   0x01000000 /* write pulse width 2clock */

Definition at line 90 of file nand-regs.h.

#define FPWS_PWS1W_4CLK   0x02000000 /* write pulse width 4clock */

Definition at line 91 of file nand-regs.h.

#define FPWS_PWS1W_5CLK   0x03000000 /* write pulse width 5clock */

Definition at line 92 of file nand-regs.h.

#define FPWS_PWS1W_6CLK   0x04000000 /* write pulse width 6clock */

Definition at line 93 of file nand-regs.h.

#define FPWS_PWS1W_7CLK   0x05000000 /* write pulse width 7clock */

Definition at line 94 of file nand-regs.h.

#define FPWS_PWS1W_8CLK   0x06000000 /* write pulse width 8clock */

Definition at line 95 of file nand-regs.h.

#define FPWS_PWS2R_2CLK   0x00000001 /* read pulse interval 2clock */

Definition at line 107 of file nand-regs.h.

#define FPWS_PWS2R_3CLK   0x00000002 /* read pulse interval 3clock */

Definition at line 108 of file nand-regs.h.

#define FPWS_PWS2R_4CLK   0x00000003 /* read pulse interval 4clock */

Definition at line 109 of file nand-regs.h.

#define FPWS_PWS2R_5CLK   0x00000004 /* read pulse interval 5clock */

Definition at line 110 of file nand-regs.h.

#define FPWS_PWS2R_6CLK   0x00000005 /* read pulse interval 6clock */

Definition at line 111 of file nand-regs.h.

#define FPWS_PWS2W_2CLK   0x00000100 /* write pulse interval 2clock */

Definition at line 102 of file nand-regs.h.

#define FPWS_PWS2W_3CLK   0x00000200 /* write pulse interval 3clock */

Definition at line 103 of file nand-regs.h.

#define FPWS_PWS2W_4CLK   0x00000300 /* write pulse interval 4clock */

Definition at line 104 of file nand-regs.h.

#define FPWS_PWS2W_5CLK   0x00000400 /* write pulse interval 5clock */

Definition at line 105 of file nand-regs.h.

#define FPWS_PWS2W_6CLK   0x00000500 /* write pulse interval 6clock */

Definition at line 106 of file nand-regs.h.

#define FSDATA   __SYSREG(FSDATA_ADDR, u32)

Definition at line 118 of file nand-regs.h.

#define FSDATA_ADDR   0xd8f00400

Definition at line 116 of file nand-regs.h.