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bfi_reg.h File Reference

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Macros

#define HOSTFN0_INT_STATUS   0x00014000 /* cb/ct */
 
#define HOSTFN1_INT_STATUS   0x00014100 /* cb/ct */
 
#define HOSTFN2_INT_STATUS   0x00014300 /* ct */
 
#define HOSTFN3_INT_STATUS   0x00014400 /* ct */
 
#define HOSTFN0_INT_MSK   0x00014004 /* cb/ct */
 
#define HOSTFN1_INT_MSK   0x00014104 /* cb/ct */
 
#define HOSTFN2_INT_MSK   0x00014304 /* ct */
 
#define HOSTFN3_INT_MSK   0x00014404 /* ct */
 
#define HOST_PAGE_NUM_FN0   0x00014008 /* cb/ct */
 
#define HOST_PAGE_NUM_FN1   0x00014108 /* cb/ct */
 
#define HOST_PAGE_NUM_FN2   0x00014308 /* ct */
 
#define HOST_PAGE_NUM_FN3   0x00014408 /* ct */
 
#define APP_PLL_LCLK_CTL_REG   0x00014204 /* cb/ct */
 
#define __P_LCLK_PLL_LOCK   0x80000000
 
#define __APP_PLL_LCLK_SRAM_USE_100MHZ   0x00100000
 
#define __APP_PLL_LCLK_RESET_TIMER_MK   0x000e0000
 
#define __APP_PLL_LCLK_RESET_TIMER_SH   17
 
#define __APP_PLL_LCLK_RESET_TIMER(_v)   ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)
 
#define __APP_PLL_LCLK_LOGIC_SOFT_RESET   0x00010000
 
#define __APP_PLL_LCLK_CNTLMT0_1_MK   0x0000c000
 
#define __APP_PLL_LCLK_CNTLMT0_1_SH   14
 
#define __APP_PLL_LCLK_CNTLMT0_1(_v)   ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)
 
#define __APP_PLL_LCLK_JITLMT0_1_MK   0x00003000
 
#define __APP_PLL_LCLK_JITLMT0_1_SH   12
 
#define __APP_PLL_LCLK_JITLMT0_1(_v)   ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)
 
#define __APP_PLL_LCLK_HREF   0x00000800
 
#define __APP_PLL_LCLK_HDIV   0x00000400
 
#define __APP_PLL_LCLK_P0_1_MK   0x00000300
 
#define __APP_PLL_LCLK_P0_1_SH   8
 
#define __APP_PLL_LCLK_P0_1(_v)   ((_v) << __APP_PLL_LCLK_P0_1_SH)
 
#define __APP_PLL_LCLK_Z0_2_MK   0x000000e0
 
#define __APP_PLL_LCLK_Z0_2_SH   5
 
#define __APP_PLL_LCLK_Z0_2(_v)   ((_v) << __APP_PLL_LCLK_Z0_2_SH)
 
#define __APP_PLL_LCLK_RSEL200500   0x00000010
 
#define __APP_PLL_LCLK_ENARST   0x00000008
 
#define __APP_PLL_LCLK_BYPASS   0x00000004
 
#define __APP_PLL_LCLK_LRESETN   0x00000002
 
#define __APP_PLL_LCLK_ENABLE   0x00000001
 
#define APP_PLL_SCLK_CTL_REG   0x00014208 /* cb/ct */
 
#define __P_SCLK_PLL_LOCK   0x80000000
 
#define __APP_PLL_SCLK_RESET_TIMER_MK   0x000e0000
 
#define __APP_PLL_SCLK_RESET_TIMER_SH   17
 
#define __APP_PLL_SCLK_RESET_TIMER(_v)   ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)
 
#define __APP_PLL_SCLK_LOGIC_SOFT_RESET   0x00010000
 
#define __APP_PLL_SCLK_CNTLMT0_1_MK   0x0000c000
 
#define __APP_PLL_SCLK_CNTLMT0_1_SH   14
 
#define __APP_PLL_SCLK_CNTLMT0_1(_v)   ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)
 
#define __APP_PLL_SCLK_JITLMT0_1_MK   0x00003000
 
#define __APP_PLL_SCLK_JITLMT0_1_SH   12
 
#define __APP_PLL_SCLK_JITLMT0_1(_v)   ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)
 
#define __APP_PLL_SCLK_HREF   0x00000800
 
#define __APP_PLL_SCLK_HDIV   0x00000400
 
#define __APP_PLL_SCLK_P0_1_MK   0x00000300
 
#define __APP_PLL_SCLK_P0_1_SH   8
 
#define __APP_PLL_SCLK_P0_1(_v)   ((_v) << __APP_PLL_SCLK_P0_1_SH)
 
#define __APP_PLL_SCLK_Z0_2_MK   0x000000e0
 
#define __APP_PLL_SCLK_Z0_2_SH   5
 
#define __APP_PLL_SCLK_Z0_2(_v)   ((_v) << __APP_PLL_SCLK_Z0_2_SH)
 
#define __APP_PLL_SCLK_RSEL200500   0x00000010
 
#define __APP_PLL_SCLK_ENARST   0x00000008
 
#define __APP_PLL_SCLK_BYPASS   0x00000004
 
#define __APP_PLL_SCLK_LRESETN   0x00000002
 
#define __APP_PLL_SCLK_ENABLE   0x00000001
 
#define __ENABLE_MAC_AHB_1   0x00800000 /* ct */
 
#define __ENABLE_MAC_AHB_0   0x00400000 /* ct */
 
#define __ENABLE_MAC_1   0x00200000 /* ct */
 
#define __ENABLE_MAC_0   0x00100000 /* ct */
 
#define HOST_SEM0_REG   0x00014230 /* cb/ct */
 
#define HOST_SEM1_REG   0x00014234 /* cb/ct */
 
#define HOST_SEM2_REG   0x00014238 /* cb/ct */
 
#define HOST_SEM3_REG   0x0001423c /* cb/ct */
 
#define HOST_SEM4_REG   0x00014610 /* cb/ct */
 
#define HOST_SEM5_REG   0x00014614 /* cb/ct */
 
#define HOST_SEM6_REG   0x00014618 /* cb/ct */
 
#define HOST_SEM7_REG   0x0001461c /* cb/ct */
 
#define HOST_SEM0_INFO_REG   0x00014240 /* cb/ct */
 
#define HOST_SEM1_INFO_REG   0x00014244 /* cb/ct */
 
#define HOST_SEM2_INFO_REG   0x00014248 /* cb/ct */
 
#define HOST_SEM3_INFO_REG   0x0001424c /* cb/ct */
 
#define HOST_SEM4_INFO_REG   0x00014620 /* cb/ct */
 
#define HOST_SEM5_INFO_REG   0x00014624 /* cb/ct */
 
#define HOST_SEM6_INFO_REG   0x00014628 /* cb/ct */
 
#define HOST_SEM7_INFO_REG   0x0001462c /* cb/ct */
 
#define HOSTFN0_LPU0_CMD_STAT   0x00019000 /* cb/ct */
 
#define HOSTFN0_LPU1_CMD_STAT   0x00019004 /* cb/ct */
 
#define HOSTFN1_LPU0_CMD_STAT   0x00019010 /* cb/ct */
 
#define HOSTFN1_LPU1_CMD_STAT   0x00019014 /* cb/ct */
 
#define HOSTFN2_LPU0_CMD_STAT   0x00019150 /* ct */
 
#define HOSTFN2_LPU1_CMD_STAT   0x00019154 /* ct */
 
#define HOSTFN3_LPU0_CMD_STAT   0x00019160 /* ct */
 
#define HOSTFN3_LPU1_CMD_STAT   0x00019164 /* ct */
 
#define LPU0_HOSTFN0_CMD_STAT   0x00019008 /* cb/ct */
 
#define LPU1_HOSTFN0_CMD_STAT   0x0001900c /* cb/ct */
 
#define LPU0_HOSTFN1_CMD_STAT   0x00019018 /* cb/ct */
 
#define LPU1_HOSTFN1_CMD_STAT   0x0001901c /* cb/ct */
 
#define LPU0_HOSTFN2_CMD_STAT   0x00019158 /* ct */
 
#define LPU1_HOSTFN2_CMD_STAT   0x0001915c /* ct */
 
#define LPU0_HOSTFN3_CMD_STAT   0x00019168 /* ct */
 
#define LPU1_HOSTFN3_CMD_STAT   0x0001916c /* ct */
 
#define PSS_CTL_REG   0x00018800 /* cb/ct */
 
#define __PSS_I2C_CLK_DIV_MK   0x007f0000
 
#define __PSS_I2C_CLK_DIV_SH   16
 
#define __PSS_I2C_CLK_DIV(_v)   ((_v) << __PSS_I2C_CLK_DIV_SH)
 
#define __PSS_LMEM_INIT_DONE   0x00001000
 
#define __PSS_LMEM_RESET   0x00000200
 
#define __PSS_LMEM_INIT_EN   0x00000100
 
#define __PSS_LPU1_RESET   0x00000002
 
#define __PSS_LPU0_RESET   0x00000001
 
#define PSS_ERR_STATUS_REG   0x00018810 /* cb/ct */
 
#define ERR_SET_REG   0x00018818 /* cb/ct */
 
#define PSS_GPIO_OUT_REG   0x000188c0 /* cb/ct */
 
#define __PSS_GPIO_OUT_REG   0x00000fff
 
#define PSS_GPIO_OE_REG   0x000188c8 /* cb/ct */
 
#define __PSS_GPIO_OE_REG   0x000000ff
 
#define HOSTFN0_LPU_MBOX0_0   0x00019200 /* cb/ct */
 
#define HOSTFN1_LPU_MBOX0_8   0x00019260 /* cb/ct */
 
#define LPU_HOSTFN0_MBOX0_0   0x00019280 /* cb/ct */
 
#define LPU_HOSTFN1_MBOX0_8   0x000192e0 /* cb/ct */
 
#define HOSTFN2_LPU_MBOX0_0   0x00019400 /* ct */
 
#define HOSTFN3_LPU_MBOX0_8   0x00019460 /* ct */
 
#define LPU_HOSTFN2_MBOX0_0   0x00019480 /* ct */
 
#define LPU_HOSTFN3_MBOX0_8   0x000194e0 /* ct */
 
#define HOST_MSIX_ERR_INDEX_FN0   0x0001400c /* ct */
 
#define HOST_MSIX_ERR_INDEX_FN1   0x0001410c /* ct */
 
#define HOST_MSIX_ERR_INDEX_FN2   0x0001430c /* ct */
 
#define HOST_MSIX_ERR_INDEX_FN3   0x0001440c /* ct */
 
#define MBIST_CTL_REG   0x00014220 /* ct */
 
#define __EDRAM_BISTR_START   0x00000004
 
#define MBIST_STAT_REG   0x00014224 /* ct */
 
#define ETH_MAC_SER_REG   0x00014288 /* ct */
 
#define __APP_EMS_CKBUFAMPIN   0x00000020
 
#define __APP_EMS_REFCLKSEL   0x00000010
 
#define __APP_EMS_CMLCKSEL   0x00000008
 
#define __APP_EMS_REFCKBUFEN2   0x00000004
 
#define __APP_EMS_REFCKBUFEN1   0x00000002
 
#define __APP_EMS_CHANNEL_SEL   0x00000001
 
#define FNC_PERS_REG   0x00014604 /* ct */
 
#define __F3_FUNCTION_ACTIVE   0x80000000
 
#define __F3_FUNCTION_MODE   0x40000000
 
#define __F3_PORT_MAP_MK   0x30000000
 
#define __F3_PORT_MAP_SH   28
 
#define __F3_PORT_MAP(_v)   ((_v) << __F3_PORT_MAP_SH)
 
#define __F3_VM_MODE   0x08000000
 
#define __F3_INTX_STATUS_MK   0x07000000
 
#define __F3_INTX_STATUS_SH   24
 
#define __F3_INTX_STATUS(_v)   ((_v) << __F3_INTX_STATUS_SH)
 
#define __F2_FUNCTION_ACTIVE   0x00800000
 
#define __F2_FUNCTION_MODE   0x00400000
 
#define __F2_PORT_MAP_MK   0x00300000
 
#define __F2_PORT_MAP_SH   20
 
#define __F2_PORT_MAP(_v)   ((_v) << __F2_PORT_MAP_SH)
 
#define __F2_VM_MODE   0x00080000
 
#define __F2_INTX_STATUS_MK   0x00070000
 
#define __F2_INTX_STATUS_SH   16
 
#define __F2_INTX_STATUS(_v)   ((_v) << __F2_INTX_STATUS_SH)
 
#define __F1_FUNCTION_ACTIVE   0x00008000
 
#define __F1_FUNCTION_MODE   0x00004000
 
#define __F1_PORT_MAP_MK   0x00003000
 
#define __F1_PORT_MAP_SH   12
 
#define __F1_PORT_MAP(_v)   ((_v) << __F1_PORT_MAP_SH)
 
#define __F1_VM_MODE   0x00000800
 
#define __F1_INTX_STATUS_MK   0x00000700
 
#define __F1_INTX_STATUS_SH   8
 
#define __F1_INTX_STATUS(_v)   ((_v) << __F1_INTX_STATUS_SH)
 
#define __F0_FUNCTION_ACTIVE   0x00000080
 
#define __F0_FUNCTION_MODE   0x00000040
 
#define __F0_PORT_MAP_MK   0x00000030
 
#define __F0_PORT_MAP_SH   4
 
#define __F0_PORT_MAP(_v)   ((_v) << __F0_PORT_MAP_SH)
 
#define __F0_VM_MODE   0x00000008
 
#define __F0_INTX_STATUS   0x00000007
 
#define OP_MODE   0x0001460c
 
#define __APP_ETH_CLK_LOWSPEED   0x00000004
 
#define __GLOBAL_CORECLK_HALFSPEED   0x00000002
 
#define __GLOBAL_FCOE_MODE   0x00000001
 
#define FW_INIT_HALT_P0   0x000191ac
 
#define __FW_INIT_HALT_P   0x00000001
 
#define FW_INIT_HALT_P1   0x000191bc
 
#define PMM_1T_RESET_REG_P0   0x0002381c
 
#define __PMM_1T_RESET_P   0x00000001
 
#define PMM_1T_RESET_REG_P1   0x00023c1c
 
#define CT2_PCI_CPQ_BASE   0x00030000
 
#define CT2_PCI_APP_BASE   0x00030100
 
#define CT2_PCI_ETH_BASE   0x00030400
 
#define CT2_HOSTFN_INT_STATUS   (CT2_PCI_APP_BASE + 0x00)
 
#define CT2_HOSTFN_INTR_MASK   (CT2_PCI_APP_BASE + 0x04)
 
#define CT2_HOSTFN_PERSONALITY0   (CT2_PCI_APP_BASE + 0x08)
 
#define __PME_STATUS_   0x00200000
 
#define __PF_VF_BAR_SIZE_MODE__MK   0x00180000
 
#define __PF_VF_BAR_SIZE_MODE__SH   19
 
#define __PF_VF_BAR_SIZE_MODE_(_v)   ((_v) << __PF_VF_BAR_SIZE_MODE__SH)
 
#define __FC_LL_PORT_MAP__MK   0x00060000
 
#define __FC_LL_PORT_MAP__SH   17
 
#define __FC_LL_PORT_MAP_(_v)   ((_v) << __FC_LL_PORT_MAP__SH)
 
#define __PF_VF_ACTIVE_   0x00010000
 
#define __PF_VF_CFG_RDY_   0x00008000
 
#define __PF_VF_ENABLE_   0x00004000
 
#define __PF_DRIVER_ACTIVE_   0x00002000
 
#define __PF_PME_SEND_ENABLE_   0x00001000
 
#define __PF_EXROM_OFFSET__MK   0x00000ff0
 
#define __PF_EXROM_OFFSET__SH   4
 
#define __PF_EXROM_OFFSET_(_v)   ((_v) << __PF_EXROM_OFFSET__SH)
 
#define __FC_LL_MODE_   0x00000008
 
#define __PF_INTX_PIN_   0x00000007
 
#define CT2_HOSTFN_PERSONALITY1   (CT2_PCI_APP_BASE + 0x0C)
 
#define __PF_NUM_QUEUES1__MK   0xff000000
 
#define __PF_NUM_QUEUES1__SH   24
 
#define __PF_NUM_QUEUES1_(_v)   ((_v) << __PF_NUM_QUEUES1__SH)
 
#define __PF_VF_QUE_OFFSET1__MK   0x00ff0000
 
#define __PF_VF_QUE_OFFSET1__SH   16
 
#define __PF_VF_QUE_OFFSET1_(_v)   ((_v) << __PF_VF_QUE_OFFSET1__SH)
 
#define __PF_VF_NUM_QUEUES__MK   0x0000ff00
 
#define __PF_VF_NUM_QUEUES__SH   8
 
#define __PF_VF_NUM_QUEUES_(_v)   ((_v) << __PF_VF_NUM_QUEUES__SH)
 
#define __PF_VF_QUE_OFFSET_   0x000000ff
 
#define CT2_HOSTFN_PAGE_NUM   (CT2_PCI_APP_BASE + 0x18)
 
#define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR   (CT2_PCI_APP_BASE + 0x38)
 
#define CT2_HOSTFN_LPU0_MBOX0   (CT2_PCI_CPQ_BASE + 0x00)
 
#define CT2_HOSTFN_LPU1_MBOX0   (CT2_PCI_CPQ_BASE + 0x20)
 
#define CT2_LPU0_HOSTFN_MBOX0   (CT2_PCI_CPQ_BASE + 0x40)
 
#define CT2_LPU1_HOSTFN_MBOX0   (CT2_PCI_CPQ_BASE + 0x60)
 
#define CT2_HOSTFN_LPU0_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x80)
 
#define CT2_HOSTFN_LPU1_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x84)
 
#define CT2_LPU0_HOSTFN_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x88)
 
#define CT2_LPU1_HOSTFN_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x8c)
 
#define CT2_HOSTFN_LPU0_READ_STAT   (CT2_PCI_CPQ_BASE + 0x90)
 
#define CT2_HOSTFN_LPU1_READ_STAT   (CT2_PCI_CPQ_BASE + 0x94)
 
#define CT2_LPU0_HOSTFN_MBOX0_MSK   (CT2_PCI_CPQ_BASE + 0x98)
 
#define CT2_LPU1_HOSTFN_MBOX0_MSK   (CT2_PCI_CPQ_BASE + 0x9C)
 
#define CT2_HOST_SEM0_REG   0x000148f0
 
#define CT2_HOST_SEM1_REG   0x000148f4
 
#define CT2_HOST_SEM2_REG   0x000148f8
 
#define CT2_HOST_SEM3_REG   0x000148fc
 
#define CT2_HOST_SEM4_REG   0x00014900
 
#define CT2_HOST_SEM5_REG   0x00014904
 
#define CT2_HOST_SEM6_REG   0x00014908
 
#define CT2_HOST_SEM7_REG   0x0001490c
 
#define CT2_HOST_SEM0_INFO_REG   0x000148b0
 
#define CT2_HOST_SEM1_INFO_REG   0x000148b4
 
#define CT2_HOST_SEM2_INFO_REG   0x000148b8
 
#define CT2_HOST_SEM3_INFO_REG   0x000148bc
 
#define CT2_HOST_SEM4_INFO_REG   0x000148c0
 
#define CT2_HOST_SEM5_INFO_REG   0x000148c4
 
#define CT2_HOST_SEM6_INFO_REG   0x000148c8
 
#define CT2_HOST_SEM7_INFO_REG   0x000148cc
 
#define CT2_APP_PLL_LCLK_CTL_REG   0x00014808
 
#define __APP_LPUCLK_HALFSPEED   0x40000000
 
#define __APP_PLL_LCLK_LOAD   0x20000000
 
#define __APP_PLL_LCLK_FBCNT_MK   0x1fe00000
 
#define __APP_PLL_LCLK_FBCNT_SH   21
 
#define __APP_PLL_LCLK_FBCNT(_v)   ((_v) << __APP_PLL_SCLK_FBCNT_SH)
 
#define __APP_PLL_LCLK_EXTFB   0x00000800
 
#define __APP_PLL_LCLK_ENOUTS   0x00000400
 
#define __APP_PLL_LCLK_RATE   0x00000010
 
#define CT2_APP_PLL_SCLK_CTL_REG   0x0001480c
 
#define __P_SCLK_PLL_LOCK   0x80000000
 
#define __APP_PLL_SCLK_REFCLK_SEL   0x40000000
 
#define __APP_PLL_SCLK_CLK_DIV2   0x20000000
 
#define __APP_PLL_SCLK_LOAD   0x10000000
 
#define __APP_PLL_SCLK_FBCNT_MK   0x0ff00000
 
#define __APP_PLL_SCLK_FBCNT_SH   20
 
#define __APP_PLL_SCLK_FBCNT(_v)   ((_v) << __APP_PLL_SCLK_FBCNT_SH)
 
#define __APP_PLL_SCLK_EXTFB   0x00000800
 
#define __APP_PLL_SCLK_ENOUTS   0x00000400
 
#define __APP_PLL_SCLK_RATE   0x00000010
 
#define CT2_PCIE_MISC_REG   0x00014804
 
#define __ETH_CLK_ENABLE_PORT1   0x00000010
 
#define CT2_CHIP_MISC_PRG   0x000148a4
 
#define __ETH_CLK_ENABLE_PORT0   0x00004000
 
#define __APP_LPU_SPEED   0x00000002
 
#define CT2_MBIST_STAT_REG   0x00014818
 
#define CT2_MBIST_CTL_REG   0x0001481c
 
#define CT2_PMM_1T_CONTROL_REG_P0   0x0002381c
 
#define __PMM_1T_PNDB_P   0x00000002
 
#define CT2_PMM_1T_CONTROL_REG_P1   0x00023c1c
 
#define CT2_WGN_STATUS   0x00014990
 
#define __A2T_AHB_LOAD   0x00000800
 
#define __WGN_READY   0x00000400
 
#define __GLBL_PF_VF_CFG_RDY   0x00000200
 
#define CT2_NFC_CSR_CLR_REG   0x00027420
 
#define CT2_NFC_CSR_SET_REG   0x00027424
 
#define __HALT_NFC_CONTROLLER   0x00000002
 
#define __NFC_CONTROLLER_HALTED   0x00001000
 
#define CT2_RSC_GPR15_REG   0x0002765c
 
#define CT2_CSI_FW_CTL_REG   0x00027080
 
#define __RESET_AND_START_SCLK_LCLK_PLLS   0x00010000
 
#define CT2_CSI_FW_CTL_SET_REG   0x00027088
 
#define CT2_CSI_MAC0_CONTROL_REG   0x000270d0
 
#define __CSI_MAC_RESET   0x00000010
 
#define __CSI_MAC_AHB_RESET   0x00000008
 
#define CT2_CSI_MAC1_CONTROL_REG   0x000270d4
 
#define CT2_CSI_MAC_CONTROL_REG(__n)
 
#define BFA_IOC0_HBEAT_REG   HOST_SEM0_INFO_REG
 
#define BFA_IOC0_STATE_REG   HOST_SEM1_INFO_REG
 
#define BFA_IOC1_HBEAT_REG   HOST_SEM2_INFO_REG
 
#define BFA_IOC1_STATE_REG   HOST_SEM3_INFO_REG
 
#define BFA_FW_USE_COUNT   HOST_SEM4_INFO_REG
 
#define BFA_IOC_FAIL_SYNC   HOST_SEM5_INFO_REG
 
#define CT2_BFA_IOC0_HBEAT_REG   CT2_HOST_SEM0_INFO_REG
 
#define CT2_BFA_IOC0_STATE_REG   CT2_HOST_SEM1_INFO_REG
 
#define CT2_BFA_IOC1_HBEAT_REG   CT2_HOST_SEM2_INFO_REG
 
#define CT2_BFA_IOC1_STATE_REG   CT2_HOST_SEM3_INFO_REG
 
#define CT2_BFA_FW_USE_COUNT   CT2_HOST_SEM4_INFO_REG
 
#define CT2_BFA_IOC_FAIL_SYNC   CT2_HOST_SEM5_INFO_REG
 
#define CPE_Q_NUM(__fn, __q)   (((__fn) << 2) + (__q))
 
#define RME_Q_NUM(__fn, __q)   (((__fn) << 2) + (__q))
 
#define __HFN_INT_CPE_Q0   0x00000001U
 
#define __HFN_INT_CPE_Q1   0x00000002U
 
#define __HFN_INT_CPE_Q2   0x00000004U
 
#define __HFN_INT_CPE_Q3   0x00000008U
 
#define __HFN_INT_CPE_Q4   0x00000010U
 
#define __HFN_INT_CPE_Q5   0x00000020U
 
#define __HFN_INT_CPE_Q6   0x00000040U
 
#define __HFN_INT_CPE_Q7   0x00000080U
 
#define __HFN_INT_RME_Q0   0x00000100U
 
#define __HFN_INT_RME_Q1   0x00000200U
 
#define __HFN_INT_RME_Q2   0x00000400U
 
#define __HFN_INT_RME_Q3   0x00000800U
 
#define __HFN_INT_RME_Q4   0x00001000U
 
#define __HFN_INT_RME_Q5   0x00002000U
 
#define __HFN_INT_RME_Q6   0x00004000U
 
#define __HFN_INT_RME_Q7   0x00008000U
 
#define __HFN_INT_ERR_EMC   0x00010000U
 
#define __HFN_INT_ERR_LPU0   0x00020000U
 
#define __HFN_INT_ERR_LPU1   0x00040000U
 
#define __HFN_INT_ERR_PSS   0x00080000U
 
#define __HFN_INT_MBOX_LPU0   0x00100000U
 
#define __HFN_INT_MBOX_LPU1   0x00200000U
 
#define __HFN_INT_MBOX1_LPU0   0x00400000U
 
#define __HFN_INT_MBOX1_LPU1   0x00800000U
 
#define __HFN_INT_LL_HALT   0x01000000U
 
#define __HFN_INT_CPE_MASK   0x000000ffU
 
#define __HFN_INT_RME_MASK   0x0000ff00U
 
#define __HFN_INT_ERR_MASK
 
#define __HFN_INT_FN0_MASK
 
#define __HFN_INT_FN1_MASK
 
#define __HFN_INT_MBOX_LPU0_CT2   0x00010000U
 
#define __HFN_INT_MBOX_LPU1_CT2   0x00020000U
 
#define __HFN_INT_ERR_PSS_CT2   0x00040000U
 
#define __HFN_INT_ERR_LPU0_CT2   0x00080000U
 
#define __HFN_INT_ERR_LPU1_CT2   0x00100000U
 
#define __HFN_INT_CPQ_HALT_CT2   0x00200000U
 
#define __HFN_INT_ERR_WGN_CT2   0x00400000U
 
#define __HFN_INT_ERR_LEHRX_CT2   0x00800000U
 
#define __HFN_INT_ERR_LEHTX_CT2   0x01000000U
 
#define __HFN_INT_ERR_MASK_CT2
 
#define __HFN_INT_FN0_MASK_CT2
 
#define __HFN_INT_FN1_MASK_CT2
 
#define PSS_SMEM_PAGE_START   0x8000
 
#define PSS_SMEM_PGNUM(_pg0, _ma)   ((_pg0) + ((_ma) >> 15))
 
#define PSS_SMEM_PGOFF(_ma)   ((_ma) & 0x7fff)
 

Enumerations

enum  {
  __F0_INTX_STATUS_MSIX = 0x0, __F0_INTX_STATUS_INTA = 0x1, __F0_INTX_STATUS_INTB = 0x2, __F0_INTX_STATUS_INTC = 0x3,
  __F0_INTX_STATUS_INTD = 0x4
}
 
enum  { __APP_PLL_LCLK_FBCNT_425_MHZ = 6, __APP_PLL_LCLK_FBCNT_468_MHZ = 4 }
 
enum  { __APP_PLL_SCLK_FBCNT_NORM = 6, __APP_PLL_SCLK_FBCNT_10G_FC = 10 }
 

Macro Definition Documentation

#define __A2T_AHB_LOAD   0x00000800

Definition at line 337 of file bfi_reg.h.

#define __APP_EMS_CHANNEL_SEL   0x00000001

Definition at line 169 of file bfi_reg.h.

#define __APP_EMS_CKBUFAMPIN   0x00000020

Definition at line 164 of file bfi_reg.h.

#define __APP_EMS_CMLCKSEL   0x00000008

Definition at line 166 of file bfi_reg.h.

#define __APP_EMS_REFCKBUFEN1   0x00000002

Definition at line 168 of file bfi_reg.h.

#define __APP_EMS_REFCKBUFEN2   0x00000004

Definition at line 167 of file bfi_reg.h.

#define __APP_EMS_REFCLKSEL   0x00000010

Definition at line 165 of file bfi_reg.h.

#define __APP_ETH_CLK_LOWSPEED   0x00000004

Definition at line 214 of file bfi_reg.h.

#define __APP_LPU_SPEED   0x00000002

Definition at line 330 of file bfi_reg.h.

#define __APP_LPUCLK_HALFSPEED   0x40000000

Definition at line 299 of file bfi_reg.h.

#define __APP_PLL_LCLK_BYPASS   0x00000004

Definition at line 63 of file bfi_reg.h.

#define __APP_PLL_LCLK_CNTLMT0_1 (   _v)    ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)

Definition at line 49 of file bfi_reg.h.

#define __APP_PLL_LCLK_CNTLMT0_1_MK   0x0000c000

Definition at line 47 of file bfi_reg.h.

#define __APP_PLL_LCLK_CNTLMT0_1_SH   14

Definition at line 48 of file bfi_reg.h.

#define __APP_PLL_LCLK_ENABLE   0x00000001

Definition at line 65 of file bfi_reg.h.

#define __APP_PLL_LCLK_ENARST   0x00000008

Definition at line 62 of file bfi_reg.h.

#define __APP_PLL_LCLK_ENOUTS   0x00000400

Definition at line 309 of file bfi_reg.h.

#define __APP_PLL_LCLK_EXTFB   0x00000800

Definition at line 308 of file bfi_reg.h.

#define __APP_PLL_LCLK_FBCNT (   _v)    ((_v) << __APP_PLL_SCLK_FBCNT_SH)

Definition at line 303 of file bfi_reg.h.

#define __APP_PLL_LCLK_FBCNT_MK   0x1fe00000

Definition at line 301 of file bfi_reg.h.

#define __APP_PLL_LCLK_FBCNT_SH   21

Definition at line 302 of file bfi_reg.h.

#define __APP_PLL_LCLK_HDIV   0x00000400

Definition at line 54 of file bfi_reg.h.

#define __APP_PLL_LCLK_HREF   0x00000800

Definition at line 53 of file bfi_reg.h.

#define __APP_PLL_LCLK_JITLMT0_1 (   _v)    ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)

Definition at line 52 of file bfi_reg.h.

#define __APP_PLL_LCLK_JITLMT0_1_MK   0x00003000

Definition at line 50 of file bfi_reg.h.

#define __APP_PLL_LCLK_JITLMT0_1_SH   12

Definition at line 51 of file bfi_reg.h.

#define __APP_PLL_LCLK_LOAD   0x20000000

Definition at line 300 of file bfi_reg.h.

#define __APP_PLL_LCLK_LOGIC_SOFT_RESET   0x00010000

Definition at line 46 of file bfi_reg.h.

#define __APP_PLL_LCLK_LRESETN   0x00000002

Definition at line 64 of file bfi_reg.h.

#define __APP_PLL_LCLK_P0_1 (   _v)    ((_v) << __APP_PLL_LCLK_P0_1_SH)

Definition at line 57 of file bfi_reg.h.

#define __APP_PLL_LCLK_P0_1_MK   0x00000300

Definition at line 55 of file bfi_reg.h.

#define __APP_PLL_LCLK_P0_1_SH   8

Definition at line 56 of file bfi_reg.h.

#define __APP_PLL_LCLK_RATE   0x00000010

Definition at line 310 of file bfi_reg.h.

#define __APP_PLL_LCLK_RESET_TIMER (   _v)    ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)

Definition at line 45 of file bfi_reg.h.

#define __APP_PLL_LCLK_RESET_TIMER_MK   0x000e0000

Definition at line 43 of file bfi_reg.h.

#define __APP_PLL_LCLK_RESET_TIMER_SH   17

Definition at line 44 of file bfi_reg.h.

#define __APP_PLL_LCLK_RSEL200500   0x00000010

Definition at line 61 of file bfi_reg.h.

#define __APP_PLL_LCLK_SRAM_USE_100MHZ   0x00100000

Definition at line 42 of file bfi_reg.h.

#define __APP_PLL_LCLK_Z0_2 (   _v)    ((_v) << __APP_PLL_LCLK_Z0_2_SH)

Definition at line 60 of file bfi_reg.h.

#define __APP_PLL_LCLK_Z0_2_MK   0x000000e0

Definition at line 58 of file bfi_reg.h.

#define __APP_PLL_LCLK_Z0_2_SH   5

Definition at line 59 of file bfi_reg.h.

#define __APP_PLL_SCLK_BYPASS   0x00000004

Definition at line 88 of file bfi_reg.h.

#define __APP_PLL_SCLK_CLK_DIV2   0x20000000

Definition at line 314 of file bfi_reg.h.

#define __APP_PLL_SCLK_CNTLMT0_1 (   _v)    ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)

Definition at line 74 of file bfi_reg.h.

#define __APP_PLL_SCLK_CNTLMT0_1_MK   0x0000c000

Definition at line 72 of file bfi_reg.h.

#define __APP_PLL_SCLK_CNTLMT0_1_SH   14

Definition at line 73 of file bfi_reg.h.

#define __APP_PLL_SCLK_ENABLE   0x00000001

Definition at line 90 of file bfi_reg.h.

#define __APP_PLL_SCLK_ENARST   0x00000008

Definition at line 87 of file bfi_reg.h.

#define __APP_PLL_SCLK_ENOUTS   0x00000400

Definition at line 324 of file bfi_reg.h.

#define __APP_PLL_SCLK_EXTFB   0x00000800

Definition at line 323 of file bfi_reg.h.

#define __APP_PLL_SCLK_FBCNT (   _v)    ((_v) << __APP_PLL_SCLK_FBCNT_SH)

Definition at line 318 of file bfi_reg.h.

#define __APP_PLL_SCLK_FBCNT_MK   0x0ff00000

Definition at line 316 of file bfi_reg.h.

#define __APP_PLL_SCLK_FBCNT_SH   20

Definition at line 317 of file bfi_reg.h.

#define __APP_PLL_SCLK_HDIV   0x00000400

Definition at line 79 of file bfi_reg.h.

#define __APP_PLL_SCLK_HREF   0x00000800

Definition at line 78 of file bfi_reg.h.

#define __APP_PLL_SCLK_JITLMT0_1 (   _v)    ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)

Definition at line 77 of file bfi_reg.h.

#define __APP_PLL_SCLK_JITLMT0_1_MK   0x00003000

Definition at line 75 of file bfi_reg.h.

#define __APP_PLL_SCLK_JITLMT0_1_SH   12

Definition at line 76 of file bfi_reg.h.

#define __APP_PLL_SCLK_LOAD   0x10000000

Definition at line 315 of file bfi_reg.h.

#define __APP_PLL_SCLK_LOGIC_SOFT_RESET   0x00010000

Definition at line 71 of file bfi_reg.h.

#define __APP_PLL_SCLK_LRESETN   0x00000002

Definition at line 89 of file bfi_reg.h.

#define __APP_PLL_SCLK_P0_1 (   _v)    ((_v) << __APP_PLL_SCLK_P0_1_SH)

Definition at line 82 of file bfi_reg.h.

#define __APP_PLL_SCLK_P0_1_MK   0x00000300

Definition at line 80 of file bfi_reg.h.

#define __APP_PLL_SCLK_P0_1_SH   8

Definition at line 81 of file bfi_reg.h.

#define __APP_PLL_SCLK_RATE   0x00000010

Definition at line 325 of file bfi_reg.h.

#define __APP_PLL_SCLK_REFCLK_SEL   0x40000000

Definition at line 313 of file bfi_reg.h.

#define __APP_PLL_SCLK_RESET_TIMER (   _v)    ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)

Definition at line 70 of file bfi_reg.h.

#define __APP_PLL_SCLK_RESET_TIMER_MK   0x000e0000

Definition at line 68 of file bfi_reg.h.

#define __APP_PLL_SCLK_RESET_TIMER_SH   17

Definition at line 69 of file bfi_reg.h.

#define __APP_PLL_SCLK_RSEL200500   0x00000010

Definition at line 86 of file bfi_reg.h.

#define __APP_PLL_SCLK_Z0_2 (   _v)    ((_v) << __APP_PLL_SCLK_Z0_2_SH)

Definition at line 85 of file bfi_reg.h.

#define __APP_PLL_SCLK_Z0_2_MK   0x000000e0

Definition at line 83 of file bfi_reg.h.

#define __APP_PLL_SCLK_Z0_2_SH   5

Definition at line 84 of file bfi_reg.h.

#define __CSI_MAC_AHB_RESET   0x00000008

Definition at line 352 of file bfi_reg.h.

#define __CSI_MAC_RESET   0x00000010

Definition at line 351 of file bfi_reg.h.

#define __EDRAM_BISTR_START   0x00000004

Definition at line 161 of file bfi_reg.h.

#define __ENABLE_MAC_0   0x00100000 /* ct */

Definition at line 94 of file bfi_reg.h.

#define __ENABLE_MAC_1   0x00200000 /* ct */

Definition at line 93 of file bfi_reg.h.

#define __ENABLE_MAC_AHB_0   0x00400000 /* ct */

Definition at line 92 of file bfi_reg.h.

#define __ENABLE_MAC_AHB_1   0x00800000 /* ct */

Definition at line 91 of file bfi_reg.h.

#define __ETH_CLK_ENABLE_PORT0   0x00004000

Definition at line 329 of file bfi_reg.h.

#define __ETH_CLK_ENABLE_PORT1   0x00000010

Definition at line 327 of file bfi_reg.h.

#define __F0_FUNCTION_ACTIVE   0x00000080

Definition at line 198 of file bfi_reg.h.

#define __F0_FUNCTION_MODE   0x00000040

Definition at line 199 of file bfi_reg.h.

#define __F0_INTX_STATUS   0x00000007

Definition at line 204 of file bfi_reg.h.

#define __F0_PORT_MAP (   _v)    ((_v) << __F0_PORT_MAP_SH)

Definition at line 202 of file bfi_reg.h.

#define __F0_PORT_MAP_MK   0x00000030

Definition at line 200 of file bfi_reg.h.

#define __F0_PORT_MAP_SH   4

Definition at line 201 of file bfi_reg.h.

#define __F0_VM_MODE   0x00000008

Definition at line 203 of file bfi_reg.h.

#define __F1_FUNCTION_ACTIVE   0x00008000

Definition at line 189 of file bfi_reg.h.

#define __F1_FUNCTION_MODE   0x00004000

Definition at line 190 of file bfi_reg.h.

#define __F1_INTX_STATUS (   _v)    ((_v) << __F1_INTX_STATUS_SH)

Definition at line 197 of file bfi_reg.h.

#define __F1_INTX_STATUS_MK   0x00000700

Definition at line 195 of file bfi_reg.h.

#define __F1_INTX_STATUS_SH   8

Definition at line 196 of file bfi_reg.h.

#define __F1_PORT_MAP (   _v)    ((_v) << __F1_PORT_MAP_SH)

Definition at line 193 of file bfi_reg.h.

#define __F1_PORT_MAP_MK   0x00003000

Definition at line 191 of file bfi_reg.h.

#define __F1_PORT_MAP_SH   12

Definition at line 192 of file bfi_reg.h.

#define __F1_VM_MODE   0x00000800

Definition at line 194 of file bfi_reg.h.

#define __F2_FUNCTION_ACTIVE   0x00800000

Definition at line 180 of file bfi_reg.h.

#define __F2_FUNCTION_MODE   0x00400000

Definition at line 181 of file bfi_reg.h.

#define __F2_INTX_STATUS (   _v)    ((_v) << __F2_INTX_STATUS_SH)

Definition at line 188 of file bfi_reg.h.

#define __F2_INTX_STATUS_MK   0x00070000

Definition at line 186 of file bfi_reg.h.

#define __F2_INTX_STATUS_SH   16

Definition at line 187 of file bfi_reg.h.

#define __F2_PORT_MAP (   _v)    ((_v) << __F2_PORT_MAP_SH)

Definition at line 184 of file bfi_reg.h.

#define __F2_PORT_MAP_MK   0x00300000

Definition at line 182 of file bfi_reg.h.

#define __F2_PORT_MAP_SH   20

Definition at line 183 of file bfi_reg.h.

#define __F2_VM_MODE   0x00080000

Definition at line 185 of file bfi_reg.h.

#define __F3_FUNCTION_ACTIVE   0x80000000

Definition at line 171 of file bfi_reg.h.

#define __F3_FUNCTION_MODE   0x40000000

Definition at line 172 of file bfi_reg.h.

#define __F3_INTX_STATUS (   _v)    ((_v) << __F3_INTX_STATUS_SH)

Definition at line 179 of file bfi_reg.h.

#define __F3_INTX_STATUS_MK   0x07000000

Definition at line 177 of file bfi_reg.h.

#define __F3_INTX_STATUS_SH   24

Definition at line 178 of file bfi_reg.h.

#define __F3_PORT_MAP (   _v)    ((_v) << __F3_PORT_MAP_SH)

Definition at line 175 of file bfi_reg.h.

#define __F3_PORT_MAP_MK   0x30000000

Definition at line 173 of file bfi_reg.h.

#define __F3_PORT_MAP_SH   28

Definition at line 174 of file bfi_reg.h.

#define __F3_VM_MODE   0x08000000

Definition at line 176 of file bfi_reg.h.

#define __FC_LL_MODE_   0x00000008

Definition at line 250 of file bfi_reg.h.

#define __FC_LL_PORT_MAP_ (   _v)    ((_v) << __FC_LL_PORT_MAP__SH)

Definition at line 241 of file bfi_reg.h.

#define __FC_LL_PORT_MAP__MK   0x00060000

Definition at line 239 of file bfi_reg.h.

#define __FC_LL_PORT_MAP__SH   17

Definition at line 240 of file bfi_reg.h.

#define __FW_INIT_HALT_P   0x00000001

Definition at line 218 of file bfi_reg.h.

#define __GLBL_PF_VF_CFG_RDY   0x00000200

Definition at line 339 of file bfi_reg.h.

#define __GLOBAL_CORECLK_HALFSPEED   0x00000002

Definition at line 215 of file bfi_reg.h.

#define __GLOBAL_FCOE_MODE   0x00000001

Definition at line 216 of file bfi_reg.h.

#define __HALT_NFC_CONTROLLER   0x00000002

Definition at line 342 of file bfi_reg.h.

#define __HFN_INT_CPE_MASK   0x000000ffU

Definition at line 409 of file bfi_reg.h.

#define __HFN_INT_CPE_Q0   0x00000001U

Definition at line 384 of file bfi_reg.h.

#define __HFN_INT_CPE_Q1   0x00000002U

Definition at line 385 of file bfi_reg.h.

#define __HFN_INT_CPE_Q2   0x00000004U

Definition at line 386 of file bfi_reg.h.

#define __HFN_INT_CPE_Q3   0x00000008U

Definition at line 387 of file bfi_reg.h.

#define __HFN_INT_CPE_Q4   0x00000010U

Definition at line 388 of file bfi_reg.h.

#define __HFN_INT_CPE_Q5   0x00000020U

Definition at line 389 of file bfi_reg.h.

#define __HFN_INT_CPE_Q6   0x00000040U

Definition at line 390 of file bfi_reg.h.

#define __HFN_INT_CPE_Q7   0x00000080U

Definition at line 391 of file bfi_reg.h.

#define __HFN_INT_CPQ_HALT_CT2   0x00200000U

Definition at line 431 of file bfi_reg.h.

#define __HFN_INT_ERR_EMC   0x00010000U

Definition at line 400 of file bfi_reg.h.

#define __HFN_INT_ERR_LEHRX_CT2   0x00800000U

Definition at line 433 of file bfi_reg.h.

#define __HFN_INT_ERR_LEHTX_CT2   0x01000000U

Definition at line 434 of file bfi_reg.h.

#define __HFN_INT_ERR_LPU0   0x00020000U

Definition at line 401 of file bfi_reg.h.

#define __HFN_INT_ERR_LPU0_CT2   0x00080000U

Definition at line 429 of file bfi_reg.h.

#define __HFN_INT_ERR_LPU1   0x00040000U

Definition at line 402 of file bfi_reg.h.

#define __HFN_INT_ERR_LPU1_CT2   0x00100000U

Definition at line 430 of file bfi_reg.h.

#define __HFN_INT_ERR_MASK
Value:

Definition at line 411 of file bfi_reg.h.

#define __HFN_INT_ERR_MASK_CT2
Value:
__HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \
__HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \
__HFN_INT_ERR_LEHTX_CT2)

Definition at line 435 of file bfi_reg.h.

#define __HFN_INT_ERR_PSS   0x00080000U

Definition at line 403 of file bfi_reg.h.

#define __HFN_INT_ERR_PSS_CT2   0x00040000U

Definition at line 428 of file bfi_reg.h.

#define __HFN_INT_ERR_WGN_CT2   0x00400000U

Definition at line 432 of file bfi_reg.h.

#define __HFN_INT_FN0_MASK
Value:

Definition at line 414 of file bfi_reg.h.

#define __HFN_INT_FN0_MASK_CT2
Value:

Definition at line 440 of file bfi_reg.h.

#define __HFN_INT_FN1_MASK
Value:

Definition at line 418 of file bfi_reg.h.

#define __HFN_INT_FN1_MASK_CT2
Value:

Definition at line 444 of file bfi_reg.h.

#define __HFN_INT_LL_HALT   0x01000000U

Definition at line 408 of file bfi_reg.h.

#define __HFN_INT_MBOX1_LPU0   0x00400000U

Definition at line 406 of file bfi_reg.h.

#define __HFN_INT_MBOX1_LPU1   0x00800000U

Definition at line 407 of file bfi_reg.h.

#define __HFN_INT_MBOX_LPU0   0x00100000U

Definition at line 404 of file bfi_reg.h.

#define __HFN_INT_MBOX_LPU0_CT2   0x00010000U

Definition at line 426 of file bfi_reg.h.

#define __HFN_INT_MBOX_LPU1   0x00200000U

Definition at line 405 of file bfi_reg.h.

#define __HFN_INT_MBOX_LPU1_CT2   0x00020000U

Definition at line 427 of file bfi_reg.h.

#define __HFN_INT_RME_MASK   0x0000ff00U

Definition at line 410 of file bfi_reg.h.

#define __HFN_INT_RME_Q0   0x00000100U

Definition at line 392 of file bfi_reg.h.

#define __HFN_INT_RME_Q1   0x00000200U

Definition at line 393 of file bfi_reg.h.

#define __HFN_INT_RME_Q2   0x00000400U

Definition at line 394 of file bfi_reg.h.

#define __HFN_INT_RME_Q3   0x00000800U

Definition at line 395 of file bfi_reg.h.

#define __HFN_INT_RME_Q4   0x00001000U

Definition at line 396 of file bfi_reg.h.

#define __HFN_INT_RME_Q5   0x00002000U

Definition at line 397 of file bfi_reg.h.

#define __HFN_INT_RME_Q6   0x00004000U

Definition at line 398 of file bfi_reg.h.

#define __HFN_INT_RME_Q7   0x00008000U

Definition at line 399 of file bfi_reg.h.

#define __NFC_CONTROLLER_HALTED   0x00001000

Definition at line 343 of file bfi_reg.h.

#define __P_LCLK_PLL_LOCK   0x80000000

Definition at line 41 of file bfi_reg.h.

#define __P_SCLK_PLL_LOCK   0x80000000

Definition at line 312 of file bfi_reg.h.

#define __P_SCLK_PLL_LOCK   0x80000000

Definition at line 312 of file bfi_reg.h.

#define __PF_DRIVER_ACTIVE_   0x00002000

Definition at line 245 of file bfi_reg.h.

#define __PF_EXROM_OFFSET_ (   _v)    ((_v) << __PF_EXROM_OFFSET__SH)

Definition at line 249 of file bfi_reg.h.

#define __PF_EXROM_OFFSET__MK   0x00000ff0

Definition at line 247 of file bfi_reg.h.

#define __PF_EXROM_OFFSET__SH   4

Definition at line 248 of file bfi_reg.h.

#define __PF_INTX_PIN_   0x00000007

Definition at line 251 of file bfi_reg.h.

#define __PF_NUM_QUEUES1_ (   _v)    ((_v) << __PF_NUM_QUEUES1__SH)

Definition at line 255 of file bfi_reg.h.

#define __PF_NUM_QUEUES1__MK   0xff000000

Definition at line 253 of file bfi_reg.h.

#define __PF_NUM_QUEUES1__SH   24

Definition at line 254 of file bfi_reg.h.

#define __PF_PME_SEND_ENABLE_   0x00001000

Definition at line 246 of file bfi_reg.h.

#define __PF_VF_ACTIVE_   0x00010000

Definition at line 242 of file bfi_reg.h.

#define __PF_VF_BAR_SIZE_MODE_ (   _v)    ((_v) << __PF_VF_BAR_SIZE_MODE__SH)

Definition at line 238 of file bfi_reg.h.

#define __PF_VF_BAR_SIZE_MODE__MK   0x00180000

Definition at line 236 of file bfi_reg.h.

#define __PF_VF_BAR_SIZE_MODE__SH   19

Definition at line 237 of file bfi_reg.h.

#define __PF_VF_CFG_RDY_   0x00008000

Definition at line 243 of file bfi_reg.h.

#define __PF_VF_ENABLE_   0x00004000

Definition at line 244 of file bfi_reg.h.

#define __PF_VF_NUM_QUEUES_ (   _v)    ((_v) << __PF_VF_NUM_QUEUES__SH)

Definition at line 261 of file bfi_reg.h.

#define __PF_VF_NUM_QUEUES__MK   0x0000ff00

Definition at line 259 of file bfi_reg.h.

#define __PF_VF_NUM_QUEUES__SH   8

Definition at line 260 of file bfi_reg.h.

#define __PF_VF_QUE_OFFSET1_ (   _v)    ((_v) << __PF_VF_QUE_OFFSET1__SH)

Definition at line 258 of file bfi_reg.h.

#define __PF_VF_QUE_OFFSET1__MK   0x00ff0000

Definition at line 256 of file bfi_reg.h.

#define __PF_VF_QUE_OFFSET1__SH   16

Definition at line 257 of file bfi_reg.h.

#define __PF_VF_QUE_OFFSET_   0x000000ff

Definition at line 262 of file bfi_reg.h.

#define __PME_STATUS_   0x00200000

Definition at line 235 of file bfi_reg.h.

#define __PMM_1T_PNDB_P   0x00000002

Definition at line 334 of file bfi_reg.h.

#define __PMM_1T_RESET_P   0x00000001

Definition at line 221 of file bfi_reg.h.

#define __PSS_GPIO_OE_REG   0x000000ff

Definition at line 144 of file bfi_reg.h.

#define __PSS_GPIO_OUT_REG   0x00000fff

Definition at line 142 of file bfi_reg.h.

#define __PSS_I2C_CLK_DIV (   _v)    ((_v) << __PSS_I2C_CLK_DIV_SH)

Definition at line 133 of file bfi_reg.h.

#define __PSS_I2C_CLK_DIV_MK   0x007f0000

Definition at line 131 of file bfi_reg.h.

#define __PSS_I2C_CLK_DIV_SH   16

Definition at line 132 of file bfi_reg.h.

#define __PSS_LMEM_INIT_DONE   0x00001000

Definition at line 134 of file bfi_reg.h.

#define __PSS_LMEM_INIT_EN   0x00000100

Definition at line 136 of file bfi_reg.h.

#define __PSS_LMEM_RESET   0x00000200

Definition at line 135 of file bfi_reg.h.

#define __PSS_LPU0_RESET   0x00000001

Definition at line 138 of file bfi_reg.h.

#define __PSS_LPU1_RESET   0x00000002

Definition at line 137 of file bfi_reg.h.

#define __RESET_AND_START_SCLK_LCLK_PLLS   0x00010000

Definition at line 347 of file bfi_reg.h.

#define __WGN_READY   0x00000400

Definition at line 338 of file bfi_reg.h.

#define APP_PLL_LCLK_CTL_REG   0x00014204 /* cb/ct */

Definition at line 40 of file bfi_reg.h.

#define APP_PLL_SCLK_CTL_REG   0x00014208 /* cb/ct */

Definition at line 66 of file bfi_reg.h.

#define BFA_FW_USE_COUNT   HOST_SEM4_INFO_REG

Definition at line 365 of file bfi_reg.h.

#define BFA_IOC0_HBEAT_REG   HOST_SEM0_INFO_REG

Definition at line 361 of file bfi_reg.h.

#define BFA_IOC0_STATE_REG   HOST_SEM1_INFO_REG

Definition at line 362 of file bfi_reg.h.

#define BFA_IOC1_HBEAT_REG   HOST_SEM2_INFO_REG

Definition at line 363 of file bfi_reg.h.

#define BFA_IOC1_STATE_REG   HOST_SEM3_INFO_REG

Definition at line 364 of file bfi_reg.h.

#define BFA_IOC_FAIL_SYNC   HOST_SEM5_INFO_REG

Definition at line 366 of file bfi_reg.h.

#define CPE_Q_NUM (   __fn,
  __q 
)    (((__fn) << 2) + (__q))

Definition at line 378 of file bfi_reg.h.

#define CT2_APP_PLL_LCLK_CTL_REG   0x00014808

Definition at line 298 of file bfi_reg.h.

#define CT2_APP_PLL_SCLK_CTL_REG   0x0001480c

Definition at line 311 of file bfi_reg.h.

#define CT2_BFA_FW_USE_COUNT   CT2_HOST_SEM4_INFO_REG

Definition at line 375 of file bfi_reg.h.

#define CT2_BFA_IOC0_HBEAT_REG   CT2_HOST_SEM0_INFO_REG

Definition at line 371 of file bfi_reg.h.

#define CT2_BFA_IOC0_STATE_REG   CT2_HOST_SEM1_INFO_REG

Definition at line 372 of file bfi_reg.h.

#define CT2_BFA_IOC1_HBEAT_REG   CT2_HOST_SEM2_INFO_REG

Definition at line 373 of file bfi_reg.h.

#define CT2_BFA_IOC1_STATE_REG   CT2_HOST_SEM3_INFO_REG

Definition at line 374 of file bfi_reg.h.

#define CT2_BFA_IOC_FAIL_SYNC   CT2_HOST_SEM5_INFO_REG

Definition at line 376 of file bfi_reg.h.

#define CT2_CHIP_MISC_PRG   0x000148a4

Definition at line 328 of file bfi_reg.h.

#define CT2_CSI_FW_CTL_REG   0x00027080

Definition at line 346 of file bfi_reg.h.

#define CT2_CSI_FW_CTL_SET_REG   0x00027088

Definition at line 348 of file bfi_reg.h.

#define CT2_CSI_MAC0_CONTROL_REG   0x000270d0

Definition at line 350 of file bfi_reg.h.

#define CT2_CSI_MAC1_CONTROL_REG   0x000270d4

Definition at line 353 of file bfi_reg.h.

#define CT2_CSI_MAC_CONTROL_REG (   __n)
Value:

Definition at line 354 of file bfi_reg.h.

#define CT2_HOST_SEM0_INFO_REG   0x000148b0

Definition at line 289 of file bfi_reg.h.

#define CT2_HOST_SEM0_REG   0x000148f0

Definition at line 281 of file bfi_reg.h.

#define CT2_HOST_SEM1_INFO_REG   0x000148b4

Definition at line 290 of file bfi_reg.h.

#define CT2_HOST_SEM1_REG   0x000148f4

Definition at line 282 of file bfi_reg.h.

#define CT2_HOST_SEM2_INFO_REG   0x000148b8

Definition at line 291 of file bfi_reg.h.

#define CT2_HOST_SEM2_REG   0x000148f8

Definition at line 283 of file bfi_reg.h.

#define CT2_HOST_SEM3_INFO_REG   0x000148bc

Definition at line 292 of file bfi_reg.h.

#define CT2_HOST_SEM3_REG   0x000148fc

Definition at line 284 of file bfi_reg.h.

#define CT2_HOST_SEM4_INFO_REG   0x000148c0

Definition at line 293 of file bfi_reg.h.

#define CT2_HOST_SEM4_REG   0x00014900

Definition at line 285 of file bfi_reg.h.

#define CT2_HOST_SEM5_INFO_REG   0x000148c4

Definition at line 294 of file bfi_reg.h.

#define CT2_HOST_SEM5_REG   0x00014904

Definition at line 286 of file bfi_reg.h.

#define CT2_HOST_SEM6_INFO_REG   0x000148c8

Definition at line 295 of file bfi_reg.h.

#define CT2_HOST_SEM6_REG   0x00014908

Definition at line 287 of file bfi_reg.h.

#define CT2_HOST_SEM7_INFO_REG   0x000148cc

Definition at line 296 of file bfi_reg.h.

#define CT2_HOST_SEM7_REG   0x0001490c

Definition at line 288 of file bfi_reg.h.

#define CT2_HOSTFN_INT_STATUS   (CT2_PCI_APP_BASE + 0x00)

Definition at line 232 of file bfi_reg.h.

#define CT2_HOSTFN_INTR_MASK   (CT2_PCI_APP_BASE + 0x04)

Definition at line 233 of file bfi_reg.h.

#define CT2_HOSTFN_LPU0_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x80)

Definition at line 273 of file bfi_reg.h.

#define CT2_HOSTFN_LPU0_MBOX0   (CT2_PCI_CPQ_BASE + 0x00)

Definition at line 269 of file bfi_reg.h.

#define CT2_HOSTFN_LPU0_READ_STAT   (CT2_PCI_CPQ_BASE + 0x90)

Definition at line 277 of file bfi_reg.h.

#define CT2_HOSTFN_LPU1_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x84)

Definition at line 274 of file bfi_reg.h.

#define CT2_HOSTFN_LPU1_MBOX0   (CT2_PCI_CPQ_BASE + 0x20)

Definition at line 270 of file bfi_reg.h.

#define CT2_HOSTFN_LPU1_READ_STAT   (CT2_PCI_CPQ_BASE + 0x94)

Definition at line 278 of file bfi_reg.h.

#define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR   (CT2_PCI_APP_BASE + 0x38)

Definition at line 264 of file bfi_reg.h.

#define CT2_HOSTFN_PAGE_NUM   (CT2_PCI_APP_BASE + 0x18)

Definition at line 263 of file bfi_reg.h.

#define CT2_HOSTFN_PERSONALITY0   (CT2_PCI_APP_BASE + 0x08)

Definition at line 234 of file bfi_reg.h.

#define CT2_HOSTFN_PERSONALITY1   (CT2_PCI_APP_BASE + 0x0C)

Definition at line 252 of file bfi_reg.h.

#define CT2_LPU0_HOSTFN_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x88)

Definition at line 275 of file bfi_reg.h.

#define CT2_LPU0_HOSTFN_MBOX0   (CT2_PCI_CPQ_BASE + 0x40)

Definition at line 271 of file bfi_reg.h.

#define CT2_LPU0_HOSTFN_MBOX0_MSK   (CT2_PCI_CPQ_BASE + 0x98)

Definition at line 279 of file bfi_reg.h.

#define CT2_LPU1_HOSTFN_CMD_STAT   (CT2_PCI_CPQ_BASE + 0x8c)

Definition at line 276 of file bfi_reg.h.

#define CT2_LPU1_HOSTFN_MBOX0   (CT2_PCI_CPQ_BASE + 0x60)

Definition at line 272 of file bfi_reg.h.

#define CT2_LPU1_HOSTFN_MBOX0_MSK   (CT2_PCI_CPQ_BASE + 0x9C)

Definition at line 280 of file bfi_reg.h.

#define CT2_MBIST_CTL_REG   0x0001481c

Definition at line 332 of file bfi_reg.h.

#define CT2_MBIST_STAT_REG   0x00014818

Definition at line 331 of file bfi_reg.h.

#define CT2_NFC_CSR_CLR_REG   0x00027420

Definition at line 340 of file bfi_reg.h.

#define CT2_NFC_CSR_SET_REG   0x00027424

Definition at line 341 of file bfi_reg.h.

#define CT2_PCI_APP_BASE   0x00030100

Definition at line 226 of file bfi_reg.h.

#define CT2_PCI_CPQ_BASE   0x00030000

Definition at line 225 of file bfi_reg.h.

#define CT2_PCI_ETH_BASE   0x00030400

Definition at line 227 of file bfi_reg.h.

#define CT2_PCIE_MISC_REG   0x00014804

Definition at line 326 of file bfi_reg.h.

#define CT2_PMM_1T_CONTROL_REG_P0   0x0002381c

Definition at line 333 of file bfi_reg.h.

#define CT2_PMM_1T_CONTROL_REG_P1   0x00023c1c

Definition at line 335 of file bfi_reg.h.

#define CT2_RSC_GPR15_REG   0x0002765c

Definition at line 345 of file bfi_reg.h.

#define CT2_WGN_STATUS   0x00014990

Definition at line 336 of file bfi_reg.h.

#define ERR_SET_REG   0x00018818 /* cb/ct */

Definition at line 140 of file bfi_reg.h.

#define ETH_MAC_SER_REG   0x00014288 /* ct */

Definition at line 163 of file bfi_reg.h.

#define FNC_PERS_REG   0x00014604 /* ct */

Definition at line 170 of file bfi_reg.h.

#define FW_INIT_HALT_P0   0x000191ac

Definition at line 217 of file bfi_reg.h.

#define FW_INIT_HALT_P1   0x000191bc

Definition at line 219 of file bfi_reg.h.

#define HOST_MSIX_ERR_INDEX_FN0   0x0001400c /* ct */

Definition at line 155 of file bfi_reg.h.

#define HOST_MSIX_ERR_INDEX_FN1   0x0001410c /* ct */

Definition at line 156 of file bfi_reg.h.

#define HOST_MSIX_ERR_INDEX_FN2   0x0001430c /* ct */

Definition at line 157 of file bfi_reg.h.

#define HOST_MSIX_ERR_INDEX_FN3   0x0001440c /* ct */

Definition at line 158 of file bfi_reg.h.

#define HOST_PAGE_NUM_FN0   0x00014008 /* cb/ct */

Definition at line 35 of file bfi_reg.h.

#define HOST_PAGE_NUM_FN1   0x00014108 /* cb/ct */

Definition at line 36 of file bfi_reg.h.

#define HOST_PAGE_NUM_FN2   0x00014308 /* ct */

Definition at line 37 of file bfi_reg.h.

#define HOST_PAGE_NUM_FN3   0x00014408 /* ct */

Definition at line 38 of file bfi_reg.h.

#define HOST_SEM0_INFO_REG   0x00014240 /* cb/ct */

Definition at line 104 of file bfi_reg.h.

#define HOST_SEM0_REG   0x00014230 /* cb/ct */

Definition at line 96 of file bfi_reg.h.

#define HOST_SEM1_INFO_REG   0x00014244 /* cb/ct */

Definition at line 105 of file bfi_reg.h.

#define HOST_SEM1_REG   0x00014234 /* cb/ct */

Definition at line 97 of file bfi_reg.h.

#define HOST_SEM2_INFO_REG   0x00014248 /* cb/ct */

Definition at line 106 of file bfi_reg.h.

#define HOST_SEM2_REG   0x00014238 /* cb/ct */

Definition at line 98 of file bfi_reg.h.

#define HOST_SEM3_INFO_REG   0x0001424c /* cb/ct */

Definition at line 107 of file bfi_reg.h.

#define HOST_SEM3_REG   0x0001423c /* cb/ct */

Definition at line 99 of file bfi_reg.h.

#define HOST_SEM4_INFO_REG   0x00014620 /* cb/ct */

Definition at line 108 of file bfi_reg.h.

#define HOST_SEM4_REG   0x00014610 /* cb/ct */

Definition at line 100 of file bfi_reg.h.

#define HOST_SEM5_INFO_REG   0x00014624 /* cb/ct */

Definition at line 109 of file bfi_reg.h.

#define HOST_SEM5_REG   0x00014614 /* cb/ct */

Definition at line 101 of file bfi_reg.h.

#define HOST_SEM6_INFO_REG   0x00014628 /* cb/ct */

Definition at line 110 of file bfi_reg.h.

#define HOST_SEM6_REG   0x00014618 /* cb/ct */

Definition at line 102 of file bfi_reg.h.

#define HOST_SEM7_INFO_REG   0x0001462c /* cb/ct */

Definition at line 111 of file bfi_reg.h.

#define HOST_SEM7_REG   0x0001461c /* cb/ct */

Definition at line 103 of file bfi_reg.h.

#define HOSTFN0_INT_MSK   0x00014004 /* cb/ct */

Definition at line 30 of file bfi_reg.h.

#define HOSTFN0_INT_STATUS   0x00014000 /* cb/ct */

Definition at line 26 of file bfi_reg.h.

#define HOSTFN0_LPU0_CMD_STAT   0x00019000 /* cb/ct */

Definition at line 113 of file bfi_reg.h.

#define HOSTFN0_LPU1_CMD_STAT   0x00019004 /* cb/ct */

Definition at line 114 of file bfi_reg.h.

#define HOSTFN0_LPU_MBOX0_0   0x00019200 /* cb/ct */

Definition at line 146 of file bfi_reg.h.

#define HOSTFN1_INT_MSK   0x00014104 /* cb/ct */

Definition at line 31 of file bfi_reg.h.

#define HOSTFN1_INT_STATUS   0x00014100 /* cb/ct */

Definition at line 27 of file bfi_reg.h.

#define HOSTFN1_LPU0_CMD_STAT   0x00019010 /* cb/ct */

Definition at line 115 of file bfi_reg.h.

#define HOSTFN1_LPU1_CMD_STAT   0x00019014 /* cb/ct */

Definition at line 116 of file bfi_reg.h.

#define HOSTFN1_LPU_MBOX0_8   0x00019260 /* cb/ct */

Definition at line 147 of file bfi_reg.h.

#define HOSTFN2_INT_MSK   0x00014304 /* ct */

Definition at line 32 of file bfi_reg.h.

#define HOSTFN2_INT_STATUS   0x00014300 /* ct */

Definition at line 28 of file bfi_reg.h.

#define HOSTFN2_LPU0_CMD_STAT   0x00019150 /* ct */

Definition at line 117 of file bfi_reg.h.

#define HOSTFN2_LPU1_CMD_STAT   0x00019154 /* ct */

Definition at line 118 of file bfi_reg.h.

#define HOSTFN2_LPU_MBOX0_0   0x00019400 /* ct */

Definition at line 150 of file bfi_reg.h.

#define HOSTFN3_INT_MSK   0x00014404 /* ct */

Definition at line 33 of file bfi_reg.h.

#define HOSTFN3_INT_STATUS   0x00014400 /* ct */

Definition at line 29 of file bfi_reg.h.

#define HOSTFN3_LPU0_CMD_STAT   0x00019160 /* ct */

Definition at line 119 of file bfi_reg.h.

#define HOSTFN3_LPU1_CMD_STAT   0x00019164 /* ct */

Definition at line 120 of file bfi_reg.h.

#define HOSTFN3_LPU_MBOX0_8   0x00019460 /* ct */

Definition at line 151 of file bfi_reg.h.

#define LPU0_HOSTFN0_CMD_STAT   0x00019008 /* cb/ct */

Definition at line 121 of file bfi_reg.h.

#define LPU0_HOSTFN1_CMD_STAT   0x00019018 /* cb/ct */

Definition at line 123 of file bfi_reg.h.

#define LPU0_HOSTFN2_CMD_STAT   0x00019158 /* ct */

Definition at line 125 of file bfi_reg.h.

#define LPU0_HOSTFN3_CMD_STAT   0x00019168 /* ct */

Definition at line 127 of file bfi_reg.h.

#define LPU1_HOSTFN0_CMD_STAT   0x0001900c /* cb/ct */

Definition at line 122 of file bfi_reg.h.

#define LPU1_HOSTFN1_CMD_STAT   0x0001901c /* cb/ct */

Definition at line 124 of file bfi_reg.h.

#define LPU1_HOSTFN2_CMD_STAT   0x0001915c /* ct */

Definition at line 126 of file bfi_reg.h.

#define LPU1_HOSTFN3_CMD_STAT   0x0001916c /* ct */

Definition at line 128 of file bfi_reg.h.

#define LPU_HOSTFN0_MBOX0_0   0x00019280 /* cb/ct */

Definition at line 148 of file bfi_reg.h.

#define LPU_HOSTFN1_MBOX0_8   0x000192e0 /* cb/ct */

Definition at line 149 of file bfi_reg.h.

#define LPU_HOSTFN2_MBOX0_0   0x00019480 /* ct */

Definition at line 152 of file bfi_reg.h.

#define LPU_HOSTFN3_MBOX0_8   0x000194e0 /* ct */

Definition at line 153 of file bfi_reg.h.

#define MBIST_CTL_REG   0x00014220 /* ct */

Definition at line 160 of file bfi_reg.h.

#define MBIST_STAT_REG   0x00014224 /* ct */

Definition at line 162 of file bfi_reg.h.

#define OP_MODE   0x0001460c

Definition at line 213 of file bfi_reg.h.

#define PMM_1T_RESET_REG_P0   0x0002381c

Definition at line 220 of file bfi_reg.h.

#define PMM_1T_RESET_REG_P1   0x00023c1c

Definition at line 222 of file bfi_reg.h.

#define PSS_CTL_REG   0x00018800 /* cb/ct */

Definition at line 130 of file bfi_reg.h.

#define PSS_ERR_STATUS_REG   0x00018810 /* cb/ct */

Definition at line 139 of file bfi_reg.h.

#define PSS_GPIO_OE_REG   0x000188c8 /* cb/ct */

Definition at line 143 of file bfi_reg.h.

#define PSS_GPIO_OUT_REG   0x000188c0 /* cb/ct */

Definition at line 141 of file bfi_reg.h.

#define PSS_SMEM_PAGE_START   0x8000

Definition at line 452 of file bfi_reg.h.

#define PSS_SMEM_PGNUM (   _pg0,
  _ma 
)    ((_pg0) + ((_ma) >> 15))

Definition at line 453 of file bfi_reg.h.

#define PSS_SMEM_PGOFF (   _ma)    ((_ma) & 0x7fff)

Definition at line 454 of file bfi_reg.h.

#define RME_Q_NUM (   __fn,
  __q 
)    (((__fn) << 2) + (__q))

Definition at line 379 of file bfi_reg.h.

Enumeration Type Documentation

anonymous enum
Enumerator:
__F0_INTX_STATUS_MSIX 
__F0_INTX_STATUS_INTA 
__F0_INTX_STATUS_INTB 
__F0_INTX_STATUS_INTC 
__F0_INTX_STATUS_INTD 

Definition at line 205 of file bfi_reg.h.

anonymous enum
Enumerator:
__APP_PLL_LCLK_FBCNT_425_MHZ 
__APP_PLL_LCLK_FBCNT_468_MHZ 

Definition at line 304 of file bfi_reg.h.

anonymous enum
Enumerator:
__APP_PLL_SCLK_FBCNT_NORM 
__APP_PLL_SCLK_FBCNT_10G_FC 

Definition at line 319 of file bfi_reg.h.