|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Enumerations | |
| enum | { __F0_INTX_STATUS_MSIX = 0x0, __F0_INTX_STATUS_INTA = 0x1, __F0_INTX_STATUS_INTB = 0x2, __F0_INTX_STATUS_INTC = 0x3, __F0_INTX_STATUS_INTD = 0x4 } |
| enum | { __APP_PLL_LCLK_FBCNT_425_MHZ = 6, __APP_PLL_LCLK_FBCNT_468_MHZ = 4 } |
| enum | { __APP_PLL_SCLK_FBCNT_NORM = 6, __APP_PLL_SCLK_FBCNT_10G_FC = 10 } |
| #define __APP_PLL_LCLK_CNTLMT0_1 | ( | _v | ) | ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH) |
| #define __APP_PLL_LCLK_FBCNT | ( | _v | ) | ((_v) << __APP_PLL_SCLK_FBCNT_SH) |
| #define __APP_PLL_LCLK_JITLMT0_1 | ( | _v | ) | ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH) |
| #define __APP_PLL_LCLK_P0_1 | ( | _v | ) | ((_v) << __APP_PLL_LCLK_P0_1_SH) |
| #define __APP_PLL_LCLK_RESET_TIMER | ( | _v | ) | ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH) |
| #define __APP_PLL_LCLK_Z0_2 | ( | _v | ) | ((_v) << __APP_PLL_LCLK_Z0_2_SH) |
| #define __APP_PLL_SCLK_CNTLMT0_1 | ( | _v | ) | ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH) |
| #define __APP_PLL_SCLK_FBCNT | ( | _v | ) | ((_v) << __APP_PLL_SCLK_FBCNT_SH) |
| #define __APP_PLL_SCLK_JITLMT0_1 | ( | _v | ) | ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH) |
| #define __APP_PLL_SCLK_P0_1 | ( | _v | ) | ((_v) << __APP_PLL_SCLK_P0_1_SH) |
| #define __APP_PLL_SCLK_RESET_TIMER | ( | _v | ) | ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH) |
| #define __APP_PLL_SCLK_Z0_2 | ( | _v | ) | ((_v) << __APP_PLL_SCLK_Z0_2_SH) |
| #define __F0_PORT_MAP | ( | _v | ) | ((_v) << __F0_PORT_MAP_SH) |
| #define __F1_INTX_STATUS | ( | _v | ) | ((_v) << __F1_INTX_STATUS_SH) |
| #define __F1_PORT_MAP | ( | _v | ) | ((_v) << __F1_PORT_MAP_SH) |
| #define __F2_INTX_STATUS | ( | _v | ) | ((_v) << __F2_INTX_STATUS_SH) |
| #define __F2_PORT_MAP | ( | _v | ) | ((_v) << __F2_PORT_MAP_SH) |
| #define __F3_INTX_STATUS | ( | _v | ) | ((_v) << __F3_INTX_STATUS_SH) |
| #define __F3_PORT_MAP | ( | _v | ) | ((_v) << __F3_PORT_MAP_SH) |
| #define __FC_LL_PORT_MAP_ | ( | _v | ) | ((_v) << __FC_LL_PORT_MAP__SH) |
| #define __HFN_INT_ERR_MASK |
| #define __HFN_INT_ERR_MASK_CT2 |
| #define __HFN_INT_FN0_MASK |
| #define __HFN_INT_FN0_MASK_CT2 |
| #define __HFN_INT_FN1_MASK |
| #define __HFN_INT_FN1_MASK_CT2 |
| #define __PF_EXROM_OFFSET_ | ( | _v | ) | ((_v) << __PF_EXROM_OFFSET__SH) |
| #define __PF_NUM_QUEUES1_ | ( | _v | ) | ((_v) << __PF_NUM_QUEUES1__SH) |
| #define __PF_VF_BAR_SIZE_MODE_ | ( | _v | ) | ((_v) << __PF_VF_BAR_SIZE_MODE__SH) |
| #define __PF_VF_NUM_QUEUES_ | ( | _v | ) | ((_v) << __PF_VF_NUM_QUEUES__SH) |
| #define __PF_VF_QUE_OFFSET1_ | ( | _v | ) | ((_v) << __PF_VF_QUE_OFFSET1__SH) |
| #define __PSS_I2C_CLK_DIV | ( | _v | ) | ((_v) << __PSS_I2C_CLK_DIV_SH) |
| #define BFA_FW_USE_COUNT HOST_SEM4_INFO_REG |
| #define BFA_IOC0_HBEAT_REG HOST_SEM0_INFO_REG |
| #define BFA_IOC0_STATE_REG HOST_SEM1_INFO_REG |
| #define BFA_IOC1_HBEAT_REG HOST_SEM2_INFO_REG |
| #define BFA_IOC1_STATE_REG HOST_SEM3_INFO_REG |
| #define BFA_IOC_FAIL_SYNC HOST_SEM5_INFO_REG |
| #define CT2_BFA_FW_USE_COUNT CT2_HOST_SEM4_INFO_REG |
| #define CT2_BFA_IOC0_HBEAT_REG CT2_HOST_SEM0_INFO_REG |
| #define CT2_BFA_IOC0_STATE_REG CT2_HOST_SEM1_INFO_REG |
| #define CT2_BFA_IOC1_HBEAT_REG CT2_HOST_SEM2_INFO_REG |
| #define CT2_BFA_IOC1_STATE_REG CT2_HOST_SEM3_INFO_REG |
| #define CT2_BFA_IOC_FAIL_SYNC CT2_HOST_SEM5_INFO_REG |
| #define CT2_CSI_MAC_CONTROL_REG | ( | __n | ) |
| #define CT2_HOSTFN_INT_STATUS (CT2_PCI_APP_BASE + 0x00) |
| #define CT2_HOSTFN_INTR_MASK (CT2_PCI_APP_BASE + 0x04) |
| #define CT2_HOSTFN_LPU0_CMD_STAT (CT2_PCI_CPQ_BASE + 0x80) |
| #define CT2_HOSTFN_LPU0_MBOX0 (CT2_PCI_CPQ_BASE + 0x00) |
| #define CT2_HOSTFN_LPU0_READ_STAT (CT2_PCI_CPQ_BASE + 0x90) |
| #define CT2_HOSTFN_LPU1_CMD_STAT (CT2_PCI_CPQ_BASE + 0x84) |
| #define CT2_HOSTFN_LPU1_MBOX0 (CT2_PCI_CPQ_BASE + 0x20) |
| #define CT2_HOSTFN_LPU1_READ_STAT (CT2_PCI_CPQ_BASE + 0x94) |
| #define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR (CT2_PCI_APP_BASE + 0x38) |
| #define CT2_HOSTFN_PAGE_NUM (CT2_PCI_APP_BASE + 0x18) |
| #define CT2_HOSTFN_PERSONALITY0 (CT2_PCI_APP_BASE + 0x08) |
| #define CT2_HOSTFN_PERSONALITY1 (CT2_PCI_APP_BASE + 0x0C) |
| #define CT2_LPU0_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x88) |
| #define CT2_LPU0_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x40) |
| #define CT2_LPU0_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x98) |
| #define CT2_LPU1_HOSTFN_CMD_STAT (CT2_PCI_CPQ_BASE + 0x8c) |
| #define CT2_LPU1_HOSTFN_MBOX0 (CT2_PCI_CPQ_BASE + 0x60) |
| #define CT2_LPU1_HOSTFN_MBOX0_MSK (CT2_PCI_CPQ_BASE + 0x9C) |
| #define PSS_SMEM_PGNUM | ( | _pg0, | |
| _ma | |||
| ) | ((_pg0) + ((_ma) >> 15)) |
| anonymous enum |
| anonymous enum |
1.8.2