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ni_atmio16d.c
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1 /*
2  comedi/drivers/ni_atmio16d.c
3  Hardware driver for National Instruments AT-MIO16D board
4  Copyright (C) 2000 Chris R. Baugher <[email protected]>
5 
6  This program is free software; you can redistribute it and/or modify
7  it under the terms of the GNU General Public License as published by
8  the Free Software Foundation; either version 2 of the License, or
9  (at your option) any later version.
10 
11  This program is distributed in the hope that it will be useful,
12  but WITHOUT ANY WARRANTY; without even the implied warranty of
13  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  GNU General Public License for more details.
15 
16  You should have received a copy of the GNU General Public License
17  along with this program; if not, write to the Free Software
18  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 
20  */
21 /*
22 Driver: ni_atmio16d
23 Description: National Instruments AT-MIO-16D
24 Author: Chris R. Baugher <[email protected]>
25 Status: unknown
26 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
27 */
28 /*
29  * I must give credit here to Michal Dobes <[email protected]> who
30  * wrote the driver for Advantec's pcl812 boards. I used the interrupt
31  * handling code from his driver as an example for this one.
32  *
33  * Chris Baugher
34  * 5/1/2000
35  *
36  */
37 
38 #include <linux/interrupt.h>
39 #include "../comedidev.h"
40 
41 #include <linux/ioport.h>
42 
43 #include "comedi_fc.h"
44 #include "8255.h"
45 
46 /* Configuration and Status Registers */
47 #define COM_REG_1 0x00 /* wo 16 */
48 #define STAT_REG 0x00 /* ro 16 */
49 #define COM_REG_2 0x02 /* wo 16 */
50 /* Event Strobe Registers */
51 #define START_CONVERT_REG 0x08 /* wo 16 */
52 #define START_DAQ_REG 0x0A /* wo 16 */
53 #define AD_CLEAR_REG 0x0C /* wo 16 */
54 #define EXT_STROBE_REG 0x0E /* wo 16 */
55 /* Analog Output Registers */
56 #define DAC0_REG 0x10 /* wo 16 */
57 #define DAC1_REG 0x12 /* wo 16 */
58 #define INT2CLR_REG 0x14 /* wo 16 */
59 /* Analog Input Registers */
60 #define MUX_CNTR_REG 0x04 /* wo 16 */
61 #define MUX_GAIN_REG 0x06 /* wo 16 */
62 #define AD_FIFO_REG 0x16 /* ro 16 */
63 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
64 /* AM9513A Counter/Timer Registers */
65 #define AM9513A_DATA_REG 0x18 /* rw 16 */
66 #define AM9513A_COM_REG 0x1A /* wo 16 */
67 #define AM9513A_STAT_REG 0x1A /* ro 16 */
68 /* MIO-16 Digital I/O Registers */
69 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
70 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
71 /* RTSI Switch Registers */
72 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
73 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
74 /* DIO-24 Registers */
75 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
76 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
77 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
78 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
79 
80 /* Command Register bits */
81 #define COMREG1_2SCADC 0x0001
82 #define COMREG1_1632CNT 0x0002
83 #define COMREG1_SCANEN 0x0008
84 #define COMREG1_DAQEN 0x0010
85 #define COMREG1_DMAEN 0x0020
86 #define COMREG1_CONVINTEN 0x0080
87 #define COMREG2_SCN2 0x0010
88 #define COMREG2_INTEN 0x0080
89 #define COMREG2_DOUTEN0 0x0100
90 #define COMREG2_DOUTEN1 0x0200
91 /* Status Register bits */
92 #define STAT_AD_OVERRUN 0x0100
93 #define STAT_AD_OVERFLOW 0x0200
94 #define STAT_AD_DAQPROG 0x0800
95 #define STAT_AD_CONVAVAIL 0x2000
96 #define STAT_AD_DAQSTOPINT 0x4000
97 /* AM9513A Counter/Timer defines */
98 #define CLOCK_1_MHZ 0x8B25
99 #define CLOCK_100_KHZ 0x8C25
100 #define CLOCK_10_KHZ 0x8D25
101 #define CLOCK_1_KHZ 0x8E25
102 #define CLOCK_100_HZ 0x8F25
103 /* Other miscellaneous defines */
104 #define ATMIO16D_SIZE 32 /* bus address range */
105 #define devpriv ((struct atmio16d_private *)dev->private)
106 #define ATMIO16D_TIMEOUT 10
107 
108 struct atmio16_board_t {
109 
110  const char *name;
111  int has_8255;
112 };
113 
114 /* range structs */
115 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
116  BIP_RANGE
117  (10),
118  BIP_RANGE
119  (1),
120  BIP_RANGE
121  (0.1),
122  BIP_RANGE
123  (0.02)
124  }
125 };
126 
127 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
128  BIP_RANGE
129  (5),
130  BIP_RANGE
131  (0.5),
132  BIP_RANGE
133  (0.05),
134  BIP_RANGE
135  (0.01)
136  }
137 };
138 
139 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
140  UNI_RANGE
141  (10),
142  UNI_RANGE
143  (1),
144  UNI_RANGE
145  (0.1),
146  UNI_RANGE
147  (0.02)
148  }
149 };
150 
151 /* private data struct */
152 struct atmio16d_private {
153  enum { adc_diff, adc_singleended } adc_mux;
154  enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
155  enum { adc_2comp, adc_straight } adc_coding;
156  enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
157  enum { dac_internal, dac_external } dac0_reference, dac1_reference;
158  enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
159  const struct comedi_lrange *ao_range_type_list[2];
160  unsigned int ao_readback[2];
161  unsigned int com_reg_1_state; /* current state of command register 1 */
162  unsigned int com_reg_2_state; /* current state of command register 2 */
163 };
164 
165 static void reset_counters(struct comedi_device *dev)
166 {
167  /* Counter 2 */
168  outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
169  outw(0xFF02, dev->iobase + AM9513A_COM_REG);
170  outw(0x4, dev->iobase + AM9513A_DATA_REG);
171  outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
172  outw(0x3, dev->iobase + AM9513A_DATA_REG);
173  outw(0xFF42, dev->iobase + AM9513A_COM_REG);
174  outw(0xFF42, dev->iobase + AM9513A_COM_REG);
175  /* Counter 3 */
176  outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
177  outw(0xFF03, dev->iobase + AM9513A_COM_REG);
178  outw(0x4, dev->iobase + AM9513A_DATA_REG);
179  outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
180  outw(0x3, dev->iobase + AM9513A_DATA_REG);
181  outw(0xFF44, dev->iobase + AM9513A_COM_REG);
182  outw(0xFF44, dev->iobase + AM9513A_COM_REG);
183  /* Counter 4 */
184  outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
185  outw(0xFF04, dev->iobase + AM9513A_COM_REG);
186  outw(0x4, dev->iobase + AM9513A_DATA_REG);
187  outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
188  outw(0x3, dev->iobase + AM9513A_DATA_REG);
189  outw(0xFF48, dev->iobase + AM9513A_COM_REG);
190  outw(0xFF48, dev->iobase + AM9513A_COM_REG);
191  /* Counter 5 */
192  outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
193  outw(0xFF05, dev->iobase + AM9513A_COM_REG);
194  outw(0x4, dev->iobase + AM9513A_DATA_REG);
195  outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
196  outw(0x3, dev->iobase + AM9513A_DATA_REG);
197  outw(0xFF50, dev->iobase + AM9513A_COM_REG);
198  outw(0xFF50, dev->iobase + AM9513A_COM_REG);
199 
200  outw(0, dev->iobase + AD_CLEAR_REG);
201 }
202 
203 static void reset_atmio16d(struct comedi_device *dev)
204 {
205  int i;
206 
207  /* now we need to initialize the board */
208  outw(0, dev->iobase + COM_REG_1);
209  outw(0, dev->iobase + COM_REG_2);
210  outw(0, dev->iobase + MUX_GAIN_REG);
211  /* init AM9513A timer */
212  outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
213  outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
214  outw(0xFF17, dev->iobase + AM9513A_COM_REG);
215  outw(0xF000, dev->iobase + AM9513A_DATA_REG);
216  for (i = 1; i <= 5; ++i) {
217  outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
218  outw(0x0004, dev->iobase + AM9513A_DATA_REG);
219  outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
220  outw(0x3, dev->iobase + AM9513A_DATA_REG);
221  }
222  outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
223  /* timer init done */
224  outw(0, dev->iobase + AD_CLEAR_REG);
225  outw(0, dev->iobase + INT2CLR_REG);
226  /* select straight binary mode for Analog Input */
227  devpriv->com_reg_1_state |= 1;
228  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
229  devpriv->adc_coding = adc_straight;
230  /* zero the analog outputs */
231  outw(2048, dev->iobase + DAC0_REG);
232  outw(2048, dev->iobase + DAC1_REG);
233 }
234 
235 static irqreturn_t atmio16d_interrupt(int irq, void *d)
236 {
237  struct comedi_device *dev = d;
238  struct comedi_subdevice *s = &dev->subdevices[0];
239 
240  comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
241 
242  comedi_event(dev, s);
243  return IRQ_HANDLED;
244 }
245 
246 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
247  struct comedi_subdevice *s,
248  struct comedi_cmd *cmd)
249 {
250  int err = 0;
251 
252  /* Step 1 : check if triggers are trivially valid */
253 
254  err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
255  err |= cfc_check_trigger_src(&cmd->scan_begin_src,
256  TRIG_FOLLOW | TRIG_TIMER);
257  err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
258  err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
259  err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
260 
261  if (err)
262  return 1;
263 
264  /* Step 2a : make sure trigger sources are unique */
265 
266  err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
267  err |= cfc_check_trigger_is_unique(cmd->stop_src);
268 
269  /* Step 2b : and mutually compatible */
270 
271  if (err)
272  return 2;
273 
274  /* step 3: make sure arguments are trivially compatible */
275 
276  if (cmd->start_arg != 0) {
277  cmd->start_arg = 0;
278  err++;
279  }
280  if (cmd->scan_begin_src == TRIG_FOLLOW) {
281  /* internal trigger */
282  if (cmd->scan_begin_arg != 0) {
283  cmd->scan_begin_arg = 0;
284  err++;
285  }
286  } else {
287 #if 0
288  /* external trigger */
289  /* should be level/edge, hi/lo specification here */
290  if (cmd->scan_begin_arg != 0) {
291  cmd->scan_begin_arg = 0;
292  err++;
293  }
294 #endif
295  }
296 
297  if (cmd->convert_arg < 10000) {
298  cmd->convert_arg = 10000;
299  err++;
300  }
301 #if 0
302  if (cmd->convert_arg > SLOWEST_TIMER) {
303  cmd->convert_arg = SLOWEST_TIMER;
304  err++;
305  }
306 #endif
307  if (cmd->scan_end_arg != cmd->chanlist_len) {
308  cmd->scan_end_arg = cmd->chanlist_len;
309  err++;
310  }
311  if (cmd->stop_src == TRIG_COUNT) {
312  /* any count is allowed */
313  } else {
314  /* TRIG_NONE */
315  if (cmd->stop_arg != 0) {
316  cmd->stop_arg = 0;
317  err++;
318  }
319  }
320 
321  if (err)
322  return 3;
323 
324  return 0;
325 }
326 
327 static int atmio16d_ai_cmd(struct comedi_device *dev,
328  struct comedi_subdevice *s)
329 {
330  struct comedi_cmd *cmd = &s->async->cmd;
331  unsigned int timer, base_clock;
332  unsigned int sample_count, tmp, chan, gain;
333  int i;
334 
335  /* This is slowly becoming a working command interface. *
336  * It is still uber-experimental */
337 
338  reset_counters(dev);
339  s->async->cur_chan = 0;
340 
341  /* check if scanning multiple channels */
342  if (cmd->chanlist_len < 2) {
343  devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
344  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
345  } else {
346  devpriv->com_reg_1_state |= COMREG1_SCANEN;
347  devpriv->com_reg_2_state |= COMREG2_SCN2;
348  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
349  outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
350  }
351 
352  /* Setup the Mux-Gain Counter */
353  for (i = 0; i < cmd->chanlist_len; ++i) {
354  chan = CR_CHAN(cmd->chanlist[i]);
355  gain = CR_RANGE(cmd->chanlist[i]);
356  outw(i, dev->iobase + MUX_CNTR_REG);
357  tmp = chan | (gain << 6);
358  if (i == cmd->scan_end_arg - 1)
359  tmp |= 0x0010; /* set LASTONE bit */
360  outw(tmp, dev->iobase + MUX_GAIN_REG);
361  }
362 
363  /* Now program the sample interval timer */
364  /* Figure out which clock to use then get an
365  * appropriate timer value */
366  if (cmd->convert_arg < 65536000) {
367  base_clock = CLOCK_1_MHZ;
368  timer = cmd->convert_arg / 1000;
369  } else if (cmd->convert_arg < 655360000) {
370  base_clock = CLOCK_100_KHZ;
371  timer = cmd->convert_arg / 10000;
372  } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
373  base_clock = CLOCK_10_KHZ;
374  timer = cmd->convert_arg / 100000;
375  } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
376  base_clock = CLOCK_1_KHZ;
377  timer = cmd->convert_arg / 1000000;
378  }
379  outw(0xFF03, dev->iobase + AM9513A_COM_REG);
380  outw(base_clock, dev->iobase + AM9513A_DATA_REG);
381  outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
382  outw(0x2, dev->iobase + AM9513A_DATA_REG);
383  outw(0xFF44, dev->iobase + AM9513A_COM_REG);
384  outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
385  outw(timer, dev->iobase + AM9513A_DATA_REG);
386  outw(0xFF24, dev->iobase + AM9513A_COM_REG);
387 
388  /* Now figure out how many samples to get */
389  /* and program the sample counter */
390  sample_count = cmd->stop_arg * cmd->scan_end_arg;
391  outw(0xFF04, dev->iobase + AM9513A_COM_REG);
392  outw(0x1025, dev->iobase + AM9513A_DATA_REG);
393  outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
394  if (sample_count < 65536) {
395  /* use only Counter 4 */
396  outw(sample_count, dev->iobase + AM9513A_DATA_REG);
397  outw(0xFF48, dev->iobase + AM9513A_COM_REG);
398  outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
399  outw(0xFF28, dev->iobase + AM9513A_COM_REG);
400  devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
401  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
402  } else {
403  /* Counter 4 and 5 are needed */
404 
405  tmp = sample_count & 0xFFFF;
406  if (tmp)
407  outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
408  else
409  outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
410 
411  outw(0xFF48, dev->iobase + AM9513A_COM_REG);
412  outw(0, dev->iobase + AM9513A_DATA_REG);
413  outw(0xFF28, dev->iobase + AM9513A_COM_REG);
414  outw(0xFF05, dev->iobase + AM9513A_COM_REG);
415  outw(0x25, dev->iobase + AM9513A_DATA_REG);
416  outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
417  tmp = sample_count & 0xFFFF;
418  if ((tmp == 0) || (tmp == 1)) {
419  outw((sample_count >> 16) & 0xFFFF,
420  dev->iobase + AM9513A_DATA_REG);
421  } else {
422  outw(((sample_count >> 16) & 0xFFFF) + 1,
423  dev->iobase + AM9513A_DATA_REG);
424  }
425  outw(0xFF70, dev->iobase + AM9513A_COM_REG);
426  devpriv->com_reg_1_state |= COMREG1_1632CNT;
427  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
428  }
429 
430  /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
431  /* Figure out which clock to use then get an
432  * appropriate timer value */
433  if (cmd->chanlist_len > 1) {
434  if (cmd->scan_begin_arg < 65536000) {
435  base_clock = CLOCK_1_MHZ;
436  timer = cmd->scan_begin_arg / 1000;
437  } else if (cmd->scan_begin_arg < 655360000) {
438  base_clock = CLOCK_100_KHZ;
439  timer = cmd->scan_begin_arg / 10000;
440  } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
441  base_clock = CLOCK_10_KHZ;
442  timer = cmd->scan_begin_arg / 100000;
443  } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
444  base_clock = CLOCK_1_KHZ;
445  timer = cmd->scan_begin_arg / 1000000;
446  }
447  outw(0xFF02, dev->iobase + AM9513A_COM_REG);
448  outw(base_clock, dev->iobase + AM9513A_DATA_REG);
449  outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
450  outw(0x2, dev->iobase + AM9513A_DATA_REG);
451  outw(0xFF42, dev->iobase + AM9513A_COM_REG);
452  outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
453  outw(timer, dev->iobase + AM9513A_DATA_REG);
454  outw(0xFF22, dev->iobase + AM9513A_COM_REG);
455  }
456 
457  /* Clear the A/D FIFO and reset the MUX counter */
458  outw(0, dev->iobase + AD_CLEAR_REG);
459  outw(0, dev->iobase + MUX_CNTR_REG);
460  outw(0, dev->iobase + INT2CLR_REG);
461  /* enable this acquisition operation */
462  devpriv->com_reg_1_state |= COMREG1_DAQEN;
463  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
464  /* enable interrupts for conversion completion */
465  devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
466  devpriv->com_reg_2_state |= COMREG2_INTEN;
467  outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
468  outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
469  /* apply a trigger. this starts the counters! */
470  outw(0, dev->iobase + START_DAQ_REG);
471 
472  return 0;
473 }
474 
475 /* This will cancel a running acquisition operation */
476 static int atmio16d_ai_cancel(struct comedi_device *dev,
477  struct comedi_subdevice *s)
478 {
479  reset_atmio16d(dev);
480 
481  return 0;
482 }
483 
484 /* Mode 0 is used to get a single conversion on demand */
485 static int atmio16d_ai_insn_read(struct comedi_device *dev,
486  struct comedi_subdevice *s,
487  struct comedi_insn *insn, unsigned int *data)
488 {
489  int i, t;
490  int chan;
491  int gain;
492  int status;
493 
494  chan = CR_CHAN(insn->chanspec);
495  gain = CR_RANGE(insn->chanspec);
496 
497  /* reset the Analog input circuitry */
498  /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
499  /* reset the Analog Input MUX Counter to 0 */
500  /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
501 
502  /* set the Input MUX gain */
503  outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
504 
505  for (i = 0; i < insn->n; i++) {
506  /* start the conversion */
507  outw(0, dev->iobase + START_CONVERT_REG);
508  /* wait for it to finish */
509  for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
510  /* check conversion status */
511  status = inw(dev->iobase + STAT_REG);
512  if (status & STAT_AD_CONVAVAIL) {
513  /* read the data now */
514  data[i] = inw(dev->iobase + AD_FIFO_REG);
515  /* change to two's complement if need be */
516  if (devpriv->adc_coding == adc_2comp)
517  data[i] ^= 0x800;
518  break;
519  }
520  if (status & STAT_AD_OVERFLOW) {
521  printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
522  outw(0, dev->iobase + AD_CLEAR_REG);
523 
524  return -ETIME;
525  }
526  }
527  /* end waiting, now check if it timed out */
528  if (t == ATMIO16D_TIMEOUT) {
529  printk(KERN_INFO "atmio16d: timeout\n");
530 
531  return -ETIME;
532  }
533  }
534 
535  return i;
536 }
537 
538 static int atmio16d_ao_insn_read(struct comedi_device *dev,
539  struct comedi_subdevice *s,
540  struct comedi_insn *insn, unsigned int *data)
541 {
542  int i;
543 
544  for (i = 0; i < insn->n; i++)
545  data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
546  return i;
547 }
548 
549 static int atmio16d_ao_insn_write(struct comedi_device *dev,
550  struct comedi_subdevice *s,
551  struct comedi_insn *insn, unsigned int *data)
552 {
553  int i;
554  int chan;
555  int d;
556 
557  chan = CR_CHAN(insn->chanspec);
558 
559  for (i = 0; i < insn->n; i++) {
560  d = data[i];
561  switch (chan) {
562  case 0:
563  if (devpriv->dac0_coding == dac_2comp)
564  d ^= 0x800;
565  outw(d, dev->iobase + DAC0_REG);
566  break;
567  case 1:
568  if (devpriv->dac1_coding == dac_2comp)
569  d ^= 0x800;
570  outw(d, dev->iobase + DAC1_REG);
571  break;
572  default:
573  return -EINVAL;
574  }
575  devpriv->ao_readback[chan] = data[i];
576  }
577  return i;
578 }
579 
580 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
581  struct comedi_subdevice *s,
582  struct comedi_insn *insn, unsigned int *data)
583 {
584  if (data[0]) {
585  s->state &= ~data[0];
586  s->state |= (data[0] | data[1]);
587  outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
588  }
589  data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
590 
591  return insn->n;
592 }
593 
594 static int atmio16d_dio_insn_config(struct comedi_device *dev,
595  struct comedi_subdevice *s,
596  struct comedi_insn *insn,
597  unsigned int *data)
598 {
599  int i;
600  int mask;
601 
602  for (i = 0; i < insn->n; i++) {
603  mask = (CR_CHAN(insn->chanspec) < 4) ? 0x0f : 0xf0;
604  s->io_bits &= ~mask;
605  if (data[i])
606  s->io_bits |= mask;
607  }
608  devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
609  if (s->io_bits & 0x0f)
610  devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
611  if (s->io_bits & 0xf0)
612  devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
613  outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
614 
615  return i;
616 }
617 
618 /*
619  options[0] - I/O port
620  options[1] - MIO irq
621  0 == no irq
622  N == irq N {3,4,5,6,7,9,10,11,12,14,15}
623  options[2] - DIO irq
624  0 == no irq
625  N == irq N {3,4,5,6,7,9}
626  options[3] - DMA1 channel
627  0 == no DMA
628  N == DMA N {5,6,7}
629  options[4] - DMA2 channel
630  0 == no DMA
631  N == DMA N {5,6,7}
632 
633  options[5] - a/d mux
634  0=differential, 1=single
635  options[6] - a/d range
636  0=bipolar10, 1=bipolar5, 2=unipolar10
637 
638  options[7] - dac0 range
639  0=bipolar, 1=unipolar
640  options[8] - dac0 reference
641  0=internal, 1=external
642  options[9] - dac0 coding
643  0=2's comp, 1=straight binary
644 
645  options[10] - dac1 range
646  options[11] - dac1 reference
647  options[12] - dac1 coding
648  */
649 
650 static int atmio16d_attach(struct comedi_device *dev,
651  struct comedi_devconfig *it)
652 {
653  const struct atmio16_board_t *board = comedi_board(dev);
654  unsigned int irq;
655  unsigned long iobase;
656  int ret;
657 
658  struct comedi_subdevice *s;
659 
660  /* make sure the address range is free and allocate it */
661  iobase = it->options[0];
662  printk(KERN_INFO "comedi%d: atmio16d: 0x%04lx ", dev->minor, iobase);
663  if (!request_region(iobase, ATMIO16D_SIZE, "ni_atmio16d")) {
664  printk("I/O port conflict\n");
665  return -EIO;
666  }
667  dev->iobase = iobase;
668 
669  dev->board_name = board->name;
670 
671  ret = comedi_alloc_subdevices(dev, 4);
672  if (ret)
673  return ret;
674 
675  ret = alloc_private(dev, sizeof(struct atmio16d_private));
676  if (ret < 0)
677  return ret;
678 
679  /* reset the atmio16d hardware */
680  reset_atmio16d(dev);
681 
682  /* check if our interrupt is available and get it */
683  irq = it->options[1];
684  if (irq) {
685 
686  ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
687  if (ret < 0) {
688  printk(KERN_INFO "failed to allocate irq %u\n", irq);
689  return ret;
690  }
691  dev->irq = irq;
692  printk(KERN_INFO "( irq = %u )\n", irq);
693  } else {
694  printk(KERN_INFO "( no irq )");
695  }
696 
697  /* set device options */
698  devpriv->adc_mux = it->options[5];
699  devpriv->adc_range = it->options[6];
700 
701  devpriv->dac0_range = it->options[7];
702  devpriv->dac0_reference = it->options[8];
703  devpriv->dac0_coding = it->options[9];
704  devpriv->dac1_range = it->options[10];
705  devpriv->dac1_reference = it->options[11];
706  devpriv->dac1_coding = it->options[12];
707 
708  /* setup sub-devices */
709  s = &dev->subdevices[0];
710  dev->read_subdev = s;
711  /* ai subdevice */
712  s->type = COMEDI_SUBD_AI;
713  s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
714  s->n_chan = (devpriv->adc_mux ? 16 : 8);
715  s->len_chanlist = 16;
716  s->insn_read = atmio16d_ai_insn_read;
717  s->do_cmdtest = atmio16d_ai_cmdtest;
718  s->do_cmd = atmio16d_ai_cmd;
719  s->cancel = atmio16d_ai_cancel;
720  s->maxdata = 0xfff; /* 4095 decimal */
721  switch (devpriv->adc_range) {
722  case adc_bipolar10:
723  s->range_table = &range_atmio16d_ai_10_bipolar;
724  break;
725  case adc_bipolar5:
726  s->range_table = &range_atmio16d_ai_5_bipolar;
727  break;
728  case adc_unipolar10:
729  s->range_table = &range_atmio16d_ai_unipolar;
730  break;
731  }
732 
733  /* ao subdevice */
734  s = &dev->subdevices[1];
735  s->type = COMEDI_SUBD_AO;
736  s->subdev_flags = SDF_WRITABLE;
737  s->n_chan = 2;
738  s->insn_read = atmio16d_ao_insn_read;
739  s->insn_write = atmio16d_ao_insn_write;
740  s->maxdata = 0xfff; /* 4095 decimal */
741  s->range_table_list = devpriv->ao_range_type_list;
742  switch (devpriv->dac0_range) {
743  case dac_bipolar:
744  devpriv->ao_range_type_list[0] = &range_bipolar10;
745  break;
746  case dac_unipolar:
747  devpriv->ao_range_type_list[0] = &range_unipolar10;
748  break;
749  }
750  switch (devpriv->dac1_range) {
751  case dac_bipolar:
752  devpriv->ao_range_type_list[1] = &range_bipolar10;
753  break;
754  case dac_unipolar:
755  devpriv->ao_range_type_list[1] = &range_unipolar10;
756  break;
757  }
758 
759  /* Digital I/O */
760  s = &dev->subdevices[2];
761  s->type = COMEDI_SUBD_DIO;
762  s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
763  s->n_chan = 8;
764  s->insn_bits = atmio16d_dio_insn_bits;
765  s->insn_config = atmio16d_dio_insn_config;
766  s->maxdata = 1;
767  s->range_table = &range_digital;
768 
769  /* 8255 subdevice */
770  s = &dev->subdevices[3];
771  if (board->has_8255)
772  subdev_8255_init(dev, s, NULL, dev->iobase);
773  else
774  s->type = COMEDI_SUBD_UNUSED;
775 
776 /* don't yet know how to deal with counter/timers */
777 #if 0
778  s = &dev->subdevices[4];
779  /* do */
780  s->type = COMEDI_SUBD_TIMER;
781  s->n_chan = 0;
782  s->maxdata = 0
783 #endif
784  printk("\n");
785 
786  return 0;
787 }
788 
789 static void atmio16d_detach(struct comedi_device *dev)
790 {
791  const struct atmio16_board_t *board = comedi_board(dev);
792  struct comedi_subdevice *s;
793 
794  if (dev->subdevices && board->has_8255) {
795  s = &dev->subdevices[3];
796  subdev_8255_cleanup(dev, s);
797  }
798  if (dev->irq)
799  free_irq(dev->irq, dev);
800  reset_atmio16d(dev);
801  if (dev->iobase)
802  release_region(dev->iobase, ATMIO16D_SIZE);
803 }
804 
805 static const struct atmio16_board_t atmio16_boards[] = {
806  {
807  .name = "atmio16",
808  .has_8255 = 0,
809  }, {
810  .name = "atmio16d",
811  .has_8255 = 1,
812  },
813 };
814 
815 static struct comedi_driver atmio16d_driver = {
816  .driver_name = "atmio16",
817  .module = THIS_MODULE,
818  .attach = atmio16d_attach,
819  .detach = atmio16d_detach,
820  .board_name = &atmio16_boards[0].name,
821  .num_names = ARRAY_SIZE(atmio16_boards),
822  .offset = sizeof(struct atmio16_board_t),
823 };
824 module_comedi_driver(atmio16d_driver);
825 
826 MODULE_AUTHOR("Comedi http://www.comedi.org");
827 MODULE_DESCRIPTION("Comedi low-level driver");
828 MODULE_LICENSE("GPL");
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