52 crtcstate->
CRTC[index]);
55 static void nv_crtc_set_digital_vibrance(
struct drm_crtc *crtc,
int level)
70 static void nv_crtc_set_image_sharpening(
struct drm_crtc *crtc,
int level)
83 #define PLLSEL_VPLL1_MASK \
84 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
85 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
86 #define PLLSEL_VPLL2_MASK \
87 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
88 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
89 #define PLLSEL_TV_MASK \
90 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
91 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
92 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
93 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
138 if (nv_device(drm->
device)->chipset > 0x40 && dot_clock <= (pll_lim.
vco1.max_freq / 2))
142 if (!clk->
pll_calc(clk, &pll_lim, dot_clock, pv))
148 if (nv_device(drm->
device)->card_type == NV_40)
151 if (nv_device(drm->
device)->chipset < 0x41)
157 NV_DEBUG(drm,
"vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
160 NV_DEBUG(drm,
"vpll: n %d m %d log2p %d\n",
163 nv_crtc->
cursor.set_offset(nv_crtc, nv_crtc->
cursor.offset);
172 unsigned char seq1 = 0, crtc17 = 0;
173 unsigned char crtc1A;
175 NV_DEBUG(drm,
"Setting dpms mode %d on CRTC %d\n", mode,
183 if (nv_two_heads(dev))
187 crtc1A = NVReadVgaCrtc(dev, nv_crtc->
index,
216 NVVgaSeqReset(dev, nv_crtc->
index,
true);
223 NVVgaSeqReset(dev, nv_crtc->
index,
false);
258 bool fp_output =
false;
263 if (encoder->
crtc == crtc &&
270 vertStart = vertTotal - 3;
271 vertEnd = vertTotal - 2;
272 vertBlankStart = vertStart;
273 horizStart = horizTotal - 5;
274 horizEnd = horizTotal - 2;
275 horizBlankEnd = horizTotal + 4;
277 if (dev->overlayAdaptor && nv_device(drm->
device)->card_type >= NV_10)
287 ErrorF(
"horizDisplay: 0x%X \n", horizDisplay);
288 ErrorF(
"horizStart: 0x%X \n", horizStart);
289 ErrorF(
"horizEnd: 0x%X \n", horizEnd);
290 ErrorF(
"horizTotal: 0x%X \n", horizTotal);
291 ErrorF(
"horizBlankStart: 0x%X \n", horizBlankStart);
292 ErrorF(
"horizBlankEnd: 0x%X \n", horizBlankEnd);
293 ErrorF(
"vertDisplay: 0x%X \n", vertDisplay);
294 ErrorF(
"vertStart: 0x%X \n", vertStart);
295 ErrorF(
"vertEnd: 0x%X \n", vertEnd);
296 ErrorF(
"vertTotal: 0x%X \n", vertTotal);
297 ErrorF(
"vertBlankStart: 0x%X \n", vertBlankStart);
298 ErrorF(
"vertBlankEnd: 0x%X \n", vertBlankEnd);
317 vdisplay *= mode->
vscan;
320 else if (vdisplay < 480)
322 else if (vdisplay < 768)
410 horizTotal = (horizTotal >> 1) & ~1;
470 bool lvds_output =
false, tmds_output =
false, tv_output =
false,
471 off_chip_digital =
false;
477 if (encoder->
crtc != crtc)
481 digital = lvds_output =
true;
485 digital = tmds_output =
true;
487 off_chip_digital =
true;
498 if (nv_crtc->
index == 0)
502 if (dev->overlayAdaptor) {
503 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
504 if (pPriv->overlayCRTC == nv_crtc->
index)
513 if (nv_device(drm->
device)->chipset >= 0x11)
525 else if (tmds_output)
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->
saturation);
541 if (nv_crtc->
index == 0)
554 if (nv_device(drm->
device)->card_type >= NV_30)
555 regp->
CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
560 if (nv_device(drm->
device)->card_type == NV_40)
564 if (nv_device(drm->
device)->card_type >= NV_30)
567 if (nv_device(drm->
device)->card_type >= NV_10)
573 if (nv_device(drm->
device)->card_type == NV_40) {
580 if (lvds_output || tmds_output || tv_output)
585 if (nv_device(drm->
device)->card_type >= NV_10)
592 if (crtc->
fb->depth == 16)
594 if (nv_device(drm->
device)->chipset >= 0x11)
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->
sharpness);
630 nv_lock_vga_crtc_shadow(dev, nv_crtc->
index, -1);
632 nv_crtc_mode_set_vga(crtc, adjusted_mode);
634 if (nv_device(drm->
device)->card_type == NV_40)
636 nv_crtc_mode_set_regs(crtc, adjusted_mode);
637 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->
clock);
641 static void nv_crtc_save(
struct drm_crtc *crtc)
650 if (nv_two_heads(crtc->
dev))
662 static void nv_crtc_restore(
struct drm_crtc *crtc)
669 if (nv_two_heads(crtc->
dev))
673 nv_lock_vga_crtc_shadow(crtc->
dev, head, saved_cr21);
678 static void nv_crtc_prepare(
struct drm_crtc *crtc)
685 if (nv_two_heads(dev))
695 if (nv_device(drm->
device)->card_type == NV_40) {
701 static void nv_crtc_commit(
struct drm_crtc *crtc)
708 nv04_crtc_mode_set_base(crtc, crtc->
x, crtc->
y,
NULL);
723 static void nv_crtc_destroy(
struct drm_crtc *crtc)
738 nv_crtc_gamma_load(
struct drm_crtc *crtc)
746 for (i = 0; i < 256; i++) {
747 rgbs[
i].r = nv_crtc->
lut.r[
i] >> 8;
748 rgbs[
i].g = nv_crtc->
lut.g[
i] >> 8;
749 rgbs[
i].b = nv_crtc->
lut.b[
i] >> 8;
759 int end = (start + size > 256) ? 256 : start + size, i;
762 for (i = start; i <
end; i++) {
763 nv_crtc->
lut.r[
i] = r[
i];
764 nv_crtc->
lut.g[
i] = g[
i];
765 nv_crtc->
lut.b[
i] = b[
i];
773 if (!nv_crtc->
base.fb) {
774 nv_crtc->
lut.depth = 0;
778 nv_crtc_gamma_load(crtc);
782 nv04_crtc_do_mode_set_base(
struct drm_crtc *crtc,
784 int x,
int y,
bool atomic)
792 int arb_burst, arb_lwm;
798 if (!atomic && !crtc->
fb) {
827 nv_crtc->
fb.offset = fb->
nvbo->bo.offset;
829 if (nv_crtc->
lut.depth != drm_fb->
depth) {
831 nv_crtc_gamma_load(crtc);
838 if (crtc->
fb->depth == 16)
860 &arb_burst, &arb_lwm);
867 if (nv_device(drm->
device)->card_type >= NV_20) {
876 nv04_crtc_mode_set_base(
struct drm_crtc *crtc,
int x,
int y,
879 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y,
false);
883 nv04_crtc_mode_set_base_atomic(
struct drm_crtc *crtc,
895 return nv04_crtc_do_mode_set_base(crtc, fb, x, y,
true);
901 int width = nv_cursor_width(dev);
905 for (i = 0; i <
width; i++) {
906 for (j = 0; j <
width; j++) {
910 | (pixel & 0xf80000) >> 9
911 | (pixel & 0xf800) >> 6
912 | (pixel & 0xf8) >> 3);
929 for (i = 0; i < 64 * 64; i++) {
938 if (alpha > 0 && alpha < 255)
939 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
945 if (nv_device(drm->
device)->chipset == 0x11) {
946 pixel = ((pixel & 0x000000ff) << 24) |
947 ((pixel & 0x0000ff00) << 8) |
948 ((pixel & 0x00ff0000) >> 8) |
949 ((pixel & 0xff000000) >> 24);
959 nv04_crtc_cursor_set(
struct drm_crtc *crtc,
struct drm_file *file_priv,
966 struct drm_gem_object *
gem;
969 if (!buffer_handle) {
970 nv_crtc->
cursor.hide(nv_crtc,
true);
974 if (width != 64 || height != 64)
980 cursor = nouveau_gem_object(gem);
986 if (nv_device(drm->
device)->chipset >= 0x11)
987 nv11_cursor_upload(dev, cursor, nv_crtc->
cursor.nvbo);
989 nv04_cursor_upload(dev, cursor, nv_crtc->
cursor.nvbo);
992 nv_crtc->
cursor.offset = nv_crtc->
cursor.nvbo->bo.offset;
993 nv_crtc->
cursor.set_offset(nv_crtc, nv_crtc->
cursor.offset);
994 nv_crtc->
cursor.show(nv_crtc,
true);
996 drm_gem_object_unreference_unlocked(gem);
1001 nv04_crtc_cursor_move(
struct drm_crtc *crtc,
int x,
int y)
1005 nv_crtc->
cursor.set_pos(nv_crtc, x, y);
1010 .save = nv_crtc_save,
1011 .restore = nv_crtc_restore,
1012 .cursor_set = nv04_crtc_cursor_set,
1013 .cursor_move = nv04_crtc_cursor_move,
1014 .gamma_set = nv_crtc_gamma_set,
1017 .destroy = nv_crtc_destroy,
1021 .dpms = nv_crtc_dpms,
1022 .prepare = nv_crtc_prepare,
1023 .commit = nv_crtc_commit,
1024 .mode_fixup = nv_crtc_mode_fixup,
1025 .mode_set = nv_crtc_mode_set,
1026 .mode_set_base = nv04_crtc_mode_set_base,
1027 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
1028 .load_lut = nv_crtc_gamma_load,
1037 nv_crtc = kzalloc(
sizeof(*nv_crtc),
GFP_KERNEL);
1041 for (i = 0; i < 256; i++) {
1042 nv_crtc->
lut.r[
i] = i << 8;
1043 nv_crtc->
lut.g[
i] = i << 8;
1044 nv_crtc->
lut.b[
i] = i << 8;
1046 nv_crtc->
lut.depth = 0;
1048 nv_crtc->
index = crtc_num;
1052 drm_crtc_helper_add(&nv_crtc->
base, &nv04_crtc_helper_funcs);