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nvme.h
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1 /*
2  * Definitions for the NVM Express interface
3  * Copyright (c) 2011, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18 
19 #ifndef _LINUX_NVME_H
20 #define _LINUX_NVME_H
21 
22 #include <linux/types.h>
23 
24 struct nvme_bar {
25  __u64 cap; /* Controller Capabilities */
26  __u32 vs; /* Version */
27  __u32 intms; /* Interrupt Mask Set */
28  __u32 intmc; /* Interrupt Mask Clear */
29  __u32 cc; /* Controller Configuration */
30  __u32 rsvd1; /* Reserved */
31  __u32 csts; /* Controller Status */
32  __u32 rsvd2; /* Reserved */
33  __u32 aqa; /* Admin Queue Attributes */
34  __u64 asq; /* Admin SQ Base Address */
35  __u64 acq; /* Admin CQ Base Address */
36 };
37 
38 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
39 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
40 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
41 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
42 
43 enum {
44  NVME_CC_ENABLE = 1 << 0,
45  NVME_CC_CSS_NVM = 0 << 4,
46  NVME_CC_MPS_SHIFT = 7,
47  NVME_CC_ARB_RR = 0 << 11,
48  NVME_CC_ARB_WRRU = 1 << 11,
49  NVME_CC_ARB_VS = 7 << 11,
50  NVME_CC_SHN_NONE = 0 << 14,
51  NVME_CC_SHN_NORMAL = 1 << 14,
52  NVME_CC_SHN_ABRUPT = 2 << 14,
53  NVME_CC_IOSQES = 6 << 16,
54  NVME_CC_IOCQES = 4 << 20,
55  NVME_CSTS_RDY = 1 << 0,
56  NVME_CSTS_CFS = 1 << 1,
57  NVME_CSTS_SHST_NORMAL = 0 << 2,
58  NVME_CSTS_SHST_OCCUR = 1 << 2,
59  NVME_CSTS_SHST_CMPLT = 2 << 2,
60 };
61 
62 struct nvme_id_power_state {
63  __le16 max_power; /* centiwatts */
64  __u16 rsvd2;
65  __le32 entry_lat; /* microseconds */
66  __le32 exit_lat; /* microseconds */
67  __u8 read_tput;
68  __u8 read_lat;
69  __u8 write_tput;
70  __u8 write_lat;
71  __u8 rsvd16[16];
72 };
73 
74 #define NVME_VS(major, minor) (major << 16 | minor)
75 
76 struct nvme_id_ctrl {
77  __le16 vid;
78  __le16 ssvid;
79  char sn[20];
80  char mn[40];
81  char fr[8];
82  __u8 rab;
83  __u8 ieee[3];
84  __u8 mic;
85  __u8 mdts;
86  __u8 rsvd78[178];
87  __le16 oacs;
88  __u8 acl;
89  __u8 aerl;
90  __u8 frmw;
91  __u8 lpa;
92  __u8 elpe;
93  __u8 npss;
94  __u8 rsvd264[248];
95  __u8 sqes;
96  __u8 cqes;
97  __u8 rsvd514[2];
98  __le32 nn;
99  __le16 oncs;
100  __le16 fuses;
101  __u8 fna;
102  __u8 vwc;
103  __le16 awun;
104  __le16 awupf;
105  __u8 rsvd530[1518];
106  struct nvme_id_power_state psd[32];
107  __u8 vs[1024];
108 };
109 
110 struct nvme_lbaf {
111  __le16 ms;
112  __u8 ds;
113  __u8 rp;
114 };
115 
116 struct nvme_id_ns {
117  __le64 nsze;
118  __le64 ncap;
119  __le64 nuse;
120  __u8 nsfeat;
121  __u8 nlbaf;
122  __u8 flbas;
123  __u8 mc;
124  __u8 dpc;
125  __u8 dps;
126  __u8 rsvd30[98];
127  struct nvme_lbaf lbaf[16];
128  __u8 rsvd192[192];
129  __u8 vs[3712];
130 };
131 
132 enum {
133  NVME_NS_FEAT_THIN = 1 << 0,
134  NVME_LBAF_RP_BEST = 0,
135  NVME_LBAF_RP_BETTER = 1,
136  NVME_LBAF_RP_GOOD = 2,
137  NVME_LBAF_RP_DEGRADED = 3,
138 };
139 
140 struct nvme_lba_range_type {
141  __u8 type;
142  __u8 attributes;
143  __u8 rsvd2[14];
144  __u64 slba;
145  __u64 nlb;
146  __u8 guid[16];
147  __u8 rsvd48[16];
148 };
149 
150 enum {
151  NVME_LBART_TYPE_FS = 0x01,
152  NVME_LBART_TYPE_RAID = 0x02,
153  NVME_LBART_TYPE_CACHE = 0x03,
154  NVME_LBART_TYPE_SWAP = 0x04,
155 
156  NVME_LBART_ATTRIB_TEMP = 1 << 0,
157  NVME_LBART_ATTRIB_HIDE = 1 << 1,
158 };
159 
160 /* I/O commands */
161 
162 enum nvme_opcode {
163  nvme_cmd_flush = 0x00,
164  nvme_cmd_write = 0x01,
165  nvme_cmd_read = 0x02,
166  nvme_cmd_write_uncor = 0x04,
167  nvme_cmd_compare = 0x05,
168  nvme_cmd_dsm = 0x09,
169 };
170 
171 struct nvme_common_command {
172  __u8 opcode;
173  __u8 flags;
174  __u16 command_id;
175  __le32 nsid;
176  __u32 cdw2[2];
177  __le64 metadata;
178  __le64 prp1;
179  __le64 prp2;
180  __u32 cdw10[6];
181 };
182 
183 struct nvme_rw_command {
184  __u8 opcode;
185  __u8 flags;
186  __u16 command_id;
187  __le32 nsid;
188  __u64 rsvd2;
189  __le64 metadata;
190  __le64 prp1;
191  __le64 prp2;
192  __le64 slba;
193  __le16 length;
194  __le16 control;
195  __le32 dsmgmt;
196  __le32 reftag;
197  __le16 apptag;
198  __le16 appmask;
199 };
200 
201 enum {
202  NVME_RW_LR = 1 << 15,
203  NVME_RW_FUA = 1 << 14,
204  NVME_RW_DSM_FREQ_UNSPEC = 0,
205  NVME_RW_DSM_FREQ_TYPICAL = 1,
206  NVME_RW_DSM_FREQ_RARE = 2,
207  NVME_RW_DSM_FREQ_READS = 3,
208  NVME_RW_DSM_FREQ_WRITES = 4,
209  NVME_RW_DSM_FREQ_RW = 5,
210  NVME_RW_DSM_FREQ_ONCE = 6,
211  NVME_RW_DSM_FREQ_PREFETCH = 7,
212  NVME_RW_DSM_FREQ_TEMP = 8,
213  NVME_RW_DSM_LATENCY_NONE = 0 << 4,
214  NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
215  NVME_RW_DSM_LATENCY_NORM = 2 << 4,
216  NVME_RW_DSM_LATENCY_LOW = 3 << 4,
217  NVME_RW_DSM_SEQ_REQ = 1 << 6,
218  NVME_RW_DSM_COMPRESSED = 1 << 7,
219 };
220 
221 /* Admin commands */
222 
223 enum nvme_admin_opcode {
224  nvme_admin_delete_sq = 0x00,
225  nvme_admin_create_sq = 0x01,
226  nvme_admin_get_log_page = 0x02,
227  nvme_admin_delete_cq = 0x04,
228  nvme_admin_create_cq = 0x05,
229  nvme_admin_identify = 0x06,
230  nvme_admin_abort_cmd = 0x08,
231  nvme_admin_set_features = 0x09,
232  nvme_admin_get_features = 0x0a,
233  nvme_admin_async_event = 0x0c,
234  nvme_admin_activate_fw = 0x10,
235  nvme_admin_download_fw = 0x11,
236  nvme_admin_format_nvm = 0x80,
237  nvme_admin_security_send = 0x81,
238  nvme_admin_security_recv = 0x82,
239 };
240 
241 enum {
242  NVME_QUEUE_PHYS_CONTIG = (1 << 0),
243  NVME_CQ_IRQ_ENABLED = (1 << 1),
244  NVME_SQ_PRIO_URGENT = (0 << 1),
245  NVME_SQ_PRIO_HIGH = (1 << 1),
246  NVME_SQ_PRIO_MEDIUM = (2 << 1),
247  NVME_SQ_PRIO_LOW = (3 << 1),
248  NVME_FEAT_ARBITRATION = 0x01,
249  NVME_FEAT_POWER_MGMT = 0x02,
250  NVME_FEAT_LBA_RANGE = 0x03,
251  NVME_FEAT_TEMP_THRESH = 0x04,
252  NVME_FEAT_ERR_RECOVERY = 0x05,
253  NVME_FEAT_VOLATILE_WC = 0x06,
254  NVME_FEAT_NUM_QUEUES = 0x07,
255  NVME_FEAT_IRQ_COALESCE = 0x08,
256  NVME_FEAT_IRQ_CONFIG = 0x09,
257  NVME_FEAT_WRITE_ATOMIC = 0x0a,
258  NVME_FEAT_ASYNC_EVENT = 0x0b,
259  NVME_FEAT_SW_PROGRESS = 0x0c,
260 };
261 
262 struct nvme_identify {
263  __u8 opcode;
264  __u8 flags;
265  __u16 command_id;
266  __le32 nsid;
267  __u64 rsvd2[2];
268  __le64 prp1;
269  __le64 prp2;
270  __le32 cns;
271  __u32 rsvd11[5];
272 };
273 
274 struct nvme_features {
275  __u8 opcode;
276  __u8 flags;
277  __u16 command_id;
278  __le32 nsid;
279  __u64 rsvd2[2];
280  __le64 prp1;
281  __le64 prp2;
282  __le32 fid;
283  __le32 dword11;
284  __u32 rsvd12[4];
285 };
286 
287 struct nvme_create_cq {
288  __u8 opcode;
289  __u8 flags;
290  __u16 command_id;
291  __u32 rsvd1[5];
292  __le64 prp1;
293  __u64 rsvd8;
294  __le16 cqid;
295  __le16 qsize;
296  __le16 cq_flags;
297  __le16 irq_vector;
298  __u32 rsvd12[4];
299 };
300 
301 struct nvme_create_sq {
302  __u8 opcode;
303  __u8 flags;
304  __u16 command_id;
305  __u32 rsvd1[5];
306  __le64 prp1;
307  __u64 rsvd8;
308  __le16 sqid;
309  __le16 qsize;
310  __le16 sq_flags;
311  __le16 cqid;
312  __u32 rsvd12[4];
313 };
314 
315 struct nvme_delete_queue {
316  __u8 opcode;
317  __u8 flags;
318  __u16 command_id;
319  __u32 rsvd1[9];
320  __le16 qid;
321  __u16 rsvd10;
322  __u32 rsvd11[5];
323 };
324 
325 struct nvme_download_firmware {
326  __u8 opcode;
327  __u8 flags;
328  __u16 command_id;
329  __u32 rsvd1[5];
330  __le64 prp1;
331  __le64 prp2;
332  __le32 numd;
333  __le32 offset;
334  __u32 rsvd12[4];
335 };
336 
337 struct nvme_command {
338  union {
339  struct nvme_common_command common;
340  struct nvme_rw_command rw;
341  struct nvme_identify identify;
342  struct nvme_features features;
343  struct nvme_create_cq create_cq;
344  struct nvme_create_sq create_sq;
345  struct nvme_delete_queue delete_queue;
346  struct nvme_download_firmware dlfw;
347  };
348 };
349 
350 enum {
351  NVME_SC_SUCCESS = 0x0,
352  NVME_SC_INVALID_OPCODE = 0x1,
353  NVME_SC_INVALID_FIELD = 0x2,
354  NVME_SC_CMDID_CONFLICT = 0x3,
355  NVME_SC_DATA_XFER_ERROR = 0x4,
356  NVME_SC_POWER_LOSS = 0x5,
357  NVME_SC_INTERNAL = 0x6,
358  NVME_SC_ABORT_REQ = 0x7,
359  NVME_SC_ABORT_QUEUE = 0x8,
360  NVME_SC_FUSED_FAIL = 0x9,
361  NVME_SC_FUSED_MISSING = 0xa,
362  NVME_SC_INVALID_NS = 0xb,
363  NVME_SC_LBA_RANGE = 0x80,
364  NVME_SC_CAP_EXCEEDED = 0x81,
365  NVME_SC_NS_NOT_READY = 0x82,
366  NVME_SC_CQ_INVALID = 0x100,
367  NVME_SC_QID_INVALID = 0x101,
368  NVME_SC_QUEUE_SIZE = 0x102,
369  NVME_SC_ABORT_LIMIT = 0x103,
370  NVME_SC_ABORT_MISSING = 0x104,
371  NVME_SC_ASYNC_LIMIT = 0x105,
372  NVME_SC_FIRMWARE_SLOT = 0x106,
373  NVME_SC_FIRMWARE_IMAGE = 0x107,
374  NVME_SC_INVALID_VECTOR = 0x108,
375  NVME_SC_INVALID_LOG_PAGE = 0x109,
376  NVME_SC_INVALID_FORMAT = 0x10a,
377  NVME_SC_BAD_ATTRIBUTES = 0x180,
378  NVME_SC_WRITE_FAULT = 0x280,
379  NVME_SC_READ_ERROR = 0x281,
380  NVME_SC_GUARD_CHECK = 0x282,
381  NVME_SC_APPTAG_CHECK = 0x283,
382  NVME_SC_REFTAG_CHECK = 0x284,
383  NVME_SC_COMPARE_FAILED = 0x285,
384  NVME_SC_ACCESS_DENIED = 0x286,
385 };
386 
387 struct nvme_completion {
388  __le32 result; /* Used by admin commands to return data */
389  __u32 rsvd;
390  __le16 sq_head; /* how much of this queue may be reclaimed */
391  __le16 sq_id; /* submission queue that generated this entry */
392  __u16 command_id; /* of the command which completed */
393  __le16 status; /* did the command fail, and if so, why? */
394 };
395 
396 struct nvme_user_io {
397  __u8 opcode;
398  __u8 flags;
399  __u16 control;
400  __u16 nblocks;
401  __u16 rsvd;
402  __u64 metadata;
403  __u64 addr;
404  __u64 slba;
405  __u32 dsmgmt;
406  __u32 reftag;
407  __u16 apptag;
408  __u16 appmask;
409 };
410 
411 struct nvme_admin_cmd {
412  __u8 opcode;
413  __u8 flags;
414  __u16 rsvd1;
415  __u32 nsid;
416  __u32 cdw2;
417  __u32 cdw3;
418  __u64 metadata;
419  __u64 addr;
420  __u32 metadata_len;
421  __u32 data_len;
422  __u32 cdw10;
423  __u32 cdw11;
424  __u32 cdw12;
425  __u32 cdw13;
426  __u32 cdw14;
427  __u32 cdw15;
428  __u32 timeout_ms;
429  __u32 result;
430 };
431 
432 #define NVME_IOCTL_ID _IO('N', 0x40)
433 #define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
434 #define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
435 
436 #endif /* _LINUX_NVME_H */
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