|
| #define | RTL8169_VERSION "2.3LK-NAPI" |
| |
| #define | MODULENAME "r8169" |
| |
| #define | PFX MODULENAME ": " |
| |
| #define | FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
| |
| #define | FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" |
| |
| #define | FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
| |
| #define | FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" |
| |
| #define | FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
| |
| #define | FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" |
| |
| #define | FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" |
| |
| #define | FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
| |
| #define | FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" |
| |
| #define | FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" |
| |
| #define | FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" |
| |
| #define | FIRMWARE_8168G_1 "rtl_nic/rtl8168g-1.fw" |
| |
| #define | assert(expr) do {} while (0) |
| |
| #define | dprintk(fmt, args...) do {} while (0) |
| |
| #define | R8169_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
| |
| #define | TX_SLOTS_AVAIL(tp) (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx) |
| |
| #define | TX_FRAGS_READY_FOR(tp, nr_frags) (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1)) |
| |
| #define | MAX_READ_REQUEST_SHIFT 12 |
| |
| #define | TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ |
| |
| #define | SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
| |
| #define | InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ |
| |
| #define | R8169_REGS_SIZE 256 |
| |
| #define | R8169_NAPI_WEIGHT 64 |
| |
| #define | NUM_TX_DESC 64 /* Number of Tx descriptor registers */ |
| |
| #define | NUM_RX_DESC 256 /* Number of Rx descriptor registers */ |
| |
| #define | RX_BUF_SIZE 1536 /* Rx Buffer size */ |
| |
| #define | R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) |
| |
| #define | R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) |
| |
| #define | RTL8169_TX_TIMEOUT (6*HZ) |
| |
| #define | RTL8169_PHY_TIMEOUT (10*HZ) |
| |
| #define | RTL_EEPROM_SIG cpu_to_le32(0x8129) |
| |
| #define | RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) |
| |
| #define | RTL_EEPROM_SIG_ADDR 0x0000 |
| |
| #define | RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
| |
| #define | RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) |
| |
| #define | RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) |
| |
| #define | RTL_R8(reg) readb (ioaddr + (reg)) |
| |
| #define | RTL_R16(reg) readw (ioaddr + (reg)) |
| |
| #define | RTL_R32(reg) readl (ioaddr + (reg)) |
| |
| #define | JUMBO_1K ETH_DATA_LEN |
| |
| #define | JUMBO_4K (4*1024 - ETH_HLEN - 2) |
| |
| #define | JUMBO_6K (6*1024 - ETH_HLEN - 2) |
| |
| #define | JUMBO_7K (7*1024 - ETH_HLEN - 2) |
| |
| #define | JUMBO_9K (9*1024 - ETH_HLEN - 2) |
| |
| #define | _R(NAME, TD, FW, SZ, B) |
| |
| #define | TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
| |
| #define | TXCFG_EMPTY (1 << 11) /* 8111e-vl */ |
| |
| #define | RX128_INT_EN (1 << 15) /* 8111c and later */ |
| |
| #define | RX_MULTI_EN (1 << 14) /* 8111c only */ |
| |
| #define | RXCFG_FIFO_SHIFT 13 |
| |
| #define | RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) |
| |
| #define | RXCFG_DMA_SHIFT 8 |
| |
| #define | RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) |
| |
| #define | PME_SIGNAL (1 << 5) /* 8168c and later */ |
| |
| #define | NoEarlyTx 0x3f /* Max value : no early transmit. */ |
| |
| #define | TxPacketMax (8064 >> 7) |
| |
| #define | EarlySize 0x27 |
| |
| #define | CSIAR_FLAG 0x80000000 |
| |
| #define | CSIAR_WRITE_CMD 0x80000000 |
| |
| #define | CSIAR_BYTE_ENABLE 0x0f |
| |
| #define | CSIAR_BYTE_ENABLE_SHIFT 12 |
| |
| #define | CSIAR_ADDR_MASK 0x0fff |
| |
| #define | CSIAR_FUNC_CARD 0x00000000 |
| |
| #define | CSIAR_FUNC_SDIO 0x00010000 |
| |
| #define | CSIAR_FUNC_NIC 0x00020000 |
| |
| #define | EPHYAR_FLAG 0x80000000 |
| |
| #define | EPHYAR_WRITE_CMD 0x80000000 |
| |
| #define | EPHYAR_REG_MASK 0x1f |
| |
| #define | EPHYAR_REG_SHIFT 16 |
| |
| #define | EPHYAR_DATA_MASK 0xffff |
| |
| #define | PFM_EN (1 << 6) |
| |
| #define | FIX_NAK_1 (1 << 4) |
| |
| #define | FIX_NAK_2 (1 << 3) |
| |
| #define | NOW_IS_OOB (1 << 7) |
| |
| #define | TX_EMPTY (1 << 5) |
| |
| #define | RX_EMPTY (1 << 4) |
| |
| #define | RXTX_EMPTY (TX_EMPTY | RX_EMPTY) |
| |
| #define | EN_NDP (1 << 3) |
| |
| #define | EN_OOB_RESET (1 << 2) |
| |
| #define | LINK_LIST_RDY (1 << 1) |
| |
| #define | EFUSEAR_FLAG 0x80000000 |
| |
| #define | EFUSEAR_WRITE_CMD 0x80000000 |
| |
| #define | EFUSEAR_READ_CMD 0x00000000 |
| |
| #define | EFUSEAR_REG_MASK 0x03ff |
| |
| #define | EFUSEAR_REG_SHIFT 8 |
| |
| #define | EFUSEAR_DATA_MASK 0xff |
| |
| #define | ERIAR_FLAG 0x80000000 |
| |
| #define | ERIAR_WRITE_CMD 0x80000000 |
| |
| #define | ERIAR_READ_CMD 0x00000000 |
| |
| #define | ERIAR_ADDR_BYTE_ALIGN 4 |
| |
| #define | ERIAR_TYPE_SHIFT 16 |
| |
| #define | ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
| |
| #define | ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) |
| |
| #define | ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) |
| |
| #define | ERIAR_MASK_SHIFT 12 |
| |
| #define | ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) |
| |
| #define | ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) |
| |
| #define | ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) |
| |
| #define | ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) |
| |
| #define | OCPDR_WRITE_CMD 0x80000000 |
| |
| #define | OCPDR_READ_CMD 0x00000000 |
| |
| #define | OCPDR_REG_MASK 0x7f |
| |
| #define | OCPDR_GPHY_REG_SHIFT 16 |
| |
| #define | OCPDR_DATA_MASK 0xffff |
| |
| #define | OCPAR_FLAG 0x80000000 |
| |
| #define | OCPAR_GPHY_WRITE_CMD 0x8000f060 |
| |
| #define | OCPAR_GPHY_READ_CMD 0x0000f060 |
| |
| #define | TXPLA_RST (1 << 29) |
| |
| #define | DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ |
| |
| #define | PWM_EN (1 << 22) |
| |
| #define | RXDV_GATED_EN (1 << 19) |
| |
| #define | EARLY_TALLY_EN (1 << 16) |
| |
| #define | RX_CONFIG_ACCEPT_MASK 0x3f |
| |
| #define | TD_MSS_MAX 0x07ffu /* MSS value */ |
| |
| #define | TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ |
| |
| #define | TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ |
| |
| #define | RxProtoUDP (PID1) |
| |
| #define | RxProtoTCP (PID0) |
| |
| #define | RxProtoIP (PID1 | PID0) |
| |
| #define | RxProtoMask RxProtoIP |
| |
| #define | RsvdMask 0x3fffc000 |
| |
| #define | RTL_VER_SIZE 32 |
| |
| #define | RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
| |
| #define | DECLARE_RTL_COND(name) |
| |
| #define | OOB_CMD_RESET 0x00 |
| |
| #define | OOB_CMD_DRIVER_START 0x05 |
| |
| #define | OOB_CMD_DRIVER_STOP 0x06 |
| |
| #define | OCP_STD_PHY_BASE 0xa400 |
| |
| #define | R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
| |
| #define | RTL_EVENT_NAPI_RX (RxOK | RxErr) |
| |
| #define | RTL_EVENT_NAPI_TX (TxOK | TxErr) |
| |
| #define | RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX) |
| |
| #define | WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
| |
| #define | PHY_READ 0x00000000 |
| |
| #define | PHY_DATA_OR 0x10000000 |
| |
| #define | PHY_DATA_AND 0x20000000 |
| |
| #define | PHY_BJMPN 0x30000000 |
| |
| #define | PHY_READ_EFUSE 0x40000000 |
| |
| #define | PHY_READ_MAC_BYTE 0x50000000 |
| |
| #define | PHY_WRITE_MAC_BYTE 0x60000000 |
| |
| #define | PHY_CLEAR_READCOUNT 0x70000000 |
| |
| #define | PHY_WRITE 0x80000000 |
| |
| #define | PHY_READCOUNT_EQ_SKIP 0x90000000 |
| |
| #define | PHY_COMP_EQ_SKIPN 0xa0000000 |
| |
| #define | PHY_COMP_NEQ_SKIPN 0xb0000000 |
| |
| #define | PHY_WRITE_PREVIOUS 0xc0000000 |
| |
| #define | PHY_SKIPN 0xd0000000 |
| |
| #define | PHY_DELAY_MS 0xe0000000 |
| |
| #define | PHY_WRITE_ERI_WORD 0xf0000000 |
| |
| #define | FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
| |
| #define | R8168_CPCMD_QUIRK_MASK |
| |
| #define | R810X_CPCMD_QUIRK_MASK |
| |
| #define | RTL8169_PM_OPS NULL |
| |
|
| enum | mac_version {
RTL_GIGA_MAC_VER_01 = 0,
RTL_GIGA_MAC_VER_02,
RTL_GIGA_MAC_VER_03,
RTL_GIGA_MAC_VER_04,
RTL_GIGA_MAC_VER_05,
RTL_GIGA_MAC_VER_06,
RTL_GIGA_MAC_VER_07,
RTL_GIGA_MAC_VER_08,
RTL_GIGA_MAC_VER_09,
RTL_GIGA_MAC_VER_10,
RTL_GIGA_MAC_VER_11,
RTL_GIGA_MAC_VER_12,
RTL_GIGA_MAC_VER_13,
RTL_GIGA_MAC_VER_14,
RTL_GIGA_MAC_VER_15,
RTL_GIGA_MAC_VER_16,
RTL_GIGA_MAC_VER_17,
RTL_GIGA_MAC_VER_18,
RTL_GIGA_MAC_VER_19,
RTL_GIGA_MAC_VER_20,
RTL_GIGA_MAC_VER_21,
RTL_GIGA_MAC_VER_22,
RTL_GIGA_MAC_VER_23,
RTL_GIGA_MAC_VER_24,
RTL_GIGA_MAC_VER_25,
RTL_GIGA_MAC_VER_26,
RTL_GIGA_MAC_VER_27,
RTL_GIGA_MAC_VER_28,
RTL_GIGA_MAC_VER_29,
RTL_GIGA_MAC_VER_30,
RTL_GIGA_MAC_VER_31,
RTL_GIGA_MAC_VER_32,
RTL_GIGA_MAC_VER_33,
RTL_GIGA_MAC_VER_34,
RTL_GIGA_MAC_VER_35,
RTL_GIGA_MAC_VER_36,
RTL_GIGA_MAC_VER_37,
RTL_GIGA_MAC_VER_38,
RTL_GIGA_MAC_VER_39,
RTL_GIGA_MAC_VER_40,
RTL_GIGA_MAC_VER_41,
RTL_GIGA_MAC_NONE = 0xff
} |
| |
| enum | rtl_tx_desc_version { RTL_TD_0 = 0,
RTL_TD_1 = 1
} |
| |
| enum | cfg_version { RTL_CFG_0 = 0x00,
RTL_CFG_1,
RTL_CFG_2
} |
| |
| enum | rtl_registers {
MAC0 = 0,
MAC4 = 4,
MAR0 = 8,
CounterAddrLow = 0x10,
CounterAddrHigh = 0x14,
TxDescStartAddrLow = 0x20,
TxDescStartAddrHigh = 0x24,
TxHDescStartAddrLow = 0x28,
TxHDescStartAddrHigh = 0x2c,
FLASH = 0x30,
ERSR = 0x36,
ChipCmd = 0x37,
TxPoll = 0x38,
IntrMask = 0x3c,
IntrStatus = 0x3e,
TxConfig = 0x40,
RxConfig = 0x44,
RxMissed = 0x4c,
Cfg9346 = 0x50,
Config0 = 0x51,
Config1 = 0x52,
Config2 = 0x53,
Config3 = 0x54,
Config4 = 0x55,
Config5 = 0x56,
MultiIntr = 0x5c,
PHYAR = 0x60,
PHYstatus = 0x6c,
RxMaxSize = 0xda,
CPlusCmd = 0xe0,
IntrMitigate = 0xe2,
RxDescAddrLow = 0xe4,
RxDescAddrHigh = 0xe8,
EarlyTxThres = 0xec,
MaxTxPacketSize = 0xec,
FuncEvent = 0xf0,
FuncEventMask = 0xf4,
FuncPresetState = 0xf8,
FuncForceEvent = 0xfc
} |
| |
| enum | rtl8110_registers { TBICSR = 0x64,
TBI_ANAR = 0x68,
TBI_LPAR = 0x6a
} |
| |
| enum | rtl8168_8101_registers {
CSIDR = 0x64,
CSIAR = 0x68,
PMCH = 0x6f,
EPHYAR = 0x80,
DLLPR = 0xd0,
DBG_REG = 0xd1,
TWSI = 0xd2,
MCU = 0xd3,
EFUSEAR = 0xdc
} |
| |
| enum | rtl8168_registers {
LED_FREQ = 0x1a,
EEE_LED = 0x1b,
ERIDR = 0x70,
ERIAR = 0x74,
EPHY_RXER_NUM = 0x7c,
OCPDR = 0xb0,
OCPAR = 0xb4,
GPHY_OCP = 0xb8,
RDSAR1 = 0xd0,
MISC = 0xf0
} |
| |
| enum | rtl_register_content {
SYSErr = 0x8000,
PCSTimeout = 0x4000,
SWInt = 0x0100,
TxDescUnavail = 0x0080,
RxFIFOOver = 0x0040,
LinkChg = 0x0020,
RxOverflow = 0x0010,
TxErr = 0x0008,
TxOK = 0x0004,
RxErr = 0x0002,
RxOK = 0x0001,
RxBOVF = (1 << 24),
RxFOVF = (1 << 23),
RxRWT = (1 << 22),
RxRES = (1 << 21),
RxRUNT = (1 << 20),
RxCRC = (1 << 19),
StopReq = 0x80,
CmdReset = 0x10,
CmdRxEnb = 0x08,
CmdTxEnb = 0x04,
RxBufEmpty = 0x01,
HPQ = 0x80,
NPQ = 0x40,
FSWInt = 0x01,
Cfg9346_Lock = 0x00,
Cfg9346_Unlock = 0xc0,
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0x08,
AcceptMulticast = 0x04,
AcceptMyPhys = 0x02,
AcceptAllPhys = 0x01,
TxInterFrameGapShift = 24,
TxDMAShift = 8,
LEDS1 = (1 << 7),
LEDS0 = (1 << 6),
Speed_down = (1 << 4),
MEMMAP = (1 << 3),
IOMAP = (1 << 2),
VPD = (1 << 1),
PMEnable = (1 << 0),
MSIEnable = (1 << 5),
PCI_Clock_66MHz = 0x01,
PCI_Clock_33MHz = 0x00,
MagicPacket = (1 << 5),
LinkUp = (1 << 4),
Jumbo_En0 = (1 << 2),
Beacon_en = (1 << 0),
Jumbo_En1 = (1 << 1),
BWF = (1 << 6),
MWF = (1 << 5),
UWF = (1 << 4),
Spi_en = (1 << 3),
LanWake = (1 << 1),
PMEStatus = (1 << 0),
TBIReset = 0x80000000,
TBILoopback = 0x40000000,
TBINwEnable = 0x20000000,
TBINwRestart = 0x10000000,
TBILinkOk = 0x02000000,
TBINwComplete = 0x01000000,
EnableBist = (1 << 15),
Mac_dbgo_oe = (1 << 14),
Normal_mode = (1 << 13),
Force_half_dup = (1 << 12),
Force_rxflow_en = (1 << 11),
Force_txflow_en = (1 << 10),
Cxpl_dbg_sel = (1 << 9),
ASF = (1 << 8),
PktCntrDisable = (1 << 7),
Mac_dbgo_sel = 0x001c,
RxVlan = (1 << 6),
RxChkSum = (1 << 5),
PCIDAC = (1 << 4),
PCIMulRW = (1 << 3),
INTT_0 = 0x0000,
INTT_1 = 0x0001,
INTT_2 = 0x0002,
INTT_3 = 0x0003,
TBI_Enable = 0x80,
TxFlowCtrl = 0x40,
RxFlowCtrl = 0x20,
_1000bpsF = 0x10,
_100bps = 0x08,
_10bps = 0x04,
LinkStatus = 0x02,
FullDup = 0x01,
TBILinkOK = 0x02000000,
CounterDump = 0x8
} |
| |
| enum | rtl_desc_bit { DescOwn = (1 << 31),
RingEnd = (1 << 30),
FirstFrag = (1 << 29),
LastFrag = (1 << 28)
} |
| |
| enum | rtl_tx_desc_bit { TD_LSO = (1 << 27),
TxVlanTag = (1 << 17)
} |
| |
| enum | rtl_tx_desc_bit_0 { TD0_TCP_CS = (1 << 16),
TD0_UDP_CS = (1 << 17),
TD0_IP_CS = (1 << 18)
} |
| |
| enum | rtl_tx_desc_bit_1 { TD1_IP_CS = (1 << 29),
TD1_TCP_CS = (1 << 30),
TD1_UDP_CS = (1 << 31)
} |
| |
| enum | rtl_rx_desc_bit {
PID1 = (1 << 18),
PID0 = (1 << 17),
IPFail = (1 << 16),
UDPFail = (1 << 15),
TCPFail = (1 << 14),
RxVlanTag = (1 << 16)
} |
| |
| enum | features { RTL_FEATURE_WOL = (1 << 0),
RTL_FEATURE_MSI = (1 << 1),
RTL_FEATURE_GMII = (1 << 2)
} |
| |
| enum | rtl_flag {
RTL_FLAG_TASK_ENABLED,
RTL_FLAG_TASK_SLOW_PENDING,
RTL_FLAG_TASK_RESET_PENDING,
RTL_FLAG_TASK_PHY_PENDING,
RTL_FLAG_MAX
} |
| |
|
| | MODULE_DEVICE_TABLE (pci, rtl8169_pci_tbl) |
| |
| | MODULE_AUTHOR ("Realtek and the Linux r8169 crew <[email protected]>") |
| |
| | MODULE_DESCRIPTION ("RealTek RTL-8169 Gigabit Ethernet driver") |
| |
| | module_param (use_dac, int, 0) |
| |
| | MODULE_PARM_DESC (use_dac,"Enable PCI DAC. Unsafe on 32 bit PCI slot.") |
| |
| | module_param_named (debug, debug.msg_enable, int, 0) |
| |
| | MODULE_PARM_DESC (debug,"Debug verbosity level (0=none, ..., 16=all)") |
| |
| | MODULE_LICENSE ("GPL") |
| |
| | MODULE_VERSION (RTL8169_VERSION) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168D_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168D_2) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168E_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168E_2) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168E_3) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8105E_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168F_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168F_2) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8402_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8411_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8106E_1) |
| |
| | MODULE_FIRMWARE (FIRMWARE_8168G_1) |
| |
| | DECLARE_RTL_COND (rtl_ocpar_cond) |
| |
| | DECLARE_RTL_COND (rtl_eriar_cond) |
| |
| | DECLARE_RTL_COND (rtl_ocp_read_cond) |
| |
| | DECLARE_RTL_COND (rtl_ocp_gphy_cond) |
| |
| | DECLARE_RTL_COND (rtl_phyar_cond) |
| |
| | DECLARE_RTL_COND (rtl_ephyar_cond) |
| |
| | DECLARE_RTL_COND (rtl_efusear_cond) |
| |
| | DECLARE_RTL_COND (rtl_counters_cond) |
| |
| | DECLARE_RTL_COND (rtl_phy_reset_cond) |
| |
| | DECLARE_RTL_COND (rtl_chipcmd_cond) |
| |
| | DECLARE_RTL_COND (rtl_npq_cond) |
| |
| | DECLARE_RTL_COND (rtl_txcfg_empty_cond) |
| |
| | DECLARE_RTL_COND (rtl_csiar_cond) |
| |
| | DECLARE_RTL_COND (rtl_link_list_ready_cond) |
| |
| | DECLARE_RTL_COND (rtl_rxtx_empty_cond) |
| |
| | module_init (rtl8169_init_module) |
| |
| | module_exit (rtl8169_cleanup_module) |
| |
1.8.2