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oaktrail.h
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1 /**************************************************************************
2  * Copyright (c) 2007-2011, Intel Corporation.
3  * All Rights Reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  **************************************************************************/
19 
20 /* MID device specific descriptors */
21 
53 } __packed;
54 
77 } __packed;
78 
80  u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
81  /* 0x61190 if MIPI */
82  u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
83  u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
85  /* Register 0x61210 */
86  struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
87  u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
88  /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
89  /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
91  /*16 bits, Defined as follows: */
92  /* if MIPI, 0x0000 if LVDS */
93  /* Bit 0, Type, 2 bits, */
94  /* 0: Type-1, */
95  /* 1: Type-2, */
96  /* 2: Type-3, */
97  /* 3: Type-4 */
98  /* Bit 2, Pixel Format, 4 bits */
99  /* Bit0: 16bpp (not supported in LNC), */
100  /* Bit1: 18bpp loosely packed, */
101  /* Bit2: 18bpp packed, */
102  /* Bit3: 24bpp */
103  /* Bit 6, Reserved, 2 bits, 00b */
104  /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
105  /* Bit 14, Reserved, 2 bits, 00b */
106 } __packed;
107 
109  u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
110  /* 0x61190 if MIPI */
111  u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
112  u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
114  /* Register 0x61210 */
115  struct oaktrail_timing_info DTD;/*18 bytes, Standard definition */
116  u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
117  /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
118  u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
119  /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
121  /*16 bits, Defined as follows: */
122  /* if MIPI, 0x0000 if LVDS */
123  /* Bit 0, Type, 2 bits, */
124  /* 0: Type-1, */
125  /* 1: Type-2, */
126  /* 2: Type-3, */
127  /* 3: Type-4 */
128  /* Bit 2, Pixel Format, 4 bits */
129  /* Bit0: 16bpp (not supported in LNC), */
130  /* Bit1: 18bpp loosely packed, */
131  /* Bit2: 18bpp packed, */
132  /* Bit3: 24bpp */
133  /* Bit 6, Reserved, 2 bits, 00b */
134  /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
135  /* Bit 14, Reserved, 2 bits, 00b */
136 } __packed;
137 
139  struct {
140  u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
141  /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
142  u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
143  /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
144  u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
145  /* 1: Burst and non-burst */
146  /* 2/3: Reserved */
147  u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
148  u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
149  u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
150  u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
151  u16 Rsvd:5;/*5 bits,00000b */
152  } panelrx;
154 } __packed;
155 
156 struct gct_r0 {
157  union { /*8 bits,Defined as follows: */
158  struct {
159  u8 PanelType:4; /*4 bits, Bit field for panels*/
160  /* 0 - 3: 0 = LVDS, 1 = MIPI*/
161  /*2 bits,Specifies which of the*/
163  /* 4 panels to use by default*/
164  u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
165  /* the 4 MIPI DSI receivers to use*/
166  } PD;
168  };
169  struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
170  union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
171 } __packed;
172 
173 struct gct_r1 {
174  union { /*8 bits,Defined as follows: */
175  struct {
176  u8 PanelType:4; /*4 bits, Bit field for panels*/
177  /* 0 - 3: 0 = LVDS, 1 = MIPI*/
178  /*2 bits,Specifies which of the*/
180  /* 4 panels to use by default*/
181  u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
182  /* the 4 MIPI DSI receivers to use*/
183  } PD;
185  };
186  struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
187  union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
188 } __packed;
189 
190 struct gct_r10 {
198 } __packed;
199 
201  u8 bpi; /* boot panel index, number of panel used during boot */
202  u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
203  struct oaktrail_timing_info DTD; /* timing info for the selected panel */
205  u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
206  u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
210 } __packed;
211 
212 #define MODE_SETTING_IN_CRTC 0x1
213 #define MODE_SETTING_IN_ENCODER 0x2
214 #define MODE_SETTING_ON_GOING 0x3
215 #define MODE_SETTING_IN_DSR 0x4
216 #define MODE_SETTING_ENCODER_DONE 0x8
217 
218 /*
219  * Moorestown HDMI interfaces
220  */
221 
223  struct pci_dev *dev;
224  void __iomem *regs;
225  unsigned int mmio, mmio_len;
228 
229  /* register state */
243 };
244 
245 extern void oaktrail_hdmi_setup(struct drm_device *dev);
246 extern void oaktrail_hdmi_teardown(struct drm_device *dev);
247 extern int oaktrail_hdmi_i2c_init(struct pci_dev *dev);
248 extern void oaktrail_hdmi_i2c_exit(struct pci_dev *dev);
249 extern void oaktrail_hdmi_save(struct drm_device *dev);
250 extern void oaktrail_hdmi_restore(struct drm_device *dev);
251 extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev);