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octeon.h
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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License. See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 2004-2008 Cavium Networks
7  */
8 #ifndef __ASM_OCTEON_OCTEON_H
9 #define __ASM_OCTEON_OCTEON_H
10 
11 #include <asm/octeon/cvmx.h>
12 
15  uint64_t min_addr,
16  uint64_t max_addr,
17  int do_locking);
19  int do_locking);
21  uint64_t min_addr, uint64_t max_addr,
22  int do_locking);
24  char *name);
26  uint64_t max_addr, uint64_t align,
27  char *name);
29  char *name);
30 extern int octeon_bootmem_free_named(char *name);
31 extern void octeon_bootmem_lock(void);
32 extern void octeon_bootmem_unlock(void);
33 
34 extern int octeon_is_simulation(void);
35 extern int octeon_is_pci_host(void);
36 extern int octeon_usb_is_ref_clk(void);
37 extern uint64_t octeon_get_clock_rate(void);
38 extern u64 octeon_get_io_clock_rate(void);
39 extern const char *octeon_board_type_string(void);
40 extern const char *octeon_get_pci_interrupts(void);
41 extern int octeon_get_southbridge_interrupt(void);
42 extern int octeon_get_boot_coremask(void);
43 extern int octeon_get_boot_num_arguments(void);
44 extern const char *octeon_get_boot_argument(int arg);
45 extern void octeon_hal_setup_reserved32(void);
46 extern void octeon_user_io_init(void);
47 struct octeon_cop2_state;
48 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
49 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
50  unsigned long flags);
51 extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
52 
53 extern void octeon_init_cvmcount(void);
54 extern void octeon_setup_delays(void);
55 extern void octeon_io_clk_delay(unsigned long);
56 
57 #define OCTEON_ARGV_MAX_ARGS 64
58 #define OCTOEN_SERIAL_LEN 20
59 
61  /* Start of block referenced by assembly code - do not change! */
67  /* Only used by bootloader */
70  /* End of This block referenced by assembly code - do not change! */
74  /* Argc count for application. */
77 
78 #define BOOT_FLAG_INIT_CORE (1 << 0)
79 #define OCTEON_BL_FLAG_DEBUG (1 << 1)
80 #define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
81  /* If set, use uart1 for console */
82 #define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
83  /* If set, use PCI console */
84 #define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
85  /* Call exit on break on serial port */
86 #define OCTEON_BL_FLAG_BREAK (1 << 5)
87 
90  /* DRAM size in megabyes. */
92  /* physical address of free memory descriptor block. */
94  /* used to pass flags from app to debugger. */
96  /* CPU clock speed, in hz. */
98  /* DRAM clock speed, in hz. */
100  /* SPI4 clock in hz. */
112 };
113 
116  struct {
117  /* RO 1 = BIST fail, 0 = BIST pass */
119  /* RO 1 = BIST fail, 0 = BIST pass */
121  /* RO 1 = BIST fail, 0 = BIST pass */
123  /* RO 1 = BIST fail, 0 = BIST pass */
125  /* RO 1 = BIST fail, 0 = BIST pass */
127  /* RO 1 = BIST fail, 0 = BIST pass */
129  /* Reserved */
131  /* R/W If set, marked write-buffer entries time out
132  * the same as as other entries; if clear, marked
133  * write-buffer entries use the maximum timeout. */
135  /* R/W If set, a merged store does not clear the
136  * write-buffer entry timeout state. */
138  /* R/W Two bits that are the MSBs of the resultant
139  * CVMSEG LM word location for an IOBDMA. The other 8
140  * bits come from the SCRADDR field of the IOBDMA. */
142  /* R/W If set, SYNCWS and SYNCS only order marked
143  * stores; if clear, SYNCWS and SYNCS only order
144  * unmarked stores. SYNCWSMARKED has no effect when
145  * DISSYNCWS is set. */
147  /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
148  * SYNC. */
150  /* R/W If set, no stall happens on write buffer
151  * full. */
153  /* R/W If set (and SX set), supervisor-level
154  * loads/stores can use XKPHYS addresses with
155  * VA<48>==0 */
157  /* R/W If set (and UX set), user-level loads/stores
158  * can use XKPHYS addresses with VA<48>==0 */
160  /* R/W If set (and SX set), supervisor-level
161  * loads/stores can use XKPHYS addresses with
162  * VA<48>==1 */
164  /* R/W If set (and UX set), user-level loads/stores
165  * can use XKPHYS addresses with VA<48>==1 */
167  /* R/W If set, all stores act as SYNCW (NOMERGE must
168  * be set when this is set) RW, reset to 0. */
170  /* R/W If set, no stores merge, and all stores reach
171  * the coherent bus in order. */
173  /* R/W Selects the bit in the counter used for DID
174  * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
175  * 214. Actual time-out is between 1x and 2x this
176  * interval. For example, with DIDTTO=3, expiration
177  * interval is between 16K and 32K. */
179  /* R/W If set, the (mem) CSR clock never turns off. */
181  /* R/W If set, mclk never turns off. */
183  /* R/W Selects the bit in the counter used for write
184  * buffer flush time-outs (WBFLT+11) is the bit
185  * position in an internal counter used to determine
186  * expiration. The write buffer expires between 1x and
187  * 2x this interval. For example, with WBFLT = 0, a
188  * write buffer expires between 2K and 4K cycles after
189  * the write buffer entry is allocated. */
191  /* R/W If set, do not put Istream in the L2 cache. */
193  /* R/W The write buffer threshold. */
195  /* Reserved */
197  /* R/W If set, CVMSEG is available for loads/stores in
198  * kernel/debug mode. */
200  /* R/W If set, CVMSEG is available for loads/stores in
201  * supervisor mode. */
203  /* R/W If set, CVMSEG is available for loads/stores in
204  * user mode. */
206  /* R/W Size of local memory in cache blocks, 54 (6912
207  * bytes) is max legal value. */
209  } s;
210 };
211 
213  unsigned long base_region_bias;
214  unsigned int base_region; /* The chip select region used by CF */
215  int is16bit; /* 0 - 8bit, !0 - 16bit */
216  int dma_engine; /* -1 for no DMA */
217 };
218 
219 extern void octeon_write_lcd(const char *s);
220 extern void octeon_check_cpu_bist(void);
221 extern int octeon_get_boot_debug_flag(void);
222 extern int octeon_get_boot_uart(void);
223 
224 struct uart_port;
225 extern unsigned int octeon_serial_in(struct uart_port *, int);
226 extern void octeon_serial_out(struct uart_port *, int, int);
227 
234 static inline void octeon_npi_write32(uint64_t address, uint32_t val)
235 {
236  cvmx_write64_uint32(address ^ 4, val);
237  cvmx_read64_uint32(address ^ 4);
238 }
239 
240 
247 static inline uint32_t octeon_npi_read32(uint64_t address)
248 {
249  return cvmx_read64_uint32(address ^ 4);
250 }
251 
252 extern struct cvmx_bootinfo *octeon_bootinfo;
253 
255 
257 
260 
261 #endif /* __ASM_OCTEON_OCTEON_H */