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arch
mips
include
asm
octeon
octeon.h
Go to the documentation of this file.
1
/*
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* This file is subject to the terms and conditions of the GNU General Public
3
* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2008 Cavium Networks
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*/
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#ifndef __ASM_OCTEON_OCTEON_H
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#define __ASM_OCTEON_OCTEON_H
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#include <
asm/octeon/cvmx.h
>
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13
extern
uint64_t
octeon_bootmem_alloc_range_phys
(
uint64_t
size
,
14
uint64_t
alignment
,
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uint64_t
min_addr,
16
uint64_t
max_addr,
17
int
do_locking);
18
extern
void
*
octeon_bootmem_alloc
(
uint64_t
size
,
uint64_t
alignment
,
19
int
do_locking);
20
extern
void
*
octeon_bootmem_alloc_range
(
uint64_t
size
,
uint64_t
alignment
,
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uint64_t
min_addr,
uint64_t
max_addr,
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int
do_locking);
23
extern
void
*
octeon_bootmem_alloc_named
(
uint64_t
size
,
uint64_t
alignment
,
24
char
*
name
);
25
extern
void
*
octeon_bootmem_alloc_named_range
(
uint64_t
size
,
uint64_t
min_addr,
26
uint64_t
max_addr,
uint64_t
align
,
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char
*
name
);
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extern
void
*
octeon_bootmem_alloc_named_address
(
uint64_t
size
,
uint64_t
address
,
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char
*
name
);
30
extern
int
octeon_bootmem_free_named
(
char
*
name
);
31
extern
void
octeon_bootmem_lock
(
void
);
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extern
void
octeon_bootmem_unlock
(
void
);
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34
extern
int
octeon_is_simulation
(
void
);
35
extern
int
octeon_is_pci_host
(
void
);
36
extern
int
octeon_usb_is_ref_clk
(
void
);
37
extern
uint64_t
octeon_get_clock_rate
(
void
);
38
extern
u64
octeon_get_io_clock_rate
(
void
);
39
extern
const
char
*
octeon_board_type_string
(
void
);
40
extern
const
char
*
octeon_get_pci_interrupts
(
void
);
41
extern
int
octeon_get_southbridge_interrupt
(
void
);
42
extern
int
octeon_get_boot_coremask
(
void
);
43
extern
int
octeon_get_boot_num_arguments
(
void
);
44
extern
const
char
*
octeon_get_boot_argument
(
int
arg
);
45
extern
void
octeon_hal_setup_reserved32
(
void
);
46
extern
void
octeon_user_io_init
(
void
);
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struct
octeon_cop2_state;
48
extern
unsigned
long
octeon_crypto_enable
(
struct
octeon_cop2_state *
state
);
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extern
void
octeon_crypto_disable
(
struct
octeon_cop2_state *
state
,
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unsigned
long
flags
);
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extern
asmlinkage
void
octeon_cop2_restore
(
struct
octeon_cop2_state *
task
);
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extern
void
octeon_init_cvmcount
(
void
);
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extern
void
octeon_setup_delays
(
void
);
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extern
void
octeon_io_clk_delay
(
unsigned
long
);
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#define OCTEON_ARGV_MAX_ARGS 64
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#define OCTOEN_SERIAL_LEN 20
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struct
octeon_boot_descriptor
{
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/* Start of block referenced by assembly code - do not change! */
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uint32_t
desc_version
;
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uint32_t
desc_size
;
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uint64_t
stack_top
;
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uint64_t
heap_base
;
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uint64_t
heap_end
;
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/* Only used by bootloader */
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uint64_t
entry_point
;
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uint64_t
desc_vaddr
;
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/* End of This block referenced by assembly code - do not change! */
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uint32_t
exception_base_addr
;
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uint32_t
stack_size
;
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uint32_t
heap_size
;
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/* Argc count for application. */
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uint32_t
argc
;
76
uint32_t
argv
[
OCTEON_ARGV_MAX_ARGS
];
77
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#define BOOT_FLAG_INIT_CORE (1 << 0)
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#define OCTEON_BL_FLAG_DEBUG (1 << 1)
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#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
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/* If set, use uart1 for console */
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#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
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/* If set, use PCI console */
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#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
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/* Call exit on break on serial port */
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#define OCTEON_BL_FLAG_BREAK (1 << 5)
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uint32_t
flags
;
89
uint32_t
core_mask
;
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/* DRAM size in megabyes. */
91
uint32_t
dram_size
;
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/* physical address of free memory descriptor block. */
93
uint32_t
phy_mem_desc_addr
;
94
/* used to pass flags from app to debugger. */
95
uint32_t
debugger_flags_base_addr
;
96
/* CPU clock speed, in hz. */
97
uint32_t
eclock_hz
;
98
/* DRAM clock speed, in hz. */
99
uint32_t
dclock_hz
;
100
/* SPI4 clock in hz. */
101
uint32_t
spi_clock_hz
;
102
uint16_t
board_type
;
103
uint8_t
board_rev_major
;
104
uint8_t
board_rev_minor
;
105
uint16_t
chip_type
;
106
uint8_t
chip_rev_major
;
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uint8_t
chip_rev_minor
;
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char
board_serial_number
[
OCTOEN_SERIAL_LEN
];
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uint8_t
mac_addr_base
[6];
110
uint8_t
mac_addr_count
;
111
uint64_t
cvmx_desc_vaddr
;
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};
113
114
union
octeon_cvmemctl
{
115
uint64_t
u64
;
116
struct
{
117
/* RO 1 = BIST fail, 0 = BIST pass */
118
uint64_t
tlbbist
:1;
119
/* RO 1 = BIST fail, 0 = BIST pass */
120
uint64_t
l1cbist
:1;
121
/* RO 1 = BIST fail, 0 = BIST pass */
122
uint64_t
l1dbist
:1;
123
/* RO 1 = BIST fail, 0 = BIST pass */
124
uint64_t
dcmbist
:1;
125
/* RO 1 = BIST fail, 0 = BIST pass */
126
uint64_t
ptgbist
:1;
127
/* RO 1 = BIST fail, 0 = BIST pass */
128
uint64_t
wbfbist
:1;
129
/* Reserved */
130
uint64_t
reserved
:22;
131
/* R/W If set, marked write-buffer entries time out
132
* the same as as other entries; if clear, marked
133
* write-buffer entries use the maximum timeout. */
134
uint64_t
dismarkwblongto
:1;
135
/* R/W If set, a merged store does not clear the
136
* write-buffer entry timeout state. */
137
uint64_t
dismrgclrwbto
:1;
138
/* R/W Two bits that are the MSBs of the resultant
139
* CVMSEG LM word location for an IOBDMA. The other 8
140
* bits come from the SCRADDR field of the IOBDMA. */
141
uint64_t
iobdmascrmsb
:2;
142
/* R/W If set, SYNCWS and SYNCS only order marked
143
* stores; if clear, SYNCWS and SYNCS only order
144
* unmarked stores. SYNCWSMARKED has no effect when
145
* DISSYNCWS is set. */
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uint64_t
syncwsmarked
:1;
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/* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
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* SYNC. */
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uint64_t
dissyncws
:1;
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/* R/W If set, no stall happens on write buffer
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* full. */
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uint64_t
diswbfst
:1;
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/* R/W If set (and SX set), supervisor-level
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* loads/stores can use XKPHYS addresses with
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* VA<48>==0 */
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uint64_t
xkmemenas
:1;
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/* R/W If set (and UX set), user-level loads/stores
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* can use XKPHYS addresses with VA<48>==0 */
159
uint64_t
xkmemenau
:1;
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/* R/W If set (and SX set), supervisor-level
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* loads/stores can use XKPHYS addresses with
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* VA<48>==1 */
163
uint64_t
xkioenas
:1;
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/* R/W If set (and UX set), user-level loads/stores
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* can use XKPHYS addresses with VA<48>==1 */
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uint64_t
xkioenau
:1;
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/* R/W If set, all stores act as SYNCW (NOMERGE must
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* be set when this is set) RW, reset to 0. */
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uint64_t
allsyncw
:1;
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/* R/W If set, no stores merge, and all stores reach
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* the coherent bus in order. */
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uint64_t
nomerge
:1;
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/* R/W Selects the bit in the counter used for DID
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* time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
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* 214. Actual time-out is between 1x and 2x this
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* interval. For example, with DIDTTO=3, expiration
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* interval is between 16K and 32K. */
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uint64_t
didtto
:2;
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/* R/W If set, the (mem) CSR clock never turns off. */
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uint64_t
csrckalwys
:1;
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/* R/W If set, mclk never turns off. */
182
uint64_t
mclkalwys
:1;
183
/* R/W Selects the bit in the counter used for write
184
* buffer flush time-outs (WBFLT+11) is the bit
185
* position in an internal counter used to determine
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* expiration. The write buffer expires between 1x and
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* 2x this interval. For example, with WBFLT = 0, a
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* write buffer expires between 2K and 4K cycles after
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* the write buffer entry is allocated. */
190
uint64_t
wbfltime
:3;
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/* R/W If set, do not put Istream in the L2 cache. */
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uint64_t
istrnol2
:1;
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/* R/W The write buffer threshold. */
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uint64_t
wbthresh
:4;
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/* Reserved */
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uint64_t
reserved2
:2;
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/* R/W If set, CVMSEG is available for loads/stores in
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* kernel/debug mode. */
199
uint64_t
cvmsegenak
:1;
200
/* R/W If set, CVMSEG is available for loads/stores in
201
* supervisor mode. */
202
uint64_t
cvmsegenas
:1;
203
/* R/W If set, CVMSEG is available for loads/stores in
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* user mode. */
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uint64_t
cvmsegenau
:1;
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/* R/W Size of local memory in cache blocks, 54 (6912
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* bytes) is max legal value. */
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uint64_t
lmemsz
:6;
209
}
s
;
210
};
211
212
struct
octeon_cf_data
{
213
unsigned
long
base_region_bias
;
214
unsigned
int
base_region
;
/* The chip select region used by CF */
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int
is16bit
;
/* 0 - 8bit, !0 - 16bit */
216
int
dma_engine
;
/* -1 for no DMA */
217
};
218
219
extern
void
octeon_write_lcd
(
const
char
*
s
);
220
extern
void
octeon_check_cpu_bist
(
void
);
221
extern
int
octeon_get_boot_debug_flag
(
void
);
222
extern
int
octeon_get_boot_uart
(
void
);
223
224
struct
uart_port
;
225
extern
unsigned
int
octeon_serial_in
(
struct
uart_port
*,
int
);
226
extern
void
octeon_serial_out
(
struct
uart_port
*,
int
,
int
);
227
234
static
inline
void
octeon_npi_write32(
uint64_t
address
,
uint32_t
val
)
235
{
236
cvmx_write64_uint32(address ^ 4, val);
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cvmx_read64_uint32(address ^ 4);
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}
239
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247
static
inline
uint32_t
octeon_npi_read32(
uint64_t
address
)
248
{
249
return
cvmx_read64_uint32(address ^ 4);
250
}
251
252
extern
struct
cvmx_bootinfo
*
octeon_bootinfo
;
253
254
extern
uint64_t
octeon_bootloader_entry_addr
;
255
256
extern
void
(*
octeon_irq_setup_secondary
)(
void
);
257
258
typedef
void
(*
octeon_irq_ip4_handler_t
)(
void
);
259
void
octeon_irq_set_ip4_handler
(
octeon_irq_ip4_handler_t
);
260
261
#endif
/* __ASM_OCTEON_OCTEON_H */
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