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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | PCIU_BASE 0x0f000c00UL |
| #define | PCIU_SIZE 0x200UL |
| #define | PCIMMAW1REG 0x00 |
| #define | PCIMMAW2REG 0x04 |
| #define | PCITAW1REG 0x08 |
| #define | PCITAW2REG 0x0c |
| #define | PCIMIOAWREG 0x10 |
| #define | IBA(addr) ((addr) & 0xff000000U) |
| #define | MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U) |
| #define | PCIA(addr) (((addr) >> 24) & 0x000000ffU) |
| #define | TARGET_MSK(mask) (((mask) >> 8) & 0x000fe000U) |
| #define | ITA(addr) (((addr) >> 24) & 0x000000ffU) |
| #define | PCIIA(addr) (((addr) >> 24) & 0x000000ffU) |
| #define | WINEN 0x1000U |
| #define | PCICONFDREG 0x14 |
| #define | PCICONFAREG 0x18 |
| #define | PCIMAILREG 0x1c |
| #define | BUSERRADREG 0x24 |
| #define | EA(reg) ((reg) &0xfffffffc) |
| #define | INTCNTSTAREG 0x28 |
| #define | MABTCLR 0x80000000U |
| #define | TRDYCLR 0x40000000U |
| #define | PARCLR 0x20000000U |
| #define | MBCLR 0x10000000U |
| #define | SERRCLR 0x08000000U |
| #define | RTYCLR 0x04000000U |
| #define | MABCLR 0x02000000U |
| #define | TABCLR 0x01000000U |
| #define | MABTMSK 0x00008000U |
| #define | TRDYMSK 0x00004000U |
| #define | PARMSK 0x00002000U |
| #define | MBMSK 0x00001000U |
| #define | SERRMSK 0x00000800U |
| #define | RTYMSK 0x00000400U |
| #define | MABMSK 0x00000200U |
| #define | TABMSK 0x00000100U |
| #define | IBAMABT 0x00000080U |
| #define | TRDYRCH 0x00000040U |
| #define | PAR 0x00000020U |
| #define | MB 0x00000010U |
| #define | PCISERR 0x00000008U |
| #define | RTYRCH 0x00000004U |
| #define | MABORT 0x00000002U |
| #define | TABORT 0x00000001U |
| #define | PCIEXACCREG 0x2c |
| #define | UNLOCK 0x2U |
| #define | EAREQ 0x1U |
| #define | PCIRECONTREG 0x30 |
| #define | RTRYCNT(reg) ((reg) & 0x000000ffU) |
| #define | PCIENREG 0x34 |
| #define | PCIU_CONFIG_DONE 0x4U |
| #define | PCICLKSELREG 0x38 |
| #define | EQUAL_VTCLOCK 0x2U |
| #define | HALF_VTCLOCK 0x0U |
| #define | ONE_THIRD_VTCLOCK 0x3U |
| #define | QUARTER_VTCLOCK 0x1U |
| #define | PCITRDYVREG 0x3c |
| #define | TRDYV(val) ((uint32_t)(val) & 0xffU) |
| #define | PCICLKRUNREG 0x60 |
| #define | VENDORIDREG 0x100 |
| #define | DEVICEIDREG 0x100 |
| #define | COMMANDREG 0x104 |
| #define | STATUSREG 0x104 |
| #define | REVIDREG 0x108 |
| #define | CLASSREG 0x108 |
| #define | CACHELSREG 0x10c |
| #define | LATTIMEREG 0x10c |
| #define | MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U) |
| #define | MAILBAREG 0x110 |
| #define | PCIMBA1REG 0x114 |
| #define | PCIMBA2REG 0x118 |
| #define | MBADD(base) ((base) & 0xfffff800U) |
| #define | PMBA(base) ((base) & 0xffe00000U) |
| #define | PREF 0x8U |
| #define | PREF_APPROVAL 0x8U |
| #define | PREF_DISAPPROVAL 0x0U |
| #define | TYPE 0x6U |
| #define | TYPE_32BITSPACE 0x0U |
| #define | MSI 0x1U |
| #define | MSI_MEMORY 0x0U |
| #define | INTLINEREG 0x13c |
| #define | INTPINREG 0x13c |
| #define | RETVALREG 0x140 |
| #define | PCIAPCNTREG 0x140 |
| #define | TKYGNT 0x04000000U |
| #define | TKYGNT_ENABLE 0x04000000U |
| #define | TKYGNT_DISABLE 0x00000000U |
| #define | PAPC 0x03000000U |
| #define | PAPC_ALTERNATE_B 0x02000000U |
| #define | PAPC_ALTERNATE_0 0x01000000U |
| #define | PAPC_FAIR 0x00000000U |
| #define | RTYVAL(val) (((uint32_t)(val) << 7) & 0xff00U) |
| #define | RTYVAL_MASK 0xff00U |
| #define | PCI_CLOCK_MAX 33333333U |
| #define | PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U |
| #define | PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U |
| #define | PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U |
| #define | PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U |
| #define | PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U |
| #define | PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U |
| #define | PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U |
| #define | PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U |
| #define | PCI_MAILBOX_BASE_ADDRESS 0x00000000U |
| #define | PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U |
| #define | IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS) |
| #define | IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS |
| #define | IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK) |
| #define | PCI_IO_RESOURCE_START 0x01000000UL |
| #define | PCI_IO_RESOURCE_END 0x01ffffffUL |
| #define | PCI_MEM_RESOURCE_START 0x11000000UL |
| #define | PCI_MEM_RESOURCE_END 0x13ffffffUL |
| #define BUSERRADREG 0x24 |
Definition at line 43 of file pci-vr41xx.h.
| #define CACHELSREG 0x10c |
Definition at line 95 of file pci-vr41xx.h.
| #define CLASSREG 0x108 |
Definition at line 94 of file pci-vr41xx.h.
| #define COMMANDREG 0x104 |
Definition at line 91 of file pci-vr41xx.h.
| #define DEVICEIDREG 0x100 |
Definition at line 90 of file pci-vr41xx.h.
Definition at line 44 of file pci-vr41xx.h.
| #define EAREQ 0x1U |
Definition at line 75 of file pci-vr41xx.h.
| #define EQUAL_VTCLOCK 0x2U |
Definition at line 81 of file pci-vr41xx.h.
| #define HALF_VTCLOCK 0x0U |
Definition at line 82 of file pci-vr41xx.h.
Definition at line 33 of file pci-vr41xx.h.
| #define IBAMABT 0x00000080U |
Definition at line 64 of file pci-vr41xx.h.
| #define INTCNTSTAREG 0x28 |
Definition at line 46 of file pci-vr41xx.h.
| #define INTLINEREG 0x13c |
Definition at line 110 of file pci-vr41xx.h.
| #define INTPINREG 0x13c |
Definition at line 111 of file pci-vr41xx.h.
| #define IO_PORT_BASE KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS) |
Definition at line 144 of file pci-vr41xx.h.
| #define IO_PORT_RESOURCE_END (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK) |
Definition at line 146 of file pci-vr41xx.h.
| #define IO_PORT_RESOURCE_START PCI_MASTER_IO_PCI_BASE_ADDRESS |
Definition at line 145 of file pci-vr41xx.h.
Definition at line 37 of file pci-vr41xx.h.
| #define LATTIMEREG 0x10c |
Definition at line 96 of file pci-vr41xx.h.
| #define MABCLR 0x02000000U |
Definition at line 53 of file pci-vr41xx.h.
| #define MABMSK 0x00000200U |
Definition at line 62 of file pci-vr41xx.h.
| #define MABORT 0x00000002U |
Definition at line 70 of file pci-vr41xx.h.
| #define MABTCLR 0x80000000U |
Definition at line 47 of file pci-vr41xx.h.
| #define MABTMSK 0x00008000U |
Definition at line 56 of file pci-vr41xx.h.
| #define MAILBAREG 0x110 |
Definition at line 98 of file pci-vr41xx.h.
Definition at line 34 of file pci-vr41xx.h.
| #define MB 0x00000010U |
Definition at line 67 of file pci-vr41xx.h.
Definition at line 101 of file pci-vr41xx.h.
| #define MBCLR 0x10000000U |
Definition at line 50 of file pci-vr41xx.h.
| #define MBMSK 0x00001000U |
Definition at line 59 of file pci-vr41xx.h.
Definition at line 97 of file pci-vr41xx.h.
| #define MSI 0x1U |
Definition at line 108 of file pci-vr41xx.h.
| #define MSI_MEMORY 0x0U |
Definition at line 109 of file pci-vr41xx.h.
| #define ONE_THIRD_VTCLOCK 0x3U |
Definition at line 83 of file pci-vr41xx.h.
| #define PAPC 0x03000000U |
Definition at line 117 of file pci-vr41xx.h.
| #define PAPC_ALTERNATE_0 0x01000000U |
Definition at line 119 of file pci-vr41xx.h.
| #define PAPC_ALTERNATE_B 0x02000000U |
Definition at line 118 of file pci-vr41xx.h.
| #define PAPC_FAIR 0x00000000U |
Definition at line 120 of file pci-vr41xx.h.
| #define PAR 0x00000020U |
Definition at line 66 of file pci-vr41xx.h.
| #define PARCLR 0x20000000U |
Definition at line 49 of file pci-vr41xx.h.
| #define PARMSK 0x00002000U |
Definition at line 58 of file pci-vr41xx.h.
| #define PCI_CLOCK_MAX 33333333U |
Definition at line 124 of file pci-vr41xx.h.
| #define PCI_IO_RESOURCE_END 0x01ffffffUL |
Definition at line 149 of file pci-vr41xx.h.
| #define PCI_IO_RESOURCE_START 0x01000000UL |
Definition at line 148 of file pci-vr41xx.h.
| #define PCI_MAILBOX_BASE_ADDRESS 0x00000000U |
Definition at line 140 of file pci-vr41xx.h.
| #define PCI_MASTER_IO_ADDRESS_MASK 0x7e000000U |
Definition at line 137 of file pci-vr41xx.h.
| #define PCI_MASTER_IO_BUS_BASE_ADDRESS 0x16000000U |
Definition at line 136 of file pci-vr41xx.h.
| #define PCI_MASTER_IO_PCI_BASE_ADDRESS 0x00000000U |
Definition at line 138 of file pci-vr41xx.h.
| #define PCI_MASTER_MEM1_ADDRESS_MASK 0x7c000000U |
Definition at line 130 of file pci-vr41xx.h.
| #define PCI_MASTER_MEM1_BUS_BASE_ADDRESS 0x10000000U |
Definition at line 129 of file pci-vr41xx.h.
| #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS 0x10000000U |
Definition at line 131 of file pci-vr41xx.h.
| #define PCI_MEM_RESOURCE_END 0x13ffffffUL |
Definition at line 152 of file pci-vr41xx.h.
| #define PCI_MEM_RESOURCE_START 0x11000000UL |
Definition at line 151 of file pci-vr41xx.h.
| #define PCI_TARGET_MEM1_ADDRESS_MASK 0x08000000U |
Definition at line 133 of file pci-vr41xx.h.
| #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS 0x00000000U |
Definition at line 134 of file pci-vr41xx.h.
| #define PCI_TARGET_WINDOW1_BASE_ADDRESS 0x00000000U |
Definition at line 142 of file pci-vr41xx.h.
Definition at line 35 of file pci-vr41xx.h.
| #define PCIAPCNTREG 0x140 |
Definition at line 113 of file pci-vr41xx.h.
| #define PCICLKRUNREG 0x60 |
Definition at line 87 of file pci-vr41xx.h.
| #define PCICLKSELREG 0x38 |
Definition at line 80 of file pci-vr41xx.h.
| #define PCICONFAREG 0x18 |
Definition at line 41 of file pci-vr41xx.h.
| #define PCICONFDREG 0x14 |
Definition at line 40 of file pci-vr41xx.h.
| #define PCIENREG 0x34 |
Definition at line 78 of file pci-vr41xx.h.
| #define PCIEXACCREG 0x2c |
Definition at line 73 of file pci-vr41xx.h.
Definition at line 38 of file pci-vr41xx.h.
| #define PCIMAILREG 0x1c |
Definition at line 42 of file pci-vr41xx.h.
| #define PCIMBA1REG 0x114 |
Definition at line 99 of file pci-vr41xx.h.
| #define PCIMBA2REG 0x118 |
Definition at line 100 of file pci-vr41xx.h.
| #define PCIMIOAWREG 0x10 |
Definition at line 32 of file pci-vr41xx.h.
| #define PCIMMAW1REG 0x00 |
Definition at line 28 of file pci-vr41xx.h.
| #define PCIMMAW2REG 0x04 |
Definition at line 29 of file pci-vr41xx.h.
| #define PCIRECONTREG 0x30 |
Definition at line 76 of file pci-vr41xx.h.
| #define PCISERR 0x00000008U |
Definition at line 68 of file pci-vr41xx.h.
| #define PCITAW1REG 0x08 |
Definition at line 30 of file pci-vr41xx.h.
| #define PCITAW2REG 0x0c |
Definition at line 31 of file pci-vr41xx.h.
| #define PCITRDYVREG 0x3c |
Definition at line 85 of file pci-vr41xx.h.
| #define PCIU_BASE 0x0f000c00UL |
Definition at line 25 of file pci-vr41xx.h.
| #define PCIU_CONFIG_DONE 0x4U |
Definition at line 79 of file pci-vr41xx.h.
| #define PCIU_SIZE 0x200UL |
Definition at line 26 of file pci-vr41xx.h.
Definition at line 102 of file pci-vr41xx.h.
| #define PREF 0x8U |
Definition at line 103 of file pci-vr41xx.h.
| #define PREF_APPROVAL 0x8U |
Definition at line 104 of file pci-vr41xx.h.
| #define PREF_DISAPPROVAL 0x0U |
Definition at line 105 of file pci-vr41xx.h.
| #define QUARTER_VTCLOCK 0x1U |
Definition at line 84 of file pci-vr41xx.h.
| #define RETVALREG 0x140 |
Definition at line 112 of file pci-vr41xx.h.
| #define REVIDREG 0x108 |
Definition at line 93 of file pci-vr41xx.h.
Definition at line 77 of file pci-vr41xx.h.
| #define RTYCLR 0x04000000U |
Definition at line 52 of file pci-vr41xx.h.
| #define RTYMSK 0x00000400U |
Definition at line 61 of file pci-vr41xx.h.
| #define RTYRCH 0x00000004U |
Definition at line 69 of file pci-vr41xx.h.
Definition at line 121 of file pci-vr41xx.h.
| #define RTYVAL_MASK 0xff00U |
Definition at line 122 of file pci-vr41xx.h.
| #define SERRCLR 0x08000000U |
Definition at line 51 of file pci-vr41xx.h.
| #define SERRMSK 0x00000800U |
Definition at line 60 of file pci-vr41xx.h.
| #define STATUSREG 0x104 |
Definition at line 92 of file pci-vr41xx.h.
| #define TABCLR 0x01000000U |
Definition at line 54 of file pci-vr41xx.h.
| #define TABMSK 0x00000100U |
Definition at line 63 of file pci-vr41xx.h.
| #define TABORT 0x00000001U |
Definition at line 71 of file pci-vr41xx.h.
Definition at line 36 of file pci-vr41xx.h.
| #define TKYGNT 0x04000000U |
Definition at line 114 of file pci-vr41xx.h.
| #define TKYGNT_DISABLE 0x00000000U |
Definition at line 116 of file pci-vr41xx.h.
| #define TKYGNT_ENABLE 0x04000000U |
Definition at line 115 of file pci-vr41xx.h.
| #define TRDYCLR 0x40000000U |
Definition at line 48 of file pci-vr41xx.h.
| #define TRDYMSK 0x00004000U |
Definition at line 57 of file pci-vr41xx.h.
| #define TRDYRCH 0x00000040U |
Definition at line 65 of file pci-vr41xx.h.
Definition at line 86 of file pci-vr41xx.h.
| #define TYPE 0x6U |
Definition at line 106 of file pci-vr41xx.h.
| #define TYPE_32BITSPACE 0x0U |
Definition at line 107 of file pci-vr41xx.h.
| #define UNLOCK 0x2U |
Definition at line 74 of file pci-vr41xx.h.
| #define VENDORIDREG 0x100 |
Definition at line 89 of file pci-vr41xx.h.
| #define WINEN 0x1000U |
Definition at line 39 of file pci-vr41xx.h.
1.8.2