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12 #ifndef _ASM_PCI_BRIDGE_H
13 #define _ASM_PCI_BRIDGE_H
15 #include <linux/types.h>
16 #include <linux/pci.h>
18 #include <asm/sn/types.h>
24 #define IOPGSIZE (1 << IOPFNSHIFT)
25 #define IOPG(x) ((x) >> IOPFNSHIFT)
26 #define IOPGOFF(x) ((x) & (IOPGSIZE-1))
30 #define BRIDGE_ATE_RAM_SIZE 0x00000400
32 #define BRIDGE_CONFIG_BASE 0x20000
33 #define BRIDGE_CONFIG1_BASE 0x28000
34 #define BRIDGE_CONFIG_END 0x30000
35 #define BRIDGE_CONFIG_SLOT_SIZE 0x1000
37 #define BRIDGE_SSRAM_512K 0x00080000
38 #define BRIDGE_SSRAM_128K 0x00020000
39 #define BRIDGE_SSRAM_64K 0x00010000
40 #define BRIDGE_SSRAM_0K 0x00000000
76 #define b_wid_id b_widget.w_id
77 #define b_wid_stat b_widget.w_status
78 #define b_wid_err_upper b_widget.w_err_upper_addr
79 #define b_wid_err_lower b_widget.w_err_lower_addr
80 #define b_wid_control b_widget.w_control
81 #define b_wid_req_timeout b_widget.w_req_timeout
82 #define b_wid_int_upper b_widget.w_intdest_upper_addr
83 #define b_wid_int_lower b_widget.w_intdest_lower_addr
84 #define b_wid_err_cmdword b_widget.w_err_cmd_word
85 #define b_wid_llp b_widget.w_llp_cfg
86 #define b_wid_tflush b_widget.w_tflush
122 #define b_pci_bus_timeout b_bus_timeout
131 #define b_gio_err_lower b_pci_err_lower
132 #define b_gio_err_upper b_pci_err_upper
170 #define b_even_resp b_rrb_map[0].reg
171 #define b_odd_resp b_rrb_map[1].reg
253 #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)]
287 #define berr_field berr_un.berr_st
298 #define BRIDGE_WID_ID WIDGET_ID
299 #define BRIDGE_WID_STAT WIDGET_STATUS
300 #define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR
301 #define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR
302 #define BRIDGE_WID_CONTROL WIDGET_CONTROL
303 #define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT
304 #define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR
305 #define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR
306 #define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD
307 #define BRIDGE_WID_LLP WIDGET_LLP_CFG
308 #define BRIDGE_WID_TFLUSH WIDGET_TFLUSH
310 #define BRIDGE_WID_AUX_ERR 0x00005C
311 #define BRIDGE_WID_RESP_UPPER 0x000064
312 #define BRIDGE_WID_RESP_LOWER 0x00006C
313 #define BRIDGE_WID_TST_PIN_CTRL 0x000074
315 #define BRIDGE_DIR_MAP 0x000084
317 #define BRIDGE_RAM_PERR 0x000094
319 #define BRIDGE_ARB 0x0000A4
321 #define BRIDGE_NIC 0x0000B4
323 #define BRIDGE_BUS_TIMEOUT 0x0000C4
324 #define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT
325 #define BRIDGE_PCI_CFG 0x0000CC
326 #define BRIDGE_PCI_ERR_UPPER 0x0000D4
327 #define BRIDGE_PCI_ERR_LOWER 0x0000DC
329 #define BRIDGE_INT_STATUS 0x000104
330 #define BRIDGE_INT_ENABLE 0x00010C
331 #define BRIDGE_INT_RST_STAT 0x000114
332 #define BRIDGE_INT_MODE 0x00011C
333 #define BRIDGE_INT_DEVICE 0x000124
334 #define BRIDGE_INT_HOST_ERR 0x00012C
336 #define BRIDGE_INT_ADDR0 0x000134
337 #define BRIDGE_INT_ADDR_OFF 0x000008
338 #define BRIDGE_INT_ADDR(x) (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
340 #define BRIDGE_DEVICE0 0x000204
341 #define BRIDGE_DEVICE_OFF 0x000008
342 #define BRIDGE_DEVICE(x) (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
344 #define BRIDGE_WR_REQ_BUF0 0x000244
345 #define BRIDGE_WR_REQ_BUF_OFF 0x000008
346 #define BRIDGE_WR_REQ_BUF(x) (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
348 #define BRIDGE_EVEN_RESP 0x000284
349 #define BRIDGE_ODD_RESP 0x00028C
351 #define BRIDGE_RESP_STATUS 0x000294
352 #define BRIDGE_RESP_CLEAR 0x00029C
356 #define BRIDGE_ATE_RAM 0x00010000
358 #define BRIDGE_TYPE0_CFG_DEV0 0x00020000
359 #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000
360 #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100
361 #define BRIDGE_TYPE0_CFG_DEV(s) (BRIDGE_TYPE0_CFG_DEV0+\
362 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
363 #define BRIDGE_TYPE0_CFG_DEVF(s, f) (BRIDGE_TYPE0_CFG_DEV0+\
364 (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
365 (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
367 #define BRIDGE_TYPE1_CFG 0x00028000
369 #define BRIDGE_PCI_IACK 0x00030000
370 #define BRIDGE_EXT_SSRAM 0x00080000
374 #define BRIDGE_DEV_CNT 8
375 #define BRIDGE_DEVIO0 0x00200000
376 #define BRIDGE_DEVIO1 0x00400000
377 #define BRIDGE_DEVIO2 0x00600000
378 #define BRIDGE_DEVIO_OFF 0x00100000
380 #define BRIDGE_DEVIO_2MB 0x00200000
381 #define BRIDGE_DEVIO_1MB 0x00100000
383 #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
385 #define BRIDGE_EXTERNAL_FLASH 0x00C00000
392 #define BRIDGE_WIDGET_PART_NUM 0xc002
393 #define XBRIDGE_WIDGET_PART_NUM 0xd002
396 #define BRIDGE_WIDGET_MFGR_NUM 0x036
397 #define XBRIDGE_WIDGET_MFGR_NUM 0x024
400 #define BRIDGE_REV_A 0x1
401 #define BRIDGE_REV_B 0x2
402 #define BRIDGE_REV_C 0x3
403 #define BRIDGE_REV_D 0x4
407 #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24)
408 #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16)
409 #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6)
410 #define BRIDGE_STAT_PCI_GIO_N (0x1 << 5)
411 #define BRIDGE_STAT_PENDING (0x1F << 0)
414 #define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31)
415 #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30)
416 #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29)
417 #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28)
418 #define BRIDGE_CTRL_RST(n) ((n) << 24)
419 #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF))
420 #define BRIDGE_CTRL_RST_PIN(x) (BRIDGE_CTRL_RST(0x1 << (x)))
421 #define BRIDGE_CTRL_IO_SWAP (0x1 << 23)
422 #define BRIDGE_CTRL_MEM_SWAP (0x1 << 22)
423 #define BRIDGE_CTRL_PAGE_SIZE (0x1 << 21)
424 #define BRIDGE_CTRL_SS_PAR_BAD (0x1 << 20)
425 #define BRIDGE_CTRL_SS_PAR_EN (0x1 << 19)
426 #define BRIDGE_CTRL_SSRAM_SIZE(n) ((n) << 17)
427 #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3))
428 #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3))
429 #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2))
430 #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1))
431 #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0))
432 #define BRIDGE_CTRL_F_BAD_PKT (0x1 << 16)
433 #define BRIDGE_CTRL_LLP_XBAR_CRD(n) ((n) << 12)
434 #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
435 #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11)
436 #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10)
437 #define BRIDGE_CTRL_SYS_END (0x1 << 9)
438 #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4)
439 #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f))
440 #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0)
441 #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf))
444 #define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
445 #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
446 #define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
447 #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
448 #define BRIDGE_RESP_ERRRUPPR_BUFMASK (0xFFFF)
450 #define BRIDGE_RESP_ERRUPPR_BUFNUM(x) \
451 (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
452 BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
454 #define BRIDGE_RESP_ERRUPPR_DEVICE(x) \
455 (((x) & BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
456 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
459 #define BRIDGE_DIRMAP_W_ID_SHFT 20
460 #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
461 #define BRIDGE_DIRMAP_RMF_64 (0x1 << 18)
462 #define BRIDGE_DIRMAP_ADD512 (0x1 << 17)
463 #define BRIDGE_DIRMAP_OFF (0x1ffff << 0)
464 #define BRIDGE_DIRMAP_OFF_ADDRSHFT (31)
467 #define BRIDGE_ARB_REQ_WAIT_TICK(x) ((x) << 16)
468 #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3)
469 #define BRIDGE_ARB_REQ_WAIT_EN(x) ((x) << 8)
470 #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff)
471 #define BRIDGE_ARB_FREEZE_GNT (1 << 6)
472 #define BRIDGE_ARB_HPRI_RING_B2 (1 << 5)
473 #define BRIDGE_ARB_HPRI_RING_B1 (1 << 4)
474 #define BRIDGE_ARB_HPRI_RING_B0 (1 << 3)
475 #define BRIDGE_ARB_LPRI_RING_B2 (1 << 2)
476 #define BRIDGE_ARB_LPRI_RING_B1 (1 << 1)
477 #define BRIDGE_ARB_LPRI_RING_B0 (1 << 0)
480 #define BRIDGE_BUS_PCI_RETRY_HLD(x) ((x) << 16)
481 #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
482 #define BRIDGE_BUS_GIO_TIMEOUT (1 << 12)
483 #define BRIDGE_BUS_PCI_RETRY_CNT(x) ((x) << 0)
484 #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
487 #define BRIDGE_ISR_MULTI_ERR (0x1u << 31)
488 #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30)
489 #define BRIDGE_ISR_UNEXP_RESP (0x1 << 29)
490 #define BRIDGE_ISR_BAD_XRESP_PKT (0x1 << 28)
491 #define BRIDGE_ISR_BAD_XREQ_PKT (0x1 << 27)
492 #define BRIDGE_ISR_RESP_XTLK_ERR (0x1 << 26)
493 #define BRIDGE_ISR_REQ_XTLK_ERR (0x1 << 25)
494 #define BRIDGE_ISR_INVLD_ADDR (0x1 << 24)
495 #define BRIDGE_ISR_UNSUPPORTED_XOP (0x1 << 23)
496 #define BRIDGE_ISR_XREQ_FIFO_OFLOW (0x1 << 22)
497 #define BRIDGE_ISR_LLP_REC_SNERR (0x1 << 21)
498 #define BRIDGE_ISR_LLP_REC_CBERR (0x1 << 20)
499 #define BRIDGE_ISR_LLP_RCTY (0x1 << 19)
500 #define BRIDGE_ISR_LLP_TX_RETRY (0x1 << 18)
501 #define BRIDGE_ISR_LLP_TCTY (0x1 << 17)
502 #define BRIDGE_ISR_SSRAM_PERR (0x1 << 16)
503 #define BRIDGE_ISR_PCI_ABORT (0x1 << 15)
504 #define BRIDGE_ISR_PCI_PARITY (0x1 << 14)
505 #define BRIDGE_ISR_PCI_SERR (0x1 << 13)
506 #define BRIDGE_ISR_PCI_PERR (0x1 << 12)
507 #define BRIDGE_ISR_PCI_MST_TIMEOUT (0x1 << 11)
508 #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
509 #define BRIDGE_ISR_PCI_RETRY_CNT (0x1 << 10)
510 #define BRIDGE_ISR_XREAD_REQ_TIMEOUT (0x1 << 9)
511 #define BRIDGE_ISR_GIO_B_ENBL_ERR (0x1 << 8)
512 #define BRIDGE_ISR_INT_MSK (0xff << 0)
513 #define BRIDGE_ISR_INT(x) (0x1 << (x))
515 #define BRIDGE_ISR_LINK_ERROR \
516 (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR| \
517 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY| \
520 #define BRIDGE_ISR_PCIBUS_PIOERR \
521 (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
523 #define BRIDGE_ISR_PCIBUS_ERROR \
524 (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \
525 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \
526 BRIDGE_ISR_PCI_PARITY)
528 #define BRIDGE_ISR_XTALK_ERROR \
529 (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
530 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR| \
531 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR| \
532 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT| \
533 BRIDGE_ISR_UNEXP_RESP)
535 #define BRIDGE_ISR_ERRORS \
536 (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \
537 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \
538 BRIDGE_ISR_PMU_ESIZE_FAULT)
543 #define BRIDGE_ISR_ERROR_FATAL \
544 ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
545 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
547 #define BRIDGE_ISR_ERROR_DUMP \
548 (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \
549 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
552 #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP
553 #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT
554 #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT
555 #define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT
556 #define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR
557 #define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR
558 #define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR
559 #define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP
560 #define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW
561 #define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR
562 #define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR
563 #define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY
564 #define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY
565 #define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY
566 #define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR
567 #define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT
568 #define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY
569 #define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR
570 #define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR
571 #define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT
572 #define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT
573 #define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT
574 #define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT
575 #define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR
576 #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK
577 #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x)
580 #define BRIDGE_IRR_MULTI_CLR (0x1 << 6)
581 #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5)
582 #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4)
583 #define BRIDGE_IRR_REQ_DSP_GRP_CLR (0x1 << 3)
584 #define BRIDGE_IRR_LLP_GRP_CLR (0x1 << 2)
585 #define BRIDGE_IRR_SSRAM_GRP_CLR (0x1 << 1)
586 #define BRIDGE_IRR_PCI_GRP_CLR (0x1 << 0)
587 #define BRIDGE_IRR_GIO_GRP_CLR (0x1 << 0)
588 #define BRIDGE_IRR_ALL_CLR 0x7f
590 #define BRIDGE_IRR_CRP_GRP (BRIDGE_ISR_UNEXP_RESP | \
591 BRIDGE_ISR_XREQ_FIFO_OFLOW)
592 #define BRIDGE_IRR_RESP_BUF_GRP (BRIDGE_ISR_BAD_XRESP_PKT | \
593 BRIDGE_ISR_RESP_XTLK_ERR | \
594 BRIDGE_ISR_XREAD_REQ_TIMEOUT)
595 #define BRIDGE_IRR_REQ_DSP_GRP (BRIDGE_ISR_UNSUPPORTED_XOP | \
596 BRIDGE_ISR_BAD_XREQ_PKT | \
597 BRIDGE_ISR_REQ_XTLK_ERR | \
598 BRIDGE_ISR_INVLD_ADDR)
599 #define BRIDGE_IRR_LLP_GRP (BRIDGE_ISR_LLP_REC_SNERR | \
600 BRIDGE_ISR_LLP_REC_CBERR | \
601 BRIDGE_ISR_LLP_RCTY | \
602 BRIDGE_ISR_LLP_TX_RETRY | \
604 #define BRIDGE_IRR_SSRAM_GRP (BRIDGE_ISR_SSRAM_PERR | \
605 BRIDGE_ISR_PMU_ESIZE_FAULT)
606 #define BRIDGE_IRR_PCI_GRP (BRIDGE_ISR_PCI_ABORT | \
607 BRIDGE_ISR_PCI_PARITY | \
608 BRIDGE_ISR_PCI_SERR | \
609 BRIDGE_ISR_PCI_PERR | \
610 BRIDGE_ISR_PCI_MST_TIMEOUT | \
611 BRIDGE_ISR_PCI_RETRY_CNT)
613 #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \
614 BRIDGE_ISR_GIO_MST_TIMEOUT)
617 #define BRIDGE_INT_DEV_SHFT(n) ((n)*3)
618 #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n))
619 #define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
622 #define BRIDGE_INT_ADDR_HOST 0x0003FF00
623 #define BRIDGE_INT_ADDR_FLD 0x000000FF
625 #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000
626 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000
627 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff
629 #define BRIDGE_TMO_PCI_RETRY_CNT_MAX 0x3ff
635 #define BRIDGE_INT_ADDR_NASID_SHFT 8
641 #define BRIDGE_INT_ADDR_DEST_IO (1 << 17)
642 #define BRIDGE_INT_ADDR_DEST_MEM 0
643 #define BRIDGE_INT_ADDR_MASK (1 << 17)
646 #define BRIDGE_DEV_ERR_LOCK_EN 0x10000000
647 #define BRIDGE_DEV_PAGE_CHK_DIS 0x08000000
648 #define BRIDGE_DEV_FORCE_PCI_PAR 0x04000000
649 #define BRIDGE_DEV_VIRTUAL_EN 0x02000000
650 #define BRIDGE_DEV_PMU_WRGA_EN 0x01000000
651 #define BRIDGE_DEV_DIR_WRGA_EN 0x00800000
652 #define BRIDGE_DEV_DEV_SIZE 0x00400000
653 #define BRIDGE_DEV_RT 0x00200000
654 #define BRIDGE_DEV_SWAP_PMU 0x00100000
655 #define BRIDGE_DEV_SWAP_DIR 0x00080000
656 #define BRIDGE_DEV_PREF 0x00040000
657 #define BRIDGE_DEV_PRECISE 0x00020000
658 #define BRIDGE_DEV_COH 0x00010000
659 #define BRIDGE_DEV_BARRIER 0x00008000
660 #define BRIDGE_DEV_GBR 0x00004000
661 #define BRIDGE_DEV_DEV_SWAP 0x00002000
662 #define BRIDGE_DEV_DEV_IO_MEM 0x00001000
663 #define BRIDGE_DEV_OFF_MASK 0x00000fff
664 #define BRIDGE_DEV_OFF_ADDR_SHFT 20
666 #define BRIDGE_DEV_PMU_BITS (BRIDGE_DEV_PMU_WRGA_EN | \
668 #define BRIDGE_DEV_D32_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
669 BRIDGE_DEV_SWAP_DIR | \
671 BRIDGE_DEV_PRECISE | \
674 #define BRIDGE_DEV_D64_BITS (BRIDGE_DEV_DIR_WRGA_EN | \
675 BRIDGE_DEV_SWAP_DIR | \
680 #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20)
681 #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19)
682 #define BRIDGE_ERRUPPR_DEVNUM_SHFT (16)
683 #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
684 #define BRIDGE_ERRUPPR_DEVICE(err) (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
685 #define BRIDGE_ERRUPPR_ADDRMASK (0xFFFF)
688 #define BRIDGE_INTMODE_CLR_PKT_EN(x) (0x1 << (x))
691 #define BRIDGE_CREDIT 3
694 #define BRIDGE_RRB_EN 0x8
695 #define BRIDGE_RRB_DEV 0x7
696 #define BRIDGE_RRB_VDEV 0x4
697 #define BRIDGE_RRB_PDEV 0x3
700 #define BRIDGE_RRB_VALID(r) (0x00010000<<(r))
701 #define BRIDGE_RRB_INUSE(r) (0x00000001<<(r))
704 #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r))
707 #define XBOX_BRIDGE_WID 8
708 #define FLASH_PROM1_BASE 0xE00000
709 #define XBOX_RPS_EXISTS 1 << 6
710 #define XBOX_RPS_FAIL 1 << 4
719 #define BRIDGE_PIO32_XTALK_ALIAS_BASE 0x000040000000L
720 #define BRIDGE_PIO32_XTALK_ALIAS_LIMIT 0x00007FFFFFFFL
721 #define BRIDGE_PIO64_XTALK_ALIAS_BASE 0x000080000000L
722 #define BRIDGE_PIO64_XTALK_ALIAS_LIMIT 0x0000BFFFFFFFL
723 #define BRIDGE_PCIIO_XTALK_ALIAS_BASE 0x000100000000L
724 #define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT 0x0001FFFFFFFFL
727 #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000
728 #define BRIDGE_MAX_PIO_ADDR_MEM 0x3fffffff
729 #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000
730 #define BRIDGE_MAX_PIO_ADDR_IO 0xffffffff
733 #define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
734 #define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
735 #define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE
736 #define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT
737 #define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE
738 #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
744 #define BRIDGE_LOCAL_BASE 0
745 #define BRIDGE_DMA_MAPPED_BASE 0x40000000
746 #define BRIDGE_DMA_MAPPED_SIZE 0x40000000
747 #define BRIDGE_DMA_DIRECT_BASE 0x80000000
748 #define BRIDGE_DMA_DIRECT_SIZE 0x80000000
750 #define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE
753 #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
754 #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
756 #define IS_PCI32_LOCAL(x) ((ulong_t)(x) < PCI32_MAPPED_BASE)
757 #define IS_PCI32_MAPPED(x) ((ulong_t)(x) < PCI32_DIRECT_BASE && \
758 (ulong_t)(x) >= PCI32_MAPPED_BASE)
759 #define IS_PCI32_DIRECT(x) ((ulong_t)(x) >= PCI32_MAPPED_BASE)
760 #define IS_PCI64(x) ((ulong_t)(x) >= PCI64_BASE)
766 #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE
767 #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT
769 #define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE
772 #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE
773 #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE
775 #define IS_GIO_LOCAL(x) ((ulong_t)(x) < GIO_MAPPED_BASE)
776 #define IS_GIO_MAPPED(x) ((ulong_t)(x) < GIO_DIRECT_BASE && \
777 (ulong_t)(x) >= GIO_MAPPED_BASE)
778 #define IS_GIO_DIRECT(x) ((ulong_t)(x) >= GIO_MAPPED_BASE)
785 #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE
786 #define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr) \
787 ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE + \
788 ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
791 #define PCI64_ATTR_TARG_MASK 0xf000000000000000
792 #define PCI64_ATTR_TARG_SHFT 60
793 #define PCI64_ATTR_PREF 0x0800000000000000
794 #define PCI64_ATTR_PREC 0x0400000000000000
795 #define PCI64_ATTR_VIRTUAL 0x0200000000000000
796 #define PCI64_ATTR_BAR 0x0100000000000000
797 #define PCI64_ATTR_RMF_MASK 0x00ff000000000000
798 #define PCI64_ATTR_RMF_SHFT 48
820 #define ATE_PREC 0x04
821 #define ATE_PREF 0x08
824 #define ATE_PFNSHIFT 12
825 #define ATE_TIDSHIFT 8
826 #define ATE_RMFSHIFT 48
828 #define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
829 ((xid)<<ATE_TIDSHIFT) | \
832 #define BRIDGE_INTERNAL_ATES 128
846 #define BRIDGE_CONTROLLER(bus) \
847 ((struct bridge_controller *)((bus)->sysdata))