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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/types.h>#include <linux/pci.h>#include <asm/xtalk/xwidget.h>#include <asm/sn/types.h>Go to the source code of this file.
Data Structures | |
| struct | bridge_s |
| struct | bridge_err_cmdword_s |
| union | ate_u |
| struct | ate_u::ate_s |
| struct | bridge_controller |
Typedefs | |
| typedef u32 | bridgereg_t |
| typedef u64 | bridge_ate_t |
| typedef volatile bridge_ate_t * | bridge_ate_p |
| typedef struct bridge_s | bridge_t |
| typedef struct bridge_err_cmdword_s | bridge_err_cmdword_t |
| typedef union ate_u | ate_t |
Functions | |
| void | register_bridge_irq (unsigned int irq) |
| int | request_bridge_irq (struct bridge_controller *bc) |
Variables | |
| struct pci_ops | bridge_pci_ops |
| #define BRIDGE_ARB_REQ_WAIT_EN_MASK BRIDGE_ARB_REQ_WAIT_EN(0xff) |
| #define BRIDGE_ARB_REQ_WAIT_TICK_MASK BRIDGE_ARB_REQ_WAIT_TICK(0x3) |
| #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ |
| #define BRIDGE_BUS_PCI_RETRY_HLD_MASK BRIDGE_BUS_PCI_RETRY_HLD(0x1f) |
| #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) |
| #define BRIDGE_BUS_TIMEOUT 0x0000C4 /* Bus Timeout Register */ |
| #define BRIDGE_CONTROLLER | ( | bus | ) | ((struct bridge_controller *)((bus)->sysdata)) |
| #define BRIDGE_CTRL_LLP_XBAR_CRD_MASK (BRIDGE_CTRL_LLP_XBAR_CRD(0xf)) |
| #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) |
| #define BRIDGE_CTRL_RST_MASK (BRIDGE_CTRL_RST(0xF)) |
| #define BRIDGE_CTRL_RST_PIN | ( | x | ) | (BRIDGE_CTRL_RST(0x1 << (x))) |
| #define BRIDGE_CTRL_SSRAM_128K (BRIDGE_CTRL_SSRAM_SIZE(0x2)) |
| #define BRIDGE_CTRL_SSRAM_1K (BRIDGE_CTRL_SSRAM_SIZE(0x0)) |
| #define BRIDGE_CTRL_SSRAM_512K (BRIDGE_CTRL_SSRAM_SIZE(0x3)) |
| #define BRIDGE_CTRL_SSRAM_64K (BRIDGE_CTRL_SSRAM_SIZE(0x1)) |
| #define BRIDGE_CTRL_SSRAM_SIZE_MASK (BRIDGE_CTRL_SSRAM_SIZE(0x3)) |
| #define BRIDGE_CTRL_WIDGET_ID_MASK (BRIDGE_CTRL_WIDGET_ID(0xf)) |
| #define BRIDGE_DEV_D32_BITS |
| #define BRIDGE_DEV_D64_BITS |
| #define BRIDGE_DEV_PMU_BITS |
| #define BRIDGE_DEVICE | ( | x | ) | (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF) |
| #define BRIDGE_DEVICE_OFF 0x000008 /* Device offset (1..7) */ |
| #define BRIDGE_DEVIO | ( | x | ) | ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) |
| #define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ |
| #define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ |
| #define BRIDGE_DEVIO_OFF 0x00100000 /* Device IO Offset (3..7) */ |
| #define BRIDGE_DIRECT_32_SEG_SIZE BRIDGE_DMA_DIRECT_SIZE |
| #define BRIDGE_DIRECT_32_TO_XTALK | ( | dir_off, | |
| adr | |||
| ) |
| #define BRIDGE_DIRMAP_W_ID (0xf << BRIDGE_DIRMAP_W_ID_SHFT) |
| #define BRIDGE_ERRUPPR_DEVICE | ( | err | ) | (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7) |
| #define BRIDGE_ERRUPPR_DEVMASTER (0x1 << 20) /* Device was master */ |
| #define BRIDGE_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT) |
| #define BRIDGE_ERRUPPR_PCIVDEV (0x1 << 19) /* Virtual Req value */ |
| #define BRIDGE_EVEN_RESP 0x000284 /* Even Device Response Buf */ |
| #define BRIDGE_EXT_SSRAM 0x00080000 /* Extern SSRAM (ATE) */ |
| #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ |
| #define BRIDGE_GIO_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE |
| #define BRIDGE_GIO_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT |
| #define BRIDGE_IMR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT |
| #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT |
| #define BRIDGE_IMR_GIO_B_ENBL_ERR BRIDGE_ISR_GIO_B_ENBL_ERR |
| #define BRIDGE_IMR_GIO_MST_TIMEOUT BRIDGE_ISR_GIO_MST_TIMEOUT |
| #define BRIDGE_IMR_INT | ( | x | ) | BRIDGE_ISR_INT(x) |
| #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK |
| #define BRIDGE_IMR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR |
| #define BRIDGE_IMR_LLP_RCTY BRIDGE_ISR_LLP_RCTY |
| #define BRIDGE_IMR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR |
| #define BRIDGE_IMR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR |
| #define BRIDGE_IMR_LLP_TCTY BRIDGE_ISR_LLP_TCTY |
| #define BRIDGE_IMR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY |
| #define BRIDGE_IMR_PCI_ABORT BRIDGE_ISR_PCI_ABORT |
| #define BRIDGE_IMR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT |
| #define BRIDGE_IMR_PCI_PARITY BRIDGE_ISR_PCI_PARITY |
| #define BRIDGE_IMR_PCI_PERR BRIDGE_ISR_PCI_PERR |
| #define BRIDGE_IMR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT |
| #define BRIDGE_IMR_PCI_SERR BRIDGE_ISR_PCI_SERR |
| #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT |
| #define BRIDGE_IMR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR |
| #define BRIDGE_IMR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR |
| #define BRIDGE_IMR_SSRAM_PERR BRIDGE_ISR_SSRAM_PERR |
| #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP |
| #define BRIDGE_IMR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP |
| #define BRIDGE_IMR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT |
| #define BRIDGE_IMR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW |
| #define BRIDGE_INT_ADDR | ( | x | ) | (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF) |
| #define BRIDGE_INT_ADDR_OFF 0x000008 /* Host Addr offset (1..7) */ |
| #define BRIDGE_INT_DEV_MASK | ( | n | ) | (0x7 << BRIDGE_INT_DEV_SHFT(n)) |
| #define BRIDGE_INT_DEV_SET | ( | _dev, | |
| _line | |||
| ) | (_dev << BRIDGE_INT_DEV_SHFT(_line)) |
| #define BRIDGE_INT_HOST_ERR 0x00012C /* Host Error Field */ |
| #define BRIDGE_INT_RST_STAT 0x000114 /* Reset Intr Status */ |
| #define BRIDGE_IRR_CRP_GRP |
| #define BRIDGE_IRR_GIO_GRP |
| #define BRIDGE_IRR_LLP_GRP |
| #define BRIDGE_IRR_PCI_GRP |
| #define BRIDGE_IRR_REQ_DSP_GRP |
| #define BRIDGE_IRR_RESP_BUF_GRP |
| #define BRIDGE_IRR_SSRAM_GRP |
| #define BRIDGE_ISR_ERROR_DUMP |
| #define BRIDGE_ISR_ERROR_FATAL |
| #define BRIDGE_ISR_ERRORS |
| #define BRIDGE_ISR_GIO_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT |
| #define BRIDGE_ISR_LINK_ERROR |
| #define BRIDGE_ISR_PCIBUS_ERROR |
| #define BRIDGE_ISR_PCIBUS_PIOERR (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) |
| #define BRIDGE_ISR_XTALK_ERROR |
| #define BRIDGE_MIN_PIO_ADDR_IO 0x00000000 /* 4G PCI IO space */ |
| #define BRIDGE_MIN_PIO_ADDR_MEM 0x00000000 /* 1G PCI memory space */ |
| #define BRIDGE_ODD_RESP 0x00028C /* Odd Device Response Buf */ |
| #define BRIDGE_PCI_BUS_TIMEOUT BRIDGE_BUS_TIMEOUT |
| #define BRIDGE_PCI_CFG 0x0000CC /* PCI Type 1 Config reg */ |
| #define BRIDGE_PCI_ERR_LOWER 0x0000DC /* PCI error Lower Addr */ |
| #define BRIDGE_PCI_ERR_UPPER 0x0000D4 /* PCI error Upper Addr */ |
| #define BRIDGE_PCI_IO_BASE BRIDGE_PCIIO_XTALK_ALIAS_BASE |
| #define BRIDGE_PCI_IO_LIMIT BRIDGE_PCIIO_XTALK_ALIAS_LIMIT |
| #define BRIDGE_PCI_MEM32_BASE BRIDGE_PIO32_XTALK_ALIAS_BASE |
| #define BRIDGE_PCI_MEM32_LIMIT BRIDGE_PIO32_XTALK_ALIAS_LIMIT |
| #define BRIDGE_PCI_MEM64_BASE BRIDGE_PIO64_XTALK_ALIAS_BASE |
| #define BRIDGE_PCI_MEM64_LIMIT BRIDGE_PIO64_XTALK_ALIAS_LIMIT |
| #define BRIDGE_RESP_CLEAR 0x00029C /* Read Response Clear reg */ |
| #define BRIDGE_RESP_ERRUPPR_BUFNUM | ( | x | ) |
| #define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT) |
| #define BRIDGE_RESP_ERRUPPR_DEVICE | ( | x | ) |
| #define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT) |
| #define BRIDGE_RESP_STATUS 0x000294 /* Read Response Status reg */ |
| #define BRIDGE_TYPE0_CFG_DEV | ( | s | ) |
| #define BRIDGE_TYPE0_CFG_DEV0 0x00020000 /* Type 0 Cfg, Device 0 */ |
| #define BRIDGE_TYPE0_CFG_FUNC_OFF 0x00000100 /* Type 0 Cfg Func Offset (1..7) */ |
| #define BRIDGE_TYPE0_CFG_SLOT_OFF 0x00001000 /* Type 0 Cfg Slot Offset (1..7) */ |
| #define BRIDGE_WID_AUX_ERR 0x00005C /* Aux Error Command Word */ |
| #define BRIDGE_WID_CONTROL WIDGET_CONTROL |
| #define BRIDGE_WID_ERR_CMDWORD WIDGET_ERR_CMD_WORD |
| #define BRIDGE_WID_ERR_LOWER WIDGET_ERR_LOWER_ADDR |
| #define BRIDGE_WID_ERR_UPPER WIDGET_ERR_UPPER_ADDR |
| #define BRIDGE_WID_INT_LOWER WIDGET_INTDEST_LOWER_ADDR |
| #define BRIDGE_WID_INT_UPPER WIDGET_INTDEST_UPPER_ADDR |
| #define BRIDGE_WID_LLP WIDGET_LLP_CFG |
| #define BRIDGE_WID_REQ_TIMEOUT WIDGET_REQ_TIMEOUT |
| #define BRIDGE_WID_RESP_LOWER 0x00006C /* Response Buf Lower Addr */ |
| #define BRIDGE_WID_RESP_UPPER 0x000064 /* Response Buf Upper Addr */ |
| #define BRIDGE_WID_STAT WIDGET_STATUS |
| #define BRIDGE_WID_TFLUSH WIDGET_TFLUSH |
| #define BRIDGE_WID_TST_PIN_CTRL 0x000074 /* Test pin control */ |
| #define BRIDGE_WR_REQ_BUF | ( | x | ) | (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF) |
| #define BRIDGE_WR_REQ_BUF0 0x000244 /* Write Request Buffer 0 */ |
| #define BRIDGE_WR_REQ_BUF_OFF 0x000008 /* Buffer Offset (1..7) */ |
| #define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ |
| #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE |
| #define GIO_LOCAL_BASE BRIDGE_LOCAL_BASE |
| #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE |
| #define IOPG | ( | x | ) | ((x) >> IOPFNSHIFT) |
| #define IOPGSIZE (1 << IOPFNSHIFT) |
| #define IS_GIO_DIRECT | ( | x | ) | ((ulong_t)(x) >= GIO_MAPPED_BASE) |
| #define IS_GIO_LOCAL | ( | x | ) | ((ulong_t)(x) < GIO_MAPPED_BASE) |
| #define IS_GIO_MAPPED | ( | x | ) |
| #define IS_PCI32_DIRECT | ( | x | ) | ((ulong_t)(x) >= PCI32_MAPPED_BASE) |
| #define IS_PCI32_LOCAL | ( | x | ) | ((ulong_t)(x) < PCI32_MAPPED_BASE) |
| #define IS_PCI32_MAPPED | ( | x | ) |
| #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE |
| #define PCI32_LOCAL_BASE BRIDGE_LOCAL_BASE |
| #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE |
| typedef volatile bridge_ate_t* bridge_ate_p |
| typedef u64 bridge_ate_t |
| typedef u32 bridgereg_t |
Definition at line 339 of file ip27-irq.c.
| int request_bridge_irq | ( | struct bridge_controller * | bc | ) |
Definition at line 344 of file ip27-irq.c.
Definition at line 319 of file ops-bridge.c.
1.8.2