pcie-sh7786.h File Reference

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Macros
#define	SH4A_PCIE_SPW_BASE   0xFE000000 /* spw config address for controller 0 */
#define	SH4A_PCIE_SPW_BASE1   0xFE200000 /* spw config address for controller 1 (Rev1.14)*/
#define	SH4A_PCIE_SPW_BASE2   0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/
#define	SH4A_PCIE_SPW_BASE_LEN   0x00080000
#define	SH4A_PCI_CNFG_BASE   0xFE040000 /* pci config address for controller 0 */
#define	SH4A_PCI_CNFG_BASE1   0xFE240000 /* pci config address for controller 1 (Rev1.14)*/
#define	SH4A_PCI_CNFG_BASE2   0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/
#define	SH4A_PCI_CNFG_BASE_LEN   0x00040000
#define	SH4A_PCIPIO_ADDR_OFFSET   0x000001c0 /* offset to pci config_address */
#define	SH4A_PCIPIO_DATA_OFFSET   0x00000220 /* offset to pci config_data */
#define	SH4A_PCIBMSTR_TRANSLATION   0x20000000
#define	SH4A_PCIEVCR0   (0x000000) /* R - 0x0000 0000 32 */
#define	BITS_TOP_MB   (24)
#define	MASK_TOP_MB   (0xff<<BITS_TOP_MB)
#define	BITS_BOT_MB   (16)
#define	MASK_BOT_MB   (0xff<<BITS_BOT_MB)
#define	BITS_VC_ID   (0)
#define	MASK_VC_ID   (0xffff<<BITS_VC_ID)
#define	SH4A_PCIEVCR1   (0x000004) /* R - 0x0000 0000 32*/
#define	BITS_BADOPC   (5) /* 5 BADOPC 0 R/W */
#define	MASK_BADOPC   (1<<BITS_BADOPC)
#define	BITS_BADDEST   (4) /*4 BADDEST 0 R/W */
#define	MASK_BADDEST   (1<<BITS_BADDEST)
#define	BITS_UNSOLRESP   (3) /* 3 UNSOLRESP 0 R/W */
#define	MASK_UNSOLRESP   (1<<BITS_UNSOLRESP)
#define	BITS_ERRSNT   (1) /* 1 ERRSNT 0 */
#define	MASK_ERRSNT   (1<<BITS_ERRSNT)
#define	BITS_ERRRCV   (0) /* 0 ERRRCV 0 */
#define	MASK_ERRRCV   (1<<BITS_ERRRCV)
#define	SH4A_PCIEENBLR   (0x000008) /* R/W - 0x0000 0001 32 */
#define	SH4A_PCIEECR   (0x00000C) /* R/W - 0x0000 0000 32 */
#define	BITS_ENBL   (0) /* 0 ENBL 0 R/W */
#define	MASK_ENBL   (1<<BITS_ENBL)
#define	SH4A_PCIEPAR   (0x000010) /* R/W - 0x0000 0000 32 */
#define	BITS_BN   (24)
#define	MASK_BN   (0xff<<BITS_BN)
#define	BITS_DN   (19)
#define	MASK_DN   (0x1f<<BITS_DN)
#define	BITS_FN   (16)
#define	MASK_FN   (0x7<<BITS_FN)
#define	BITS_EREGNO   (8)
#define	MASK_EREGNO   (0xff<<BITS_EREGNO)
#define	BITS_REGNO   (2)
#define	MASK_REGNO   (0x3f<<BITS_REGNO)
#define	SH4A_PCIEPCTLR   (0x000018) /* R/W - 0x0000 0000 32 */
#define	BITS_CCIE   (31) /* 31 CCIE */
#define	MASK_CCIE   (1<<BITS_CCIE)
#define	BITS_TYPE   (8)
#define	MASK_TYPE   (1<<BITS_TYPE)
#define	BITS_C_VC   (0)
#define	MASK_C_VC   (1<<BITS_C_VC)
#define	SH4A_PCIEPDR   (0x000020) /* R/W - 0x0000 0000 32 */
#define	BITS_PDR   (0)
#define	MASK_PDR   (0xffffffff<<BITS_PDR)
#define	SH4A_PCIEMSGALR   (0x000030) /* R/W - 0x0000 0000 32 */
#define	BITS_MSGADRL   (0)
#define	MASK_MSGADRL   (0xffffffff<<BITS_MSGADRL)
#define	SH4A_PCIEMSGAHR   (0x000034) /* R/W - 0x0000 0000 32 */
#define	BITS_MSGADRH   (0)
#define	MASK_MSGADRH   (0xffffffff<<BITS_MSGADRH)
#define	SH4A_PCIEMSGCTLR   (0x000038) /* R/W - 0x0000 0000 32 */
#define	BITS_MSGIE   (31)
#define	MASK_MSGIE   (1<<BITS_MSGIE)
#define	BITS_MROUTE   (16)
#define	MASK_MROUTE   (0x7<<BITS_MROUTE)
#define	BITS_MCODE   (8)
#define	MASK_MCODE   (0xff<<BITS_MCODE)
#define	BITS_M_VC   (0)
#define	MASK_M_VC   (1<<BITS_M_VC)
#define	SH4A_PCIEMSG   (0x000040) /* W - - 32 */
#define	BITS_MDATA   (0)
#define	MASK_MDATA   (0xffffffff<<BITS_MDATA)
#define	SH4A_PCIEUNLOCKCR   (0x000048) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEIDR   (0x000060) /* R/W - 0x0101 1101 32 */
#define	SH4A_PCIEDBGCTLR   (0x000100) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEINTXR   (0x004000) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIERMSGR   (0x004010) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIERSTR(x)   (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIESRSTR   (0x008040) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPHYCTLR   (0x010000) /* R/W - 0x0000 0000 32 */
#define	BITS_CKE   (0)
#define	MASK_CKE   (1<<BITS_CKE)
#define	SH4A_PCIERMSGIER   (0x004040) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPHYCTLR   (0x010000) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPHYADRR   (0x010004) /* R/W - 0x0000 0000 32 */
#define	BITS_ACK   (24)
#define	MASK_ACK   (1<<BITS_ACK)
#define	BITS_CMD   (16)
#define	MASK_CMD   (0x03<<BITS_CMD)
#define	BITS_LANE   (8)
#define	MASK_LANE   (0x0f<<BITS_LANE)
#define	BITS_ADR   (0)
#define	MASK_ADR   (0xff<<BITS_ADR)
#define	SH4A_PCIEPHYDINR   (0x010008) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPHYDOUTR   (0x01000C) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPHYSR   (0x010010) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPHYDATAR   (0x00008) /* R/W - 0xxxxx xxxx 32 */
#define	BITS_DATA   (0)
#define	MASK_DATA   (0xffffffff<<BITS_DATA)
#define	SH4A_PCIETCTLR   (0x020000) /* R/W R/W 0x0000 0000 32 */
#define	BITS_CFINT   (0)
#define	MASK_CFINT   (1<<BITS_CFINT)
#define	SH4A_PCIETSTR   (0x020004) /* R 0x0000 0000 32 */
#define	SH4A_PCIEINTR   (0x020008) /* R/W R/W 0x0000 0000 32 */
#define	BITS_INT_RX_ERP   (31)
#define	MASK_INT_RX_ERP   (1<<BITS_INT_RX_ERP)
#define	BITS_INT_RX_VCX_Posted   (30)
#define	MASK_INT_RX_VCX_Posted   (1<<BITS_INT_RX_VCX_Posted)
#define	BITS_INT_RX_VCX_NonPosted   (29)
#define	MASK_INT_RX_VCX_NonPosted   (1<<BITS_INT_RX_VCX_NonPosted)
#define	BITS_INT_RX_VCX_CPL   (28)
#define	MASK_INT_RX_VCX_CPL   (1<<BITS_INT_RX_VCX_CPL)
#define	BITS_INT_TX_VCX_Posted   (26)
#define	MASK_INT_TX_VCX_Posted   (1<<BITS_INT_TX_VCX_Posted)
#define	BITS_INT_TX_VCX_NonPosted   (25)
#define	MASK_INT_TX_VCX_NonPosted   (1<<BITS_INT_TX_VCX_NonPosted)
#define	BITS_INT_TX_VCX_CPL   (24)
#define	MASK_INT_TX_VCX_CPL   (1<<BITS_INT_TX_VCX_CPL)
#define	BITS_INT_RX_VC0_Posted   (22)
#define	MASK_INT_RX_VC0_Posted   (1<<BITS_INT_RX_VC0_Posted)
#define	BITS_INT_RX_VC0_NonPosted   (21)
#define	MASK_INT_RX_VC0_NonPosted   (1<<BITS_INT_RX_VC0_NonPosted)
#define	BITS_INT_RX_VC0_CPL   (20)
#define	MASK_INT_RX_VC0_CPL   (1<<BITS_INT_RX_VC0_CPL)
#define	BITS_INT_TX_VC0_Posted   (18)
#define	MASK_INT_TX_VC0_Posted   (1<<BITS_INT_TX_VC0_Posted)
#define	BITS_INT_TX_VC0_NonPosted   (17)
#define	MASK_INT_TX_VC0_NonPosted   (1<<BITS_INT_TX_VC0_NonPosted)
#define	BITS_INT_TX_VC0_CPL   (16)
#define	MASK_INT_TX_VC0_CPL   (1<<BITS_INT_TX_VC0_CPL)
#define	BITS_INT_RX_CTRL   (15)
#define	MASK_INT_RX_CTRL   (1<<BITS_INT_RX_CTRL)
#define	BITS_INT_TX_CTRL   (14)
#define	MASK_INT_TX_CTRL   (1<<BITS_INT_TX_CTRL)
#define	BITS_INTTL   (11)
#define	MASK_INTTL   (1<<BITS_INTTL)
#define	BITS_INTDL   (10)
#define	MASK_INTDL   (1<<BITS_INTDL)
#define	BITS_INTMAC   (9)
#define	MASK_INTMAC   (1<<BITS_INTMAC)
#define	BITS_INTPM   (8)
#define	MASK_INTPM   (1<<BITS_INTPM)
#define	SH4A_PCIEINTER   (0x02000C) /* R/W R/W 0x0000 0000 32 */
#define	BITS_INT_RX_ERP   (31)
#define	MASK_INT_RX_ERP   (1<<BITS_INT_RX_ERP)
#define	BITS_INT_RX_VCX_Posted   (30)
#define	MASK_INT_RX_VCX_Posted   (1<<BITS_INT_RX_VCX_Posted)
#define	BITS_INT_RX_VCX_NonPosted   (29)
#define	MASK_INT_RX_VCX_NonPosted   (1<<BITS_INT_RX_VCX_NonPosted)
#define	BITS_INT_RX_VCX_CPL   (28)
#define	MASK_INT_RX_VCX_CPL   (1<<BITS_INT_RX_VCX_CPL)
#define	BITS_INT_TX_VCX_Posted   (26)
#define	MASK_INT_TX_VCX_Posted   (1<<BITS_INT_TX_VCX_Posted)
#define	BITS_INT_TX_VCX_NonPosted   (25)
#define	MASK_INT_TX_VCX_NonPosted   (1<<BITS_INT_TX_VCX_NonPosted)
#define	BITS_INT_TX_VCX_CPL   (24)
#define	MASK_INT_TX_VCX_CPL   (1<<BITS_INT_TX_VCX_CPL)
#define	BITS_INT_RX_VC0_Posted   (22)
#define	MASK_INT_RX_VC0_Posted   (1<<BITS_INT_RX_VC0_Posted)
#define	BITS_INT_RX_VC0_NonPosted   (21)
#define	MASK_INT_RX_VC0_NonPosted   (1<<BITS_INT_RX_VC0_NonPosted)
#define	BITS_INT_RX_VC0_CPL   (20)
#define	MASK_INT_RX_VC0_CPL   (1<<BITS_INT_RX_VC0_CPL)
#define	BITS_INT_TX_VC0_Posted   (18)
#define	MASK_INT_TX_VC0_Posted   (1<<BITS_INT_TX_VC0_Posted)
#define	BITS_INT_TX_VC0_NonPosted   (17)
#define	MASK_INT_TX_VC0_NonPosted   (1<<BITS_INT_TX_VC0_NonPosted)
#define	BITS_INT_TX_VC0_CPL   (16)
#define	MASK_INT_TX_VC0_CPL   (1<<BITS_INT_TX_VC0_CPL)
#define	BITS_INT_RX_CTRL   (15)
#define	MASK_INT_RX_CTRL   (1<<BITS_INT_RX_CTRL)
#define	BITS_INT_TX_CTRL   (14)
#define	MASK_INT_TX_CTRL   (1<<BITS_INT_TX_CTRL)
#define	BITS_INTTL   (11)
#define	MASK_INTTL   (1<<BITS_INTTL)
#define	BITS_INTDL   (10)
#define	MASK_INTDL   (1<<BITS_INTDL)
#define	BITS_INTMAC   (9)
#define	MASK_INTMAC   (1<<BITS_INTMAC)
#define	BITS_INTPM   (8)
#define	MASK_INTPM   (1<<BITS_INTPM)
#define	SH4A_PCIEEHR(x)   (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
#define	SH4A_PCIEAIR   (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
#define	SH4A_PCIECIR   (SH4A_PCIE_BASE) /* R/W R/W 0xxxxx xxxx 32 */
#define	SH4A_PCIEERRFR   (0x020020) /* R/W R/W 0xxxxx xxxx 32 */
#define	SH4A_PCIEERRFER   (0x020024) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEERRFR2   (0x020028) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEMSIR   (0x020040) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEMSIFR   (0x020044) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEPWRCTLR   (0x020100) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEPCCTLR   (0x020180) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIELAR0   (0x020200) /* R/W R/W 0x0000 0000 32 */
#define	BITS_LARn   (20)
#define	MASK_LARn   (0xfff<<BITS_LARn)
#define	SH4A_PCIE_020204   (0x020204) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAMR0   (0x020208) /* R/W R/W 0x0000 0000 32 */
#define	BITS_LAMRn   (20)
#define	MASK_LAMRn   (0x1ff<<BITS_LAMRn)
#define	BITS_LAREn   (0)
#define	MASK_LAREn   (0x1<<BITS_LAREn)
#define	SH4A_PCIECSCR0   (0x020210) /* R/W R/W 0x0000 0000 32 */
#define	BITS_RANGE   (2)
#define	MASK_RANGE   (0x7<<BITS_RANGE)
#define	BITS_SNPMD   (0)
#define	MASK_SNPMD   (0x3<<BITS_SNPMD)
#define	SH4A_PCIECSAR0   (0x020214) /* R/W R/W 0x0000 0000 32 */
#define	BITS_CSADR   (0)
#define	MASK_CSADR   (0xffffffff<<BITS_CSADR)
#define	SH4A_PCIESTCTLR0   (0x020218) /* R/W R/W 0x0000 0000 32 */
#define	BITS_SHPRI   (8)
#define	MASK_SHPRI   (0x0f<<BITS_SHPRI)
#define	SH4A_PCIE_020224   (0x020224) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAR1   (0x020220) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAMR1   (0x020228) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSCR1   (0x020230) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSAR1   (0x020234) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIESTCTLR1   (0x020238) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAR2   (0x020240) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIE_020244   (0x020244) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAMR2   (0x020248) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSCR2   (0x020250) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSAR2   (0x020254) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIESTCTLR2   (0x020258) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAR3   (0x020260) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIE_020264   (0x020264) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAMR3   (0x020268) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSCR3   (0x020270) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSAR3   (0x020274) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIESTCTLR3   (0x020278) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAR4   (0x020280) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIE_020284   (0x020284) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAMR4   (0x020288) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSCR4   (0x020290) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSAR4   (0x020294) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIESTCTLR4   (0x020298) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAR5   (0x0202A0) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIE_0202A4   (0x0202A4) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIELAMR5   (0x0202A8) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSCR5   (0x0202B0) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIECSAR5   (0x0202B4) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIESTCTLR5   (0x0202B8) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEPARL(x)   (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define	BITS_PAL   (18)
#define	MASK_PAL   (0x3fff<<BITS_PAL)
#define	SH4A_PCIEPARH(x)   (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define	BITS_PAH   (0)
#define	MASK_PAH   (0xffffffff<<BITS_PAH)
#define	SH4A_PCIEPAMR(x)   (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
#define	BITS_PAM   (18)
#define	MASK_PAM   (0x3fff<<BITS_PAM)
#define	SH4A_PCIEPTCTLR(x)   (0x02040C + ((x) * 0x20))
#define	BITS_PARE   (31)
#define	MASK_PARE   (0x1<<BITS_PARE)
#define	BITS_TC   (20)
#define	MASK_TC   (0x7<<BITS_TC)
#define	BITS_T_VC   (16)
#define	MASK_T_VC   (0x1<<BITS_T_VC)
#define	BITS_LOCK   (12)
#define	MASK_LOCK   (0x1<<BITS_LOCK)
#define	BITS_SPC   (8)
#define	MASK_SPC   (0x1<<BITS_SPC)
#define	SH4A_PCIEDMAOR   (0x021000) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSAR0   (0x021100) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSAHR0   (0x021104) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAR0   (0x021108) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAHR0   (0x02110C) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMBCNTR0   (0x021110) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSBCNTR0   (0x021114) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSTRR0   (0x021118) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCAR0   (0x02111C) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCR0   (0x021120) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCC2R0   (0x021124) /* R/W R/W 0x0000 0000 - */
#define	SH4A_PCIEDMCCCR0   (0x021128) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCHSR0   (0x02112C) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEDMSAR1   (0x021140) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSAHR1   (0x021144) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAR1   (0x021148) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAHR1   (0x02114C) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMBCNTR1   (0x021150) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSBCNTR1   (0x021154) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSTRR1   (0x021158) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCAR1   (0x02115C) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCR1   (0x021160) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCC2R1   (0x021164) /* R/W R/W 0x0000 0000 - */
#define	SH4A_PCIEDMCCCR1   (0x021168) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCHSR1   (0x02116C) /* R/W - 0x0000 0000 32 */
#define	SH4A_PCIEDMSAR2   (0x021180) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSAHR2   (0x021184) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAR2   (0x021188) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAHR2   (0x02118C) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMBCNTR2   (0x021190) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSBCNTR2   (0x021194) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSTRR2   (0x021198) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCAR2   (0x02119C) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCR2   (0x0211A0) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCC2R2   (0x0211A4) /* R/W R/W 0x0000 0000 - */
#define	SH4A_PCIEDMCCCR2   (0x0211A8) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSAR3   (0x0211C0) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSAHR3   (0x0211C4) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAR3   (0x0211C8) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMDAHR3   (0x0211CC) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMBCNTR3   (0x0211D0) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSBCNTR3   (0x0211D4) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMSTRR3   (0x0211D8) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCAR3   (0x0211DC) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCCR3   (0x0211E0) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCC2R3   (0x0211E4) /* R/W R/W 0x0000 0000 - */
#define	SH4A_PCIEDMCCCR3   (0x0211E8) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEDMCHSR3   (0x0211EC) /* R/W R/W 0x0000 0000 32 */
#define	SH4A_PCIEPCICONF0   (0x040000) /* R R - 8/16/32 */
#define	SH4A_PCIEPCICONF1   (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
#define	SH4A_PCIEPCICONF2   (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */
#define	SH4A_PCIEPCICONF3   (0x04000C) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEPCICONF4   (0x040010) /* - R/W - 8/16/32 */
#define	SH4A_PCIEPCICONF5   (0x040014) /* - R/W - 8/16/32 */
#define	SH4A_PCIEPCICONF6   (0x040018) /* - R/W - 8/16/32 */
#define	SH4A_PCIEPCICONF7   (0x04001C) /* - R/W - 8/16/32 */
#define	SH4A_PCIEPCICONF8   (0x040020) /* - R/W - 8/16/32 */
#define	SH4A_PCIEPCICONF9   (0x040024) /* - R/W - 8/16/32 */
#define	SH4A_PCIEPCICONF10   (0x040028) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEPCICONF11   (0x04002C) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEPCICONF12   (0x040030) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEPCICONF13   (0x040034) /* R/W R/W 0x0000 0040 8/16/32 */
#define	SH4A_PCIEPCICONF14   (0x040038) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEPCICONF15   (0x04003C) /* R/W R/W 0x0000 00FF 8/16/32 */
#define	SH4A_PCIEPMCAP0   (0x040040) /* R/W R 0x0003 5001 8/16/32 */
#define	SH4A_PCIEPMCAP1   (0x040044) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEMSICAP0   (0x040050) /* R/W R/W 0x0180 7005 8/16/32 */
#define	SH4A_PCIEMSICAP1   (0x040054) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEMSICAP2   (0x040058) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEMSICAP3   (0x04005C) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEMSICAP4   (0x040060) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEMSICAP5   (0x040064) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEEXPCAP0   (0x040070) /* R/W R/W 0x0001 0010 8/16/32 */
#define	SH4A_PCIEEXPCAP1   (0x040074) /* R/W R 0x0000 0005 8/16/32 */
#define	SH4A_PCIEEXPCAP2   (0x040078) /* R/W R/W 0x0000 0801 8/16/32 */
#define	SH4A_PCIEEXPCAP3   (0x04007C) /* R/W R 0x0003 F421 8/16/32 */
#define	SH4A_PCIEEXPCAP4   (0x040080) /* R/W R/W 0x0041 0000 8/16/32 */
#define	SH4A_PCIEEXPCAP5   (0x040084) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEEXPCAP6   (0x040088) /* R/W R/W 0x0000 03C0 8/16/32 */
#define	SH4A_PCIEEXPCAP7   (0x04008C) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEEXPCAP8   (0x040090) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEVCCAP0   (0x040100) /* R/W R 0x1B01 0002 8/16/32 */
#define	SH4A_PCIEVCCAP1   (0x040104) /* R R 0x0000 0001 8/16/32 */
#define	SH4A_PCIEVCCAP2   (0x040108) /* R R 0x0000 0000 8/16/32 */
#define	SH4A_PCIEVCCAP3   (0x04010C) /* R R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEVCCAP4   (0x040110) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEVCCAP5   (0x040114) /* R/W R/W 0x8000 00FF 8/16/32 */
#define	SH4A_PCIEVCCAP6   (0x040118) /* R/W R 0x0002 0000 8/16/32 */
#define	SH4A_PCIEVCCAP7   (0x04011C) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEVCCAP8   (0x040120) /* R/W R/W 0x0000 0000 8/16/32 */
#define	SH4A_PCIEVCCAP9   (0x040124) /* R/W R 0x0002 0000 8/16/32 */
#define	SH4A_PCIENUMCAP0   (0x0001B0) /* RW R 0x0001 0003 8/16/32 */
#define	SH4A_PCIENUMCAP1   (0x0001B4) /* R R 0x0000 0000 8/16/32 */
#define	SH4A_PCIENUMCAP2   (0x0001B8) /* R R 0x0000 0000 8/16/32 */
#define	SH4A_PCIEIDSETR0   (0x041000) /* R/W R 0x0000 FFFF 16/32 */
#define	SH4A_PCIEIDSETR1   (0x041004) /* R/W R 0xFF00 0000 16/32 */
#define	SH4A_PCIEBAR0SETR   (0x041008) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEBAR1SETR   (0x04100C) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEBAR2SETR   (0x041010) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEBAR3SETR   (0x041014) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEBAR4SETR   (0x041018) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEBAR5SETR   (0x04101C) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIECISSETR   (0x041020) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEIDSETR2   (0x041024) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEEROMSETR   (0x041028) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEDSERSETR0   (0x04102C) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEDSERSETR1   (0x041030) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIECTLR   (0x041040) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIETLSR   (0x041044) /* R/W1C R 0x0000 0000 16/32 */
#define	SH4A_PCIETLCTLR   (0x041048) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEDLSR   (0x04104C) /* R/W1C R 0x4003 0000 16/32 */
#define	SH4A_PCIEDLCTLR   (0x041050) /* R R 0x0000 0000 16/32 */
#define	SH4A_PCIEMACSR   (0x041054) /* R/W1C R 0x0041 0000 16/32 */
#define	SH4A_PCIEMACCTLR   (0x041058) /* R/W R 0x0000 0000 16/32 */
#define	PCIEMACCTLR_SCR_DIS   (1 << 27) /* scramble disable */
#define	SH4A_PCIEPMSTR   (0x04105C) /* R/W1C R 0x0000 0000 16/32 */
#define	SH4A_PCIEPMCTLR   (0x041060) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIETLINTENR   (0x041064) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEDLINTENR   (0x041068) /* R/W R 0x0000 0000 16/32 */
#define	PCIEDLINTENR_DLL_ACT_ENABLE   (1 << 31) /* DL active irq */
#define	SH4A_PCIEMACINTENR   (0x04106C) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIEPMINTENR   (0x041070) /* R/W R 0x0000 0000 16/32 */
#define	SH4A_PCIETXDCTLR   (0x044000) /* R/W - H'00000000_00000000 32/64 */
#define	SH4A_PCIETXCTLR   (0x044020) /* R/W - H'00000000_00000000 32/64 */
#define	SH4A_PCIETXSR   (0x044028) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIETXVC0DCTLR   (0x044100) /* R/W - H'00000000_00000000 32/64 */
#define	SH4A_PCIETXVC0SR   (0x044108) /* R/W - H'00888000_00000000 32/64 */
#define	SH4A_PCIEVC0PDTXR   (0x044110) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0PHTXR   (0x044118) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0NPDTXR   (0x044120) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0NPHTXR   (0x044128) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0CDTXR   (0x044130) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0CHTXR   (0x044138) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIETXVCXDCTLR   (0x044200) /* R/W - H'00000000_00000000 32/64 */
#define	SH4A_PCIETXVCXSR   (0x044208) /* R/W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXPDTXR   (0x044210) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXPHTXR   (0x044218) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXNPDTXR   (0x044220) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXNPHTXR   (0x044228) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXCDTXR   (0x044230) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXCHTXR   (0x044238) /* W - H'00000000_00000000 32/64 */
#define	SH4A_PCIERDCTLR   (0x046000) /* RW - H'00000000_00000000 32/64 */
#define	SH4A_PCIEERPCTLR   (0x046008) /* RW - H'00000000_00000000 32/64 */
#define	SH4A_PCIEERPHR   (0x046010) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEERPERR   (0x046018) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIERXVC0DCTLR   (0x046100) /* RW - H'00000000_00000000 32/64 */
#define	SH4A_PCIERXVC0SR   (0x046108) /* RW - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0PDRXR   (0x046140) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0PHRXR   (0x046148) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0PERR   (0x046150) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0NPDRXR   (0x046158) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0NPHRXR   (0x046160) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0NPERR   (0x046168) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0CDRXR   (0x046170) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0CHRXR   (0x046178) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVC0CERR   (0x046180) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIERXVCXDCTLR   (0x046200) /* RW - H'00000000_00000000 32/64 */
#define	SH4A_PCIERXVCXSR   (0x046208) /* RW - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXPDRXR   (0x046240) /* R - H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXPHRXR   (0x046248) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXPERR   (0x046250) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXNPDRXR   (0x046258) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXNPHRXR   (0x046260) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXNPERR   (0x046268) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXCDRXR   (0x046270) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXCHRXR   (0x046278) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCIEVCXCERR   (0x046280) /* R H'00000000_00000000 32/64 */
#define	SH4A_PCI_SSI_BASE   0xFFE00000 /* spw config address */
#define	SH4A_PCI_SSI_BASE_LEN   0x00100000 /* 1MB */
#define	SH4A_SSICR0   (0x000000)
#define	SH4A_SSICR1   (0x010000)
#define	SH4A_SSICR2   (0x020000)
#define	SH4A_SSICR3   (0x030000)
#define	PCI_REG(x)   ((x) + 0x40000)

Macro Definition Documentation

#define BITS_ACK   (24)

Definition at line 153 of file pcie-sh7786.h.

#define BITS_ADR   (0)

Definition at line 159 of file pcie-sh7786.h.

#define BITS_BADDEST   (4) /*4 BADDEST 0 R/W */

Definition at line 49 of file pcie-sh7786.h.

#define BITS_BADOPC   (5) /* 5 BADOPC 0 R/W */

Definition at line 47 of file pcie-sh7786.h.

#define BITS_BN   (24)

Definition at line 68 of file pcie-sh7786.h.

#define BITS_BOT_MB   (16)

Definition at line 40 of file pcie-sh7786.h.

#define BITS_C_VC   (0)

Definition at line 85 of file pcie-sh7786.h.

#define BITS_CCIE   (31) /* 31 CCIE */

Definition at line 81 of file pcie-sh7786.h.

#define BITS_CFINT   (0)

Definition at line 178 of file pcie-sh7786.h.

#define BITS_CKE   (0)

Definition at line 142 of file pcie-sh7786.h.

#define BITS_CMD   (16)

Definition at line 155 of file pcie-sh7786.h.

#define BITS_CSADR   (0)

Definition at line 320 of file pcie-sh7786.h.

#define BITS_DATA   (0)

Definition at line 173 of file pcie-sh7786.h.

#define BITS_DN   (19)

Definition at line 70 of file pcie-sh7786.h.

#define BITS_ENBL   (0) /* 0 ENBL 0 R/W */

Definition at line 63 of file pcie-sh7786.h.

#define BITS_EREGNO   (8)

Definition at line 74 of file pcie-sh7786.h.

#define BITS_ERRRCV   (0) /* 0 ERRRCV 0 */

Definition at line 55 of file pcie-sh7786.h.

#define BITS_ERRSNT   (1) /* 1 ERRSNT 0 */

Definition at line 53 of file pcie-sh7786.h.

#define BITS_FN   (16)

Definition at line 72 of file pcie-sh7786.h.

#define BITS_INT_RX_CTRL   (15)

Definition at line 253 of file pcie-sh7786.h.

#define BITS_INT_RX_CTRL   (15)

Definition at line 253 of file pcie-sh7786.h.

#define BITS_INT_RX_ERP   (31)

Definition at line 227 of file pcie-sh7786.h.

#define BITS_INT_RX_ERP   (31)

Definition at line 227 of file pcie-sh7786.h.

#define BITS_INT_RX_VC0_CPL   (20)

Definition at line 245 of file pcie-sh7786.h.

#define BITS_INT_RX_VC0_CPL   (20)

Definition at line 245 of file pcie-sh7786.h.

#define BITS_INT_RX_VC0_NonPosted   (21)

Definition at line 243 of file pcie-sh7786.h.

#define BITS_INT_RX_VC0_NonPosted   (21)

Definition at line 243 of file pcie-sh7786.h.

#define BITS_INT_RX_VC0_Posted   (22)

Definition at line 241 of file pcie-sh7786.h.

#define BITS_INT_RX_VC0_Posted   (22)

Definition at line 241 of file pcie-sh7786.h.

#define BITS_INT_RX_VCX_CPL   (28)

Definition at line 233 of file pcie-sh7786.h.

#define BITS_INT_RX_VCX_CPL   (28)

Definition at line 233 of file pcie-sh7786.h.

#define BITS_INT_RX_VCX_NonPosted   (29)

Definition at line 231 of file pcie-sh7786.h.

#define BITS_INT_RX_VCX_NonPosted   (29)

Definition at line 231 of file pcie-sh7786.h.

#define BITS_INT_RX_VCX_Posted   (30)

Definition at line 229 of file pcie-sh7786.h.

#define BITS_INT_RX_VCX_Posted   (30)

Definition at line 229 of file pcie-sh7786.h.

#define BITS_INT_TX_CTRL   (14)

Definition at line 255 of file pcie-sh7786.h.

#define BITS_INT_TX_CTRL   (14)

Definition at line 255 of file pcie-sh7786.h.

#define BITS_INT_TX_VC0_CPL   (16)

Definition at line 251 of file pcie-sh7786.h.

#define BITS_INT_TX_VC0_CPL   (16)

Definition at line 251 of file pcie-sh7786.h.

#define BITS_INT_TX_VC0_NonPosted   (17)

Definition at line 249 of file pcie-sh7786.h.

#define BITS_INT_TX_VC0_NonPosted   (17)

Definition at line 249 of file pcie-sh7786.h.

#define BITS_INT_TX_VC0_Posted   (18)

Definition at line 247 of file pcie-sh7786.h.

#define BITS_INT_TX_VC0_Posted   (18)

Definition at line 247 of file pcie-sh7786.h.

#define BITS_INT_TX_VCX_CPL   (24)

Definition at line 239 of file pcie-sh7786.h.

#define BITS_INT_TX_VCX_CPL   (24)

Definition at line 239 of file pcie-sh7786.h.

#define BITS_INT_TX_VCX_NonPosted   (25)

Definition at line 237 of file pcie-sh7786.h.

#define BITS_INT_TX_VCX_NonPosted   (25)

Definition at line 237 of file pcie-sh7786.h.

#define BITS_INT_TX_VCX_Posted   (26)

Definition at line 235 of file pcie-sh7786.h.

#define BITS_INT_TX_VCX_Posted   (26)

Definition at line 235 of file pcie-sh7786.h.

#define BITS_INTDL   (10)

Definition at line 259 of file pcie-sh7786.h.

#define BITS_INTDL   (10)

Definition at line 259 of file pcie-sh7786.h.

#define BITS_INTMAC   (9)

Definition at line 261 of file pcie-sh7786.h.

#define BITS_INTMAC   (9)

Definition at line 261 of file pcie-sh7786.h.

#define BITS_INTPM   (8)

Definition at line 263 of file pcie-sh7786.h.

#define BITS_INTPM   (8)

Definition at line 263 of file pcie-sh7786.h.

#define BITS_INTTL   (11)

Definition at line 257 of file pcie-sh7786.h.

#define BITS_INTTL   (11)

Definition at line 257 of file pcie-sh7786.h.

#define BITS_LAMRn   (20)

Definition at line 306 of file pcie-sh7786.h.

#define BITS_LANE   (8)

Definition at line 157 of file pcie-sh7786.h.

#define BITS_LAREn   (0)

Definition at line 308 of file pcie-sh7786.h.

#define BITS_LARn   (20)

Definition at line 299 of file pcie-sh7786.h.

#define BITS_LOCK   (12)

Definition at line 387 of file pcie-sh7786.h.

#define BITS_M_VC   (0)

Definition at line 111 of file pcie-sh7786.h.

#define BITS_MCODE   (8)

Definition at line 109 of file pcie-sh7786.h.

#define BITS_MDATA   (0)

Definition at line 116 of file pcie-sh7786.h.

#define BITS_MROUTE   (16)

Definition at line 107 of file pcie-sh7786.h.

#define BITS_MSGADRH   (0)

Definition at line 100 of file pcie-sh7786.h.

#define BITS_MSGADRL   (0)

Definition at line 95 of file pcie-sh7786.h.

#define BITS_MSGIE   (31)

Definition at line 105 of file pcie-sh7786.h.

#define BITS_PAH   (0)

Definition at line 371 of file pcie-sh7786.h.

#define BITS_PAL   (18)

Definition at line 366 of file pcie-sh7786.h.

#define BITS_PAM   (18)

Definition at line 376 of file pcie-sh7786.h.

#define BITS_PARE   (31)

Definition at line 381 of file pcie-sh7786.h.

#define BITS_PDR   (0)

Definition at line 90 of file pcie-sh7786.h.

#define BITS_RANGE   (2)

Definition at line 313 of file pcie-sh7786.h.

#define BITS_REGNO   (2)

Definition at line 76 of file pcie-sh7786.h.

#define BITS_SHPRI   (8)

Definition at line 325 of file pcie-sh7786.h.

#define BITS_SNPMD   (0)

Definition at line 315 of file pcie-sh7786.h.

#define BITS_SPC   (8)

Definition at line 389 of file pcie-sh7786.h.

#define BITS_T_VC   (16)

Definition at line 385 of file pcie-sh7786.h.

#define BITS_TC   (20)

Definition at line 383 of file pcie-sh7786.h.

#define BITS_TOP_MB   (24)

Definition at line 38 of file pcie-sh7786.h.

#define BITS_TYPE   (8)

Definition at line 83 of file pcie-sh7786.h.

#define BITS_UNSOLRESP   (3) /* 3 UNSOLRESP 0 R/W */

Definition at line 51 of file pcie-sh7786.h.

#define BITS_VC_ID   (0)

Definition at line 42 of file pcie-sh7786.h.

#define MASK_ACK   (1<<BITS_ACK)

Definition at line 154 of file pcie-sh7786.h.

#define MASK_ADR   (0xff<<BITS_ADR)

Definition at line 160 of file pcie-sh7786.h.

#define MASK_BADDEST   (1<<BITS_BADDEST)

Definition at line 50 of file pcie-sh7786.h.

#define MASK_BADOPC   (1<<BITS_BADOPC)

Definition at line 48 of file pcie-sh7786.h.

#define MASK_BN   (0xff<<BITS_BN)

Definition at line 69 of file pcie-sh7786.h.

#define MASK_BOT_MB   (0xff<<BITS_BOT_MB)

Definition at line 41 of file pcie-sh7786.h.

#define MASK_C_VC   (1<<BITS_C_VC)

Definition at line 86 of file pcie-sh7786.h.

#define MASK_CCIE   (1<<BITS_CCIE)

Definition at line 82 of file pcie-sh7786.h.

#define MASK_CFINT   (1<<BITS_CFINT)

Definition at line 179 of file pcie-sh7786.h.

#define MASK_CKE   (1<<BITS_CKE)

Definition at line 143 of file pcie-sh7786.h.

#define MASK_CMD   (0x03<<BITS_CMD)

Definition at line 156 of file pcie-sh7786.h.

#define MASK_CSADR   (0xffffffff<<BITS_CSADR)

Definition at line 321 of file pcie-sh7786.h.

#define MASK_DATA   (0xffffffff<<BITS_DATA)

Definition at line 174 of file pcie-sh7786.h.

#define MASK_DN   (0x1f<<BITS_DN)

Definition at line 71 of file pcie-sh7786.h.

#define MASK_ENBL   (1<<BITS_ENBL)

Definition at line 64 of file pcie-sh7786.h.

#define MASK_EREGNO   (0xff<<BITS_EREGNO)

Definition at line 75 of file pcie-sh7786.h.

#define MASK_ERRRCV   (1<<BITS_ERRRCV)

Definition at line 56 of file pcie-sh7786.h.

#define MASK_ERRSNT   (1<<BITS_ERRSNT)

Definition at line 54 of file pcie-sh7786.h.

#define MASK_FN   (0x7<<BITS_FN)

Definition at line 73 of file pcie-sh7786.h.

#define MASK_INT_RX_CTRL   (1<<BITS_INT_RX_CTRL)

Definition at line 254 of file pcie-sh7786.h.

#define MASK_INT_RX_CTRL   (1<<BITS_INT_RX_CTRL)

Definition at line 254 of file pcie-sh7786.h.

#define MASK_INT_RX_ERP   (1<<BITS_INT_RX_ERP)

Definition at line 228 of file pcie-sh7786.h.

#define MASK_INT_RX_ERP   (1<<BITS_INT_RX_ERP)

Definition at line 228 of file pcie-sh7786.h.

#define MASK_INT_RX_VC0_CPL   (1<<BITS_INT_RX_VC0_CPL)

Definition at line 246 of file pcie-sh7786.h.

#define MASK_INT_RX_VC0_CPL   (1<<BITS_INT_RX_VC0_CPL)

Definition at line 246 of file pcie-sh7786.h.

#define MASK_INT_RX_VC0_NonPosted   (1<<BITS_INT_RX_VC0_NonPosted)

Definition at line 244 of file pcie-sh7786.h.

#define MASK_INT_RX_VC0_NonPosted   (1<<BITS_INT_RX_VC0_NonPosted)

Definition at line 244 of file pcie-sh7786.h.

#define MASK_INT_RX_VC0_Posted   (1<<BITS_INT_RX_VC0_Posted)

Definition at line 242 of file pcie-sh7786.h.

#define MASK_INT_RX_VC0_Posted   (1<<BITS_INT_RX_VC0_Posted)

Definition at line 242 of file pcie-sh7786.h.

#define MASK_INT_RX_VCX_CPL   (1<<BITS_INT_RX_VCX_CPL)

Definition at line 234 of file pcie-sh7786.h.

#define MASK_INT_RX_VCX_CPL   (1<<BITS_INT_RX_VCX_CPL)

Definition at line 234 of file pcie-sh7786.h.

#define MASK_INT_RX_VCX_NonPosted   (1<<BITS_INT_RX_VCX_NonPosted)

Definition at line 232 of file pcie-sh7786.h.

#define MASK_INT_RX_VCX_NonPosted   (1<<BITS_INT_RX_VCX_NonPosted)

Definition at line 232 of file pcie-sh7786.h.

#define MASK_INT_RX_VCX_Posted   (1<<BITS_INT_RX_VCX_Posted)

Definition at line 230 of file pcie-sh7786.h.

#define MASK_INT_RX_VCX_Posted   (1<<BITS_INT_RX_VCX_Posted)

Definition at line 230 of file pcie-sh7786.h.

#define MASK_INT_TX_CTRL   (1<<BITS_INT_TX_CTRL)

Definition at line 256 of file pcie-sh7786.h.

#define MASK_INT_TX_CTRL   (1<<BITS_INT_TX_CTRL)

Definition at line 256 of file pcie-sh7786.h.

#define MASK_INT_TX_VC0_CPL   (1<<BITS_INT_TX_VC0_CPL)

Definition at line 252 of file pcie-sh7786.h.

#define MASK_INT_TX_VC0_CPL   (1<<BITS_INT_TX_VC0_CPL)

Definition at line 252 of file pcie-sh7786.h.

#define MASK_INT_TX_VC0_NonPosted   (1<<BITS_INT_TX_VC0_NonPosted)

Definition at line 250 of file pcie-sh7786.h.

#define MASK_INT_TX_VC0_NonPosted   (1<<BITS_INT_TX_VC0_NonPosted)

Definition at line 250 of file pcie-sh7786.h.

#define MASK_INT_TX_VC0_Posted   (1<<BITS_INT_TX_VC0_Posted)

Definition at line 248 of file pcie-sh7786.h.

#define MASK_INT_TX_VC0_Posted   (1<<BITS_INT_TX_VC0_Posted)

Definition at line 248 of file pcie-sh7786.h.

#define MASK_INT_TX_VCX_CPL   (1<<BITS_INT_TX_VCX_CPL)

Definition at line 240 of file pcie-sh7786.h.

#define MASK_INT_TX_VCX_CPL   (1<<BITS_INT_TX_VCX_CPL)

Definition at line 240 of file pcie-sh7786.h.

#define MASK_INT_TX_VCX_NonPosted   (1<<BITS_INT_TX_VCX_NonPosted)

Definition at line 238 of file pcie-sh7786.h.

#define MASK_INT_TX_VCX_NonPosted   (1<<BITS_INT_TX_VCX_NonPosted)

Definition at line 238 of file pcie-sh7786.h.

#define MASK_INT_TX_VCX_Posted   (1<<BITS_INT_TX_VCX_Posted)

Definition at line 236 of file pcie-sh7786.h.

#define MASK_INT_TX_VCX_Posted   (1<<BITS_INT_TX_VCX_Posted)

Definition at line 236 of file pcie-sh7786.h.

#define MASK_INTDL   (1<<BITS_INTDL)

Definition at line 260 of file pcie-sh7786.h.

#define MASK_INTDL   (1<<BITS_INTDL)

Definition at line 260 of file pcie-sh7786.h.

#define MASK_INTMAC   (1<<BITS_INTMAC)

Definition at line 262 of file pcie-sh7786.h.

#define MASK_INTMAC   (1<<BITS_INTMAC)

Definition at line 262 of file pcie-sh7786.h.

#define MASK_INTPM   (1<<BITS_INTPM)

Definition at line 264 of file pcie-sh7786.h.

#define MASK_INTPM   (1<<BITS_INTPM)

Definition at line 264 of file pcie-sh7786.h.

#define MASK_INTTL   (1<<BITS_INTTL)

Definition at line 258 of file pcie-sh7786.h.

#define MASK_INTTL   (1<<BITS_INTTL)

Definition at line 258 of file pcie-sh7786.h.

#define MASK_LAMRn   (0x1ff<<BITS_LAMRn)

Definition at line 307 of file pcie-sh7786.h.

#define MASK_LANE   (0x0f<<BITS_LANE)

Definition at line 158 of file pcie-sh7786.h.

#define MASK_LAREn   (0x1<<BITS_LAREn)

Definition at line 309 of file pcie-sh7786.h.

#define MASK_LARn   (0xfff<<BITS_LARn)

Definition at line 300 of file pcie-sh7786.h.

#define MASK_LOCK   (0x1<<BITS_LOCK)

Definition at line 388 of file pcie-sh7786.h.

#define MASK_M_VC   (1<<BITS_M_VC)

Definition at line 112 of file pcie-sh7786.h.

#define MASK_MCODE   (0xff<<BITS_MCODE)

Definition at line 110 of file pcie-sh7786.h.

#define MASK_MDATA   (0xffffffff<<BITS_MDATA)

Definition at line 117 of file pcie-sh7786.h.

#define MASK_MROUTE   (0x7<<BITS_MROUTE)

Definition at line 108 of file pcie-sh7786.h.

#define MASK_MSGADRH   (0xffffffff<<BITS_MSGADRH)

Definition at line 101 of file pcie-sh7786.h.

#define MASK_MSGADRL   (0xffffffff<<BITS_MSGADRL)

Definition at line 96 of file pcie-sh7786.h.

#define MASK_MSGIE   (1<<BITS_MSGIE)

Definition at line 106 of file pcie-sh7786.h.

#define MASK_PAH   (0xffffffff<<BITS_PAH)

Definition at line 372 of file pcie-sh7786.h.

#define MASK_PAL   (0x3fff<<BITS_PAL)

Definition at line 367 of file pcie-sh7786.h.

#define MASK_PAM   (0x3fff<<BITS_PAM)

Definition at line 377 of file pcie-sh7786.h.

#define MASK_PARE   (0x1<<BITS_PARE)

Definition at line 382 of file pcie-sh7786.h.

#define MASK_PDR   (0xffffffff<<BITS_PDR)

Definition at line 91 of file pcie-sh7786.h.

#define MASK_RANGE   (0x7<<BITS_RANGE)

Definition at line 314 of file pcie-sh7786.h.

#define MASK_REGNO   (0x3f<<BITS_REGNO)

Definition at line 77 of file pcie-sh7786.h.

#define MASK_SHPRI   (0x0f<<BITS_SHPRI)

Definition at line 326 of file pcie-sh7786.h.

#define MASK_SNPMD   (0x3<<BITS_SNPMD)

Definition at line 316 of file pcie-sh7786.h.

#define MASK_SPC   (0x1<<BITS_SPC)

Definition at line 390 of file pcie-sh7786.h.

#define MASK_T_VC   (0x1<<BITS_T_VC)

Definition at line 386 of file pcie-sh7786.h.

#define MASK_TC   (0x7<<BITS_TC)

Definition at line 384 of file pcie-sh7786.h.

#define MASK_TOP_MB   (0xff<<BITS_TOP_MB)

Definition at line 39 of file pcie-sh7786.h.

#define MASK_TYPE   (1<<BITS_TYPE)

Definition at line 84 of file pcie-sh7786.h.

#define MASK_UNSOLRESP   (1<<BITS_UNSOLRESP)

Definition at line 52 of file pcie-sh7786.h.

#define MASK_VC_ID   (0xffff<<BITS_VC_ID)

Definition at line 43 of file pcie-sh7786.h.

#define PCI_REG

(

x

)

((x) + 0x40000)

Definition at line 569 of file pcie-sh7786.h.

#define PCIEDLINTENR_DLL_ACT_ENABLE   (1 << 31) /* DL active irq */

Definition at line 511 of file pcie-sh7786.h.

#define PCIEMACCTLR_SCR_DIS   (1 << 27) /* scramble disable */

Definition at line 506 of file pcie-sh7786.h.

#define SH4A_PCI_CNFG_BASE   0xFE040000 /* pci config address for controller 0 */

Definition at line 20 of file pcie-sh7786.h.

#define SH4A_PCI_CNFG_BASE1   0xFE240000 /* pci config address for controller 1 (Rev1.14)*/

Definition at line 21 of file pcie-sh7786.h.

#define SH4A_PCI_CNFG_BASE2   0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/

Definition at line 22 of file pcie-sh7786.h.

#define SH4A_PCI_CNFG_BASE_LEN   0x00040000

Definition at line 23 of file pcie-sh7786.h.

#define SH4A_PCI_SSI_BASE   0xFFE00000 /* spw config address */

Definition at line 561 of file pcie-sh7786.h.

#define SH4A_PCI_SSI_BASE_LEN   0x00100000 /* 1MB */

Definition at line 562 of file pcie-sh7786.h.

#define SH4A_PCIBMSTR_TRANSLATION   0x20000000

Definition at line 34 of file pcie-sh7786.h.

#define SH4A_PCIE_020204   (0x020204) /* R/W R/W 0x0000 0000 32 */

Definition at line 302 of file pcie-sh7786.h.

#define SH4A_PCIE_020224   (0x020224) /* R/W R/W 0x0000 0000 32 */

Definition at line 328 of file pcie-sh7786.h.

#define SH4A_PCIE_020244   (0x020244) /* R/W R/W 0x0000 0000 32 */

Definition at line 337 of file pcie-sh7786.h.

#define SH4A_PCIE_020264   (0x020264) /* R/W R/W 0x0000 0000 32 */

Definition at line 344 of file pcie-sh7786.h.

#define SH4A_PCIE_020284   (0x020284) /* R/W R/W 0x0000 0000 32 */

Definition at line 351 of file pcie-sh7786.h.

#define SH4A_PCIE_0202A4   (0x0202A4) /* R/W R/W 0x0000 0000 32 */

Definition at line 358 of file pcie-sh7786.h.

#define SH4A_PCIE_SPW_BASE   0xFE000000 /* spw config address for controller 0 */

Definition at line 15 of file pcie-sh7786.h.

#define SH4A_PCIE_SPW_BASE1   0xFE200000 /* spw config address for controller 1 (Rev1.14)*/

Definition at line 16 of file pcie-sh7786.h.

#define SH4A_PCIE_SPW_BASE2   0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/

Definition at line 17 of file pcie-sh7786.h.

#define SH4A_PCIE_SPW_BASE_LEN   0x00080000

Definition at line 18 of file pcie-sh7786.h.

#define SH4A_PCIEAIR   (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */

Definition at line 270 of file pcie-sh7786.h.

#define SH4A_PCIEBAR0SETR   (0x041008) /* R/W R 0x0000 0000 16/32 */

Definition at line 488 of file pcie-sh7786.h.

#define SH4A_PCIEBAR1SETR   (0x04100C) /* R/W R 0x0000 0000 16/32 */

Definition at line 489 of file pcie-sh7786.h.

#define SH4A_PCIEBAR2SETR   (0x041010) /* R/W R 0x0000 0000 16/32 */

Definition at line 490 of file pcie-sh7786.h.

#define SH4A_PCIEBAR3SETR   (0x041014) /* R/W R 0x0000 0000 16/32 */

Definition at line 491 of file pcie-sh7786.h.

#define SH4A_PCIEBAR4SETR   (0x041018) /* R/W R 0x0000 0000 16/32 */

Definition at line 492 of file pcie-sh7786.h.

#define SH4A_PCIEBAR5SETR   (0x04101C) /* R/W R 0x0000 0000 16/32 */

Definition at line 493 of file pcie-sh7786.h.

#define SH4A_PCIECIR   (SH4A_PCIE_BASE) /* R/W R/W 0xxxxx xxxx 32 */

Definition at line 273 of file pcie-sh7786.h.

#define SH4A_PCIECISSETR   (0x041020) /* R/W R 0x0000 0000 16/32 */

Definition at line 494 of file pcie-sh7786.h.

#define SH4A_PCIECSAR0   (0x020214) /* R/W R/W 0x0000 0000 32 */

Definition at line 319 of file pcie-sh7786.h.

#define SH4A_PCIECSAR1   (0x020234) /* R/W R/W 0x0000 0000 32 */

Definition at line 333 of file pcie-sh7786.h.

#define SH4A_PCIECSAR2   (0x020254) /* R/W R/W 0x0000 0000 32 */

Definition at line 340 of file pcie-sh7786.h.

#define SH4A_PCIECSAR3   (0x020274) /* R/W R/W 0x0000 0000 32 */

Definition at line 347 of file pcie-sh7786.h.

#define SH4A_PCIECSAR4   (0x020294) /* R/W R/W 0x0000 0000 32 */

Definition at line 354 of file pcie-sh7786.h.

#define SH4A_PCIECSAR5   (0x0202B4) /* R/W R/W 0x0000 0000 32 */

Definition at line 361 of file pcie-sh7786.h.

#define SH4A_PCIECSCR0   (0x020210) /* R/W R/W 0x0000 0000 32 */

Definition at line 312 of file pcie-sh7786.h.

#define SH4A_PCIECSCR1   (0x020230) /* R/W R/W 0x0000 0000 32 */

Definition at line 332 of file pcie-sh7786.h.

#define SH4A_PCIECSCR2   (0x020250) /* R/W R/W 0x0000 0000 32 */

Definition at line 339 of file pcie-sh7786.h.

#define SH4A_PCIECSCR3   (0x020270) /* R/W R/W 0x0000 0000 32 */

Definition at line 346 of file pcie-sh7786.h.

#define SH4A_PCIECSCR4   (0x020290) /* R/W R/W 0x0000 0000 32 */

Definition at line 353 of file pcie-sh7786.h.

#define SH4A_PCIECSCR5   (0x0202B0) /* R/W R/W 0x0000 0000 32 */

Definition at line 360 of file pcie-sh7786.h.

#define SH4A_PCIECTLR   (0x041040) /* R/W R 0x0000 0000 16/32 */

Definition at line 499 of file pcie-sh7786.h.

#define SH4A_PCIEDBGCTLR   (0x000100) /* R/W - 0x0000 0000 32 */

Definition at line 126 of file pcie-sh7786.h.

#define SH4A_PCIEDLCTLR   (0x041050) /* R R 0x0000 0000 16/32 */

Definition at line 503 of file pcie-sh7786.h.

#define SH4A_PCIEDLINTENR   (0x041068) /* R/W R 0x0000 0000 16/32 */

Definition at line 510 of file pcie-sh7786.h.

#define SH4A_PCIEDLSR   (0x04104C) /* R/W1C R 0x4003 0000 16/32 */

Definition at line 502 of file pcie-sh7786.h.

#define SH4A_PCIEDMAOR   (0x021000) /* R/W R/W 0x0000 0000 32 */

Definition at line 392 of file pcie-sh7786.h.

#define SH4A_PCIEDMBCNTR0   (0x021110) /* R/W R/W 0x0000 0000 32 */

Definition at line 397 of file pcie-sh7786.h.

#define SH4A_PCIEDMBCNTR1   (0x021150) /* R/W R/W 0x0000 0000 32 */

Definition at line 409 of file pcie-sh7786.h.

#define SH4A_PCIEDMBCNTR2   (0x021190) /* R/W R/W 0x0000 0000 32 */

Definition at line 421 of file pcie-sh7786.h.

#define SH4A_PCIEDMBCNTR3   (0x0211D0) /* R/W R/W 0x0000 0000 32 */

Definition at line 432 of file pcie-sh7786.h.

#define SH4A_PCIEDMCC2R0   (0x021124) /* R/W R/W 0x0000 0000 - */

Definition at line 402 of file pcie-sh7786.h.

#define SH4A_PCIEDMCC2R1   (0x021164) /* R/W R/W 0x0000 0000 - */

Definition at line 414 of file pcie-sh7786.h.

#define SH4A_PCIEDMCC2R2   (0x0211A4) /* R/W R/W 0x0000 0000 - */

Definition at line 426 of file pcie-sh7786.h.

#define SH4A_PCIEDMCC2R3   (0x0211E4) /* R/W R/W 0x0000 0000 - */

Definition at line 437 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCAR0   (0x02111C) /* R/W R/W 0x0000 0000 32 */

Definition at line 400 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCAR1   (0x02115C) /* R/W R/W 0x0000 0000 32 */

Definition at line 412 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCAR2   (0x02119C) /* R/W R/W 0x0000 0000 32 */

Definition at line 424 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCAR3   (0x0211DC) /* R/W R/W 0x0000 0000 32 */

Definition at line 435 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCCR0   (0x021128) /* R/W R/W 0x0000 0000 32 */

Definition at line 403 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCCR1   (0x021168) /* R/W R/W 0x0000 0000 32 */

Definition at line 415 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCCR2   (0x0211A8) /* R/W R/W 0x0000 0000 32 */

Definition at line 427 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCCR3   (0x0211E8) /* R/W R/W 0x0000 0000 32 */

Definition at line 438 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCR0   (0x021120) /* R/W R/W 0x0000 0000 32 */

Definition at line 401 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCR1   (0x021160) /* R/W R/W 0x0000 0000 32 */

Definition at line 413 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCR2   (0x0211A0) /* R/W R/W 0x0000 0000 32 */

Definition at line 425 of file pcie-sh7786.h.

#define SH4A_PCIEDMCCR3   (0x0211E0) /* R/W R/W 0x0000 0000 32 */

Definition at line 436 of file pcie-sh7786.h.

#define SH4A_PCIEDMCHSR0   (0x02112C) /* R/W - 0x0000 0000 32 */

Definition at line 404 of file pcie-sh7786.h.

#define SH4A_PCIEDMCHSR1   (0x02116C) /* R/W - 0x0000 0000 32 */

Definition at line 416 of file pcie-sh7786.h.

#define SH4A_PCIEDMCHSR3   (0x0211EC) /* R/W R/W 0x0000 0000 32 */

Definition at line 439 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAHR0   (0x02110C) /* R/W R/W 0x0000 0000 32 */

Definition at line 396 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAHR1   (0x02114C) /* R/W R/W 0x0000 0000 32 */

Definition at line 408 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAHR2   (0x02118C) /* R/W R/W 0x0000 0000 32 */

Definition at line 420 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAHR3   (0x0211CC) /* R/W R/W 0x0000 0000 32 */

Definition at line 431 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAR0   (0x021108) /* R/W R/W 0x0000 0000 32 */

Definition at line 395 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAR1   (0x021148) /* R/W R/W 0x0000 0000 32 */

Definition at line 407 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAR2   (0x021188) /* R/W R/W 0x0000 0000 32 */

Definition at line 419 of file pcie-sh7786.h.

#define SH4A_PCIEDMDAR3   (0x0211C8) /* R/W R/W 0x0000 0000 32 */

Definition at line 430 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAHR0   (0x021104) /* R/W R/W 0x0000 0000 32 */

Definition at line 394 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAHR1   (0x021144) /* R/W R/W 0x0000 0000 32 */

Definition at line 406 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAHR2   (0x021184) /* R/W R/W 0x0000 0000 32 */

Definition at line 418 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAHR3   (0x0211C4) /* R/W R/W 0x0000 0000 32 */

Definition at line 429 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAR0   (0x021100) /* R/W R/W 0x0000 0000 32 */

Definition at line 393 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAR1   (0x021140) /* R/W R/W 0x0000 0000 32 */

Definition at line 405 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAR2   (0x021180) /* R/W R/W 0x0000 0000 32 */

Definition at line 417 of file pcie-sh7786.h.

#define SH4A_PCIEDMSAR3   (0x0211C0) /* R/W R/W 0x0000 0000 32 */

Definition at line 428 of file pcie-sh7786.h.

#define SH4A_PCIEDMSBCNTR0   (0x021114) /* R/W R/W 0x0000 0000 32 */

Definition at line 398 of file pcie-sh7786.h.

#define SH4A_PCIEDMSBCNTR1   (0x021154) /* R/W R/W 0x0000 0000 32 */

Definition at line 410 of file pcie-sh7786.h.

#define SH4A_PCIEDMSBCNTR2   (0x021194) /* R/W R/W 0x0000 0000 32 */

Definition at line 422 of file pcie-sh7786.h.

#define SH4A_PCIEDMSBCNTR3   (0x0211D4) /* R/W R/W 0x0000 0000 32 */

Definition at line 433 of file pcie-sh7786.h.

#define SH4A_PCIEDMSTRR0   (0x021118) /* R/W R/W 0x0000 0000 32 */

Definition at line 399 of file pcie-sh7786.h.

#define SH4A_PCIEDMSTRR1   (0x021158) /* R/W R/W 0x0000 0000 32 */

Definition at line 411 of file pcie-sh7786.h.

#define SH4A_PCIEDMSTRR2   (0x021198) /* R/W R/W 0x0000 0000 32 */

Definition at line 423 of file pcie-sh7786.h.

#define SH4A_PCIEDMSTRR3   (0x0211D8) /* R/W R/W 0x0000 0000 32 */

Definition at line 434 of file pcie-sh7786.h.

#define SH4A_PCIEDSERSETR0   (0x04102C) /* R/W R 0x0000 0000 16/32 */

Definition at line 497 of file pcie-sh7786.h.

#define SH4A_PCIEDSERSETR1   (0x041030) /* R/W R 0x0000 0000 16/32 */

Definition at line 498 of file pcie-sh7786.h.

#define SH4A_PCIEECR   (0x00000C) /* R/W - 0x0000 0000 32 */

Definition at line 62 of file pcie-sh7786.h.

#define SH4A_PCIEEHR

(

x

)

(0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */

Definition at line 267 of file pcie-sh7786.h.

#define SH4A_PCIEENBLR   (0x000008) /* R/W - 0x0000 0001 32 */

Definition at line 59 of file pcie-sh7786.h.

#define SH4A_PCIEEROMSETR   (0x041028) /* R/W R 0x0000 0000 16/32 */

Definition at line 496 of file pcie-sh7786.h.

#define SH4A_PCIEERPCTLR   (0x046008) /* RW - H'00000000_00000000 32/64 */

Definition at line 534 of file pcie-sh7786.h.

#define SH4A_PCIEERPERR   (0x046018) /* R - H'00000000_00000000 32/64 */

Definition at line 536 of file pcie-sh7786.h.

#define SH4A_PCIEERPHR   (0x046010) /* R - H'00000000_00000000 32/64 */

Definition at line 535 of file pcie-sh7786.h.

#define SH4A_PCIEERRFER   (0x020024) /* R/W R/W 0x0000 0000 32 */

Definition at line 279 of file pcie-sh7786.h.

#define SH4A_PCIEERRFR   (0x020020) /* R/W R/W 0xxxxx xxxx 32 */

Definition at line 276 of file pcie-sh7786.h.

#define SH4A_PCIEERRFR2   (0x020028) /* R/W R/W 0x0000 0000 32 */

Definition at line 282 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP0   (0x040070) /* R/W R/W 0x0001 0010 8/16/32 */

Definition at line 464 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP1   (0x040074) /* R/W R 0x0000 0005 8/16/32 */

Definition at line 465 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP2   (0x040078) /* R/W R/W 0x0000 0801 8/16/32 */

Definition at line 466 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP3   (0x04007C) /* R/W R 0x0003 F421 8/16/32 */

Definition at line 467 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP4   (0x040080) /* R/W R/W 0x0041 0000 8/16/32 */

Definition at line 468 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP5   (0x040084) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 469 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP6   (0x040088) /* R/W R/W 0x0000 03C0 8/16/32 */

Definition at line 470 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP7   (0x04008C) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 471 of file pcie-sh7786.h.

#define SH4A_PCIEEXPCAP8   (0x040090) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 472 of file pcie-sh7786.h.

#define SH4A_PCIEIDR   (0x000060) /* R/W - 0x0101 1101 32 */

Definition at line 123 of file pcie-sh7786.h.

#define SH4A_PCIEIDSETR0   (0x041000) /* R/W R 0x0000 FFFF 16/32 */

Definition at line 486 of file pcie-sh7786.h.

#define SH4A_PCIEIDSETR1   (0x041004) /* R/W R 0xFF00 0000 16/32 */

Definition at line 487 of file pcie-sh7786.h.

#define SH4A_PCIEIDSETR2   (0x041024) /* R/W R 0x0000 0000 16/32 */

Definition at line 495 of file pcie-sh7786.h.

#define SH4A_PCIEINTER   (0x02000C) /* R/W R/W 0x0000 0000 32 */

Definition at line 226 of file pcie-sh7786.h.

#define SH4A_PCIEINTR   (0x020008) /* R/W R/W 0x0000 0000 32 */

Definition at line 185 of file pcie-sh7786.h.

#define SH4A_PCIEINTXR   (0x004000) /* R/W - 0x0000 0000 32 */

Definition at line 129 of file pcie-sh7786.h.

#define SH4A_PCIELAMR0   (0x020208) /* R/W R/W 0x0000 0000 32 */

Definition at line 305 of file pcie-sh7786.h.

#define SH4A_PCIELAMR1   (0x020228) /* R/W R/W 0x0000 0000 32 */

Definition at line 331 of file pcie-sh7786.h.

#define SH4A_PCIELAMR2   (0x020248) /* R/W R/W 0x0000 0000 32 */

Definition at line 338 of file pcie-sh7786.h.

#define SH4A_PCIELAMR3   (0x020268) /* R/W R/W 0x0000 0000 32 */

Definition at line 345 of file pcie-sh7786.h.

#define SH4A_PCIELAMR4   (0x020288) /* R/W R/W 0x0000 0000 32 */

Definition at line 352 of file pcie-sh7786.h.

#define SH4A_PCIELAMR5   (0x0202A8) /* R/W R/W 0x0000 0000 32 */

Definition at line 359 of file pcie-sh7786.h.

#define SH4A_PCIELAR0   (0x020200) /* R/W R/W 0x0000 0000 32 */

Definition at line 298 of file pcie-sh7786.h.

#define SH4A_PCIELAR1   (0x020220) /* R/W R/W 0x0000 0000 32 */

Definition at line 330 of file pcie-sh7786.h.

#define SH4A_PCIELAR2   (0x020240) /* R/W R/W 0x0000 0000 32 */

Definition at line 336 of file pcie-sh7786.h.

#define SH4A_PCIELAR3   (0x020260) /* R/W R/W 0x0000 0000 32 */

Definition at line 343 of file pcie-sh7786.h.

#define SH4A_PCIELAR4   (0x020280) /* R/W R/W 0x0000 0000 32 */

Definition at line 350 of file pcie-sh7786.h.

#define SH4A_PCIELAR5   (0x0202A0) /* R/W R/W 0x0000 0000 32 */

Definition at line 357 of file pcie-sh7786.h.

#define SH4A_PCIEMACCTLR   (0x041058) /* R/W R 0x0000 0000 16/32 */

Definition at line 505 of file pcie-sh7786.h.

#define SH4A_PCIEMACINTENR   (0x04106C) /* R/W R 0x0000 0000 16/32 */

Definition at line 512 of file pcie-sh7786.h.

#define SH4A_PCIEMACSR   (0x041054) /* R/W1C R 0x0041 0000 16/32 */

Definition at line 504 of file pcie-sh7786.h.

#define SH4A_PCIEMSG   (0x000040) /* W - - 32 */

Definition at line 115 of file pcie-sh7786.h.

#define SH4A_PCIEMSGAHR   (0x000034) /* R/W - 0x0000 0000 32 */

Definition at line 99 of file pcie-sh7786.h.

#define SH4A_PCIEMSGALR   (0x000030) /* R/W - 0x0000 0000 32 */

Definition at line 94 of file pcie-sh7786.h.

#define SH4A_PCIEMSGCTLR   (0x000038) /* R/W - 0x0000 0000 32 */

Definition at line 104 of file pcie-sh7786.h.

#define SH4A_PCIEMSICAP0   (0x040050) /* R/W R/W 0x0180 7005 8/16/32 */

Definition at line 458 of file pcie-sh7786.h.

#define SH4A_PCIEMSICAP1   (0x040054) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 459 of file pcie-sh7786.h.

#define SH4A_PCIEMSICAP2   (0x040058) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 460 of file pcie-sh7786.h.

#define SH4A_PCIEMSICAP3   (0x04005C) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 461 of file pcie-sh7786.h.

#define SH4A_PCIEMSICAP4   (0x040060) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 462 of file pcie-sh7786.h.

#define SH4A_PCIEMSICAP5   (0x040064) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 463 of file pcie-sh7786.h.

#define SH4A_PCIEMSIFR   (0x020044) /* R/W R/W 0x0000 0000 32 */

Definition at line 288 of file pcie-sh7786.h.

#define SH4A_PCIEMSIR   (0x020040) /* R/W - 0x0000 0000 32 */

Definition at line 285 of file pcie-sh7786.h.

#define SH4A_PCIENUMCAP0   (0x0001B0) /* RW R 0x0001 0003 8/16/32 */

Definition at line 483 of file pcie-sh7786.h.

#define SH4A_PCIENUMCAP1   (0x0001B4) /* R R 0x0000 0000 8/16/32 */

Definition at line 484 of file pcie-sh7786.h.

#define SH4A_PCIENUMCAP2   (0x0001B8) /* R R 0x0000 0000 8/16/32 */

Definition at line 485 of file pcie-sh7786.h.

#define SH4A_PCIEPAMR

(

x

)

(0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */

Definition at line 375 of file pcie-sh7786.h.

#define SH4A_PCIEPAR   (0x000010) /* R/W - 0x0000 0000 32 */

Definition at line 67 of file pcie-sh7786.h.

#define SH4A_PCIEPARH

(

x

)

(0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */

Definition at line 370 of file pcie-sh7786.h.

#define SH4A_PCIEPARL

(

x

)

(0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */

Definition at line 365 of file pcie-sh7786.h.

#define SH4A_PCIEPCCTLR   (0x020180) /* R/W - 0x0000 0000 32 */

Definition at line 294 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF0   (0x040000) /* R R - 8/16/32 */

Definition at line 440 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF1   (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */

Definition at line 441 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF10   (0x040028) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 450 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF11   (0x04002C) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 451 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF12   (0x040030) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 452 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF13   (0x040034) /* R/W R/W 0x0000 0040 8/16/32 */

Definition at line 453 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF14   (0x040038) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 454 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF15   (0x04003C) /* R/W R/W 0x0000 00FF 8/16/32 */

Definition at line 455 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF2   (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */

Definition at line 442 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF3   (0x04000C) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 443 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF4   (0x040010) /* - R/W - 8/16/32 */

Definition at line 444 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF5   (0x040014) /* - R/W - 8/16/32 */

Definition at line 445 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF6   (0x040018) /* - R/W - 8/16/32 */

Definition at line 446 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF7   (0x04001C) /* - R/W - 8/16/32 */

Definition at line 447 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF8   (0x040020) /* - R/W - 8/16/32 */

Definition at line 448 of file pcie-sh7786.h.

#define SH4A_PCIEPCICONF9   (0x040024) /* - R/W - 8/16/32 */

Definition at line 449 of file pcie-sh7786.h.

#define SH4A_PCIEPCTLR   (0x000018) /* R/W - 0x0000 0000 32 */

Definition at line 80 of file pcie-sh7786.h.

#define SH4A_PCIEPDR   (0x000020) /* R/W - 0x0000 0000 32 */

Definition at line 89 of file pcie-sh7786.h.

#define SH4A_PCIEPHYADRR   (0x010004) /* R/W - 0x0000 0000 32 */

Definition at line 152 of file pcie-sh7786.h.

#define SH4A_PCIEPHYCTLR   (0x010000) /* R/W - 0x0000 0000 32 */

Definition at line 149 of file pcie-sh7786.h.

#define SH4A_PCIEPHYCTLR   (0x010000) /* R/W - 0x0000 0000 32 */

Definition at line 149 of file pcie-sh7786.h.

#define SH4A_PCIEPHYDATAR   (0x00008) /* R/W - 0xxxxx xxxx 32 */

Definition at line 172 of file pcie-sh7786.h.

#define SH4A_PCIEPHYDINR   (0x010008) /* R/W - 0x0000 0000 32 */

Definition at line 163 of file pcie-sh7786.h.

#define SH4A_PCIEPHYDOUTR   (0x01000C) /* R/W - 0x0000 0000 32 */

Definition at line 166 of file pcie-sh7786.h.

#define SH4A_PCIEPHYSR   (0x010010) /* R/W - 0x0000 0000 32 */

Definition at line 169 of file pcie-sh7786.h.

#define SH4A_PCIEPMCAP0   (0x040040) /* R/W R 0x0003 5001 8/16/32 */

Definition at line 456 of file pcie-sh7786.h.

#define SH4A_PCIEPMCAP1   (0x040044) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 457 of file pcie-sh7786.h.

#define SH4A_PCIEPMCTLR   (0x041060) /* R/W R 0x0000 0000 16/32 */

Definition at line 508 of file pcie-sh7786.h.

#define SH4A_PCIEPMINTENR   (0x041070) /* R/W R 0x0000 0000 16/32 */

Definition at line 513 of file pcie-sh7786.h.

#define SH4A_PCIEPMSTR   (0x04105C) /* R/W1C R 0x0000 0000 16/32 */

Definition at line 507 of file pcie-sh7786.h.

#define SH4A_PCIEPTCTLR

(

x

)

(0x02040C + ((x) * 0x20))

Definition at line 380 of file pcie-sh7786.h.

#define SH4A_PCIEPWRCTLR   (0x020100) /* R/W - 0x0000 0000 32 */

Definition at line 291 of file pcie-sh7786.h.

#define SH4A_PCIERDCTLR   (0x046000) /* RW - H'00000000_00000000 32/64 */

Definition at line 533 of file pcie-sh7786.h.

#define SH4A_PCIERMSGIER   (0x004040) /* R/W - 0x0000 0000 32 */

Definition at line 146 of file pcie-sh7786.h.

#define SH4A_PCIERMSGR   (0x004010) /* R/W - 0x0000 0000 32 */

Definition at line 132 of file pcie-sh7786.h.

#define SH4A_PCIERSTR

(

x

)

(0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */

Definition at line 135 of file pcie-sh7786.h.

#define SH4A_PCIERXVC0DCTLR   (0x046100) /* RW - H'00000000_00000000 32/64 */

Definition at line 537 of file pcie-sh7786.h.

#define SH4A_PCIERXVC0SR   (0x046108) /* RW - H'00000000_00000000 32/64 */

Definition at line 538 of file pcie-sh7786.h.

#define SH4A_PCIERXVCXDCTLR   (0x046200) /* RW - H'00000000_00000000 32/64 */

Definition at line 548 of file pcie-sh7786.h.

#define SH4A_PCIERXVCXSR   (0x046208) /* RW - H'00000000_00000000 32/64 */

Definition at line 549 of file pcie-sh7786.h.

#define SH4A_PCIESRSTR   (0x008040) /* R/W - 0x0000 0000 32 */

Definition at line 138 of file pcie-sh7786.h.

#define SH4A_PCIESTCTLR0   (0x020218) /* R/W R/W 0x0000 0000 32 */

Definition at line 324 of file pcie-sh7786.h.

#define SH4A_PCIESTCTLR1   (0x020238) /* R/W R/W 0x0000 0000 32 */

Definition at line 334 of file pcie-sh7786.h.

#define SH4A_PCIESTCTLR2   (0x020258) /* R/W R/W 0x0000 0000 32 */

Definition at line 341 of file pcie-sh7786.h.

#define SH4A_PCIESTCTLR3   (0x020278) /* R/W R/W 0x0000 0000 32 */

Definition at line 348 of file pcie-sh7786.h.

#define SH4A_PCIESTCTLR4   (0x020298) /* R/W R/W 0x0000 0000 32 */

Definition at line 355 of file pcie-sh7786.h.

#define SH4A_PCIESTCTLR5   (0x0202B8) /* R/W R/W 0x0000 0000 32 */

Definition at line 362 of file pcie-sh7786.h.

#define SH4A_PCIETCTLR   (0x020000) /* R/W R/W 0x0000 0000 32 */

Definition at line 177 of file pcie-sh7786.h.

#define SH4A_PCIETLCTLR   (0x041048) /* R/W R 0x0000 0000 16/32 */

Definition at line 501 of file pcie-sh7786.h.

#define SH4A_PCIETLINTENR   (0x041064) /* R/W R 0x0000 0000 16/32 */

Definition at line 509 of file pcie-sh7786.h.

#define SH4A_PCIETLSR   (0x041044) /* R/W1C R 0x0000 0000 16/32 */

Definition at line 500 of file pcie-sh7786.h.

#define SH4A_PCIETSTR   (0x020004) /* R 0x0000 0000 32 */

Definition at line 182 of file pcie-sh7786.h.

#define SH4A_PCIETXCTLR   (0x044020) /* R/W - H'00000000_00000000 32/64 */

Definition at line 515 of file pcie-sh7786.h.

#define SH4A_PCIETXDCTLR   (0x044000) /* R/W - H'00000000_00000000 32/64 */

Definition at line 514 of file pcie-sh7786.h.

#define SH4A_PCIETXSR   (0x044028) /* R - H'00000000_00000000 32/64 */

Definition at line 516 of file pcie-sh7786.h.

#define SH4A_PCIETXVC0DCTLR   (0x044100) /* R/W - H'00000000_00000000 32/64 */

Definition at line 517 of file pcie-sh7786.h.

#define SH4A_PCIETXVC0SR   (0x044108) /* R/W - H'00888000_00000000 32/64 */

Definition at line 518 of file pcie-sh7786.h.

#define SH4A_PCIETXVCXDCTLR   (0x044200) /* R/W - H'00000000_00000000 32/64 */

Definition at line 525 of file pcie-sh7786.h.

#define SH4A_PCIETXVCXSR   (0x044208) /* R/W - H'00000000_00000000 32/64 */

Definition at line 526 of file pcie-sh7786.h.

#define SH4A_PCIEUNLOCKCR   (0x000048) /* R/W - 0x0000 0000 32 */

Definition at line 120 of file pcie-sh7786.h.

#define SH4A_PCIEVC0CDRXR   (0x046170) /* R - H'00000000_00000000 32/64 */

Definition at line 545 of file pcie-sh7786.h.

#define SH4A_PCIEVC0CDTXR   (0x044130) /* W - H'00000000_00000000 32/64 */

Definition at line 523 of file pcie-sh7786.h.

#define SH4A_PCIEVC0CERR   (0x046180) /* R - H'00000000_00000000 32/64 */

Definition at line 547 of file pcie-sh7786.h.

#define SH4A_PCIEVC0CHRXR   (0x046178) /* R - H'00000000_00000000 32/64 */

Definition at line 546 of file pcie-sh7786.h.

#define SH4A_PCIEVC0CHTXR   (0x044138) /* W - H'00000000_00000000 32/64 */

Definition at line 524 of file pcie-sh7786.h.

#define SH4A_PCIEVC0NPDRXR   (0x046158) /* R - H'00000000_00000000 32/64 */

Definition at line 542 of file pcie-sh7786.h.

#define SH4A_PCIEVC0NPDTXR   (0x044120) /* W - H'00000000_00000000 32/64 */

Definition at line 521 of file pcie-sh7786.h.

#define SH4A_PCIEVC0NPERR   (0x046168) /* R - H'00000000_00000000 32/64 */

Definition at line 544 of file pcie-sh7786.h.

#define SH4A_PCIEVC0NPHRXR   (0x046160) /* R - H'00000000_00000000 32/64 */

Definition at line 543 of file pcie-sh7786.h.

#define SH4A_PCIEVC0NPHTXR   (0x044128) /* W - H'00000000_00000000 32/64 */

Definition at line 522 of file pcie-sh7786.h.

#define SH4A_PCIEVC0PDRXR   (0x046140) /* R - H'00000000_00000000 32/64 */

Definition at line 539 of file pcie-sh7786.h.

#define SH4A_PCIEVC0PDTXR   (0x044110) /* W - H'00000000_00000000 32/64 */

Definition at line 519 of file pcie-sh7786.h.

#define SH4A_PCIEVC0PERR   (0x046150) /* R - H'00000000_00000000 32/64 */

Definition at line 541 of file pcie-sh7786.h.

#define SH4A_PCIEVC0PHRXR   (0x046148) /* R - H'00000000_00000000 32/64 */

Definition at line 540 of file pcie-sh7786.h.

#define SH4A_PCIEVC0PHTXR   (0x044118) /* W - H'00000000_00000000 32/64 */

Definition at line 520 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP0   (0x040100) /* R/W R 0x1B01 0002 8/16/32 */

Definition at line 473 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP1   (0x040104) /* R R 0x0000 0001 8/16/32 */

Definition at line 474 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP2   (0x040108) /* R R 0x0000 0000 8/16/32 */

Definition at line 475 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP3   (0x04010C) /* R R/W 0x0000 0000 8/16/32 */

Definition at line 476 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP4   (0x040110) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 477 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP5   (0x040114) /* R/W R/W 0x8000 00FF 8/16/32 */

Definition at line 478 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP6   (0x040118) /* R/W R 0x0002 0000 8/16/32 */

Definition at line 479 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP7   (0x04011C) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 480 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP8   (0x040120) /* R/W R/W 0x0000 0000 8/16/32 */

Definition at line 481 of file pcie-sh7786.h.

#define SH4A_PCIEVCCAP9   (0x040124) /* R/W R 0x0002 0000 8/16/32 */

Definition at line 482 of file pcie-sh7786.h.

#define SH4A_PCIEVCR0   (0x000000) /* R - 0x0000 0000 32 */

Definition at line 37 of file pcie-sh7786.h.

#define SH4A_PCIEVCR1   (0x000004) /* R - 0x0000 0000 32*/

Definition at line 46 of file pcie-sh7786.h.

#define SH4A_PCIEVCXCDRXR   (0x046270) /* R H'00000000_00000000 32/64 */

Definition at line 556 of file pcie-sh7786.h.

#define SH4A_PCIEVCXCDTXR   (0x044230) /* W - H'00000000_00000000 32/64 */

Definition at line 531 of file pcie-sh7786.h.

#define SH4A_PCIEVCXCERR   (0x046280) /* R H'00000000_00000000 32/64 */

Definition at line 558 of file pcie-sh7786.h.

#define SH4A_PCIEVCXCHRXR   (0x046278) /* R H'00000000_00000000 32/64 */

Definition at line 557 of file pcie-sh7786.h.

#define SH4A_PCIEVCXCHTXR   (0x044238) /* W - H'00000000_00000000 32/64 */

Definition at line 532 of file pcie-sh7786.h.

#define SH4A_PCIEVCXNPDRXR   (0x046258) /* R H'00000000_00000000 32/64 */

Definition at line 553 of file pcie-sh7786.h.

#define SH4A_PCIEVCXNPDTXR   (0x044220) /* W - H'00000000_00000000 32/64 */

Definition at line 529 of file pcie-sh7786.h.

#define SH4A_PCIEVCXNPERR   (0x046268) /* R H'00000000_00000000 32/64 */

Definition at line 555 of file pcie-sh7786.h.

#define SH4A_PCIEVCXNPHRXR   (0x046260) /* R H'00000000_00000000 32/64 */

Definition at line 554 of file pcie-sh7786.h.

#define SH4A_PCIEVCXNPHTXR   (0x044228) /* W - H'00000000_00000000 32/64 */

Definition at line 530 of file pcie-sh7786.h.

#define SH4A_PCIEVCXPDRXR   (0x046240) /* R - H'00000000_00000000 32/64 */

Definition at line 550 of file pcie-sh7786.h.

#define SH4A_PCIEVCXPDTXR   (0x044210) /* W - H'00000000_00000000 32/64 */

Definition at line 527 of file pcie-sh7786.h.

#define SH4A_PCIEVCXPERR   (0x046250) /* R H'00000000_00000000 32/64 */

Definition at line 552 of file pcie-sh7786.h.

#define SH4A_PCIEVCXPHRXR   (0x046248) /* R H'00000000_00000000 32/64 */

Definition at line 551 of file pcie-sh7786.h.

#define SH4A_PCIEVCXPHTXR   (0x044218) /* W - H'00000000_00000000 32/64 */

Definition at line 528 of file pcie-sh7786.h.

#define SH4A_PCIPIO_ADDR_OFFSET   0x000001c0 /* offset to pci config_address */

Definition at line 25 of file pcie-sh7786.h.

#define SH4A_PCIPIO_DATA_OFFSET   0x00000220 /* offset to pci config_data */

Definition at line 26 of file pcie-sh7786.h.

#define SH4A_SSICR0   (0x000000)

Definition at line 564 of file pcie-sh7786.h.

#define SH4A_SSICR1   (0x010000)

Definition at line 565 of file pcie-sh7786.h.

#define SH4A_SSICR2   (0x020000)

Definition at line 566 of file pcie-sh7786.h.

#define SH4A_SSICR3   (0x030000)

Definition at line 567 of file pcie-sh7786.h.