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Data Structures | Macros
perf_event_intel_uncore.h File Reference
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/perf_event.h>
#include "perf_event.h"

Go to the source code of this file.

Data Structures

struct  intel_uncore_type
 
struct  intel_uncore_ops
 
struct  intel_uncore_pmu
 
struct  intel_uncore_extra_reg
 
struct  intel_uncore_box
 
struct  uncore_event_desc
 

Macros

#define UNCORE_PMU_NAME_LEN   32
 
#define UNCORE_PMU_HRTIMER_INTERVAL   (60LL * NSEC_PER_SEC)
 
#define UNCORE_FIXED_EVENT   0xff
 
#define UNCORE_PMC_IDX_MAX_GENERIC   8
 
#define UNCORE_PMC_IDX_FIXED   UNCORE_PMC_IDX_MAX_GENERIC
 
#define UNCORE_PMC_IDX_MAX   (UNCORE_PMC_IDX_FIXED + 1)
 
#define UNCORE_EVENT_CONSTRAINT(c, n)   EVENT_CONSTRAINT(c, n, 0xff)
 
#define SNB_UNC_CTL_EV_SEL_MASK   0x000000ff
 
#define SNB_UNC_CTL_UMASK_MASK   0x0000ff00
 
#define SNB_UNC_CTL_EDGE_DET   (1 << 18)
 
#define SNB_UNC_CTL_EN   (1 << 22)
 
#define SNB_UNC_CTL_INVERT   (1 << 23)
 
#define SNB_UNC_CTL_CMASK_MASK   0x1f000000
 
#define NHM_UNC_CTL_CMASK_MASK   0xff000000
 
#define NHM_UNC_FIXED_CTR_CTL_EN   (1 << 0)
 
#define SNB_UNC_RAW_EVENT_MASK
 
#define NHM_UNC_RAW_EVENT_MASK
 
#define SNB_UNC_PERF_GLOBAL_CTL   0x391
 
#define SNB_UNC_FIXED_CTR_CTRL   0x394
 
#define SNB_UNC_FIXED_CTR   0x395
 
#define SNB_UNC_GLOBAL_CTL_CORE_ALL   ((1 << 4) - 1)
 
#define SNB_UNC_GLOBAL_CTL_EN   (1 << 29)
 
#define SNB_UNC_CBO_0_PERFEVTSEL0   0x700
 
#define SNB_UNC_CBO_0_PER_CTR0   0x706
 
#define SNB_UNC_CBO_MSR_OFFSET   0x10
 
#define NHM_UNC_PERF_GLOBAL_CTL   0x391
 
#define NHM_UNC_FIXED_CTR   0x394
 
#define NHM_UNC_FIXED_CTR_CTRL   0x395
 
#define NHM_UNC_GLOBAL_CTL_EN_PC_ALL   ((1ULL << 8) - 1)
 
#define NHM_UNC_GLOBAL_CTL_EN_FC   (1ULL << 32)
 
#define NHM_UNC_PERFEVTSEL0   0x3c0
 
#define NHM_UNC_UNCORE_PMC0   0x3b0
 
#define SNBEP_PMON_BOX_CTL_RST_CTRL   (1 << 0)
 
#define SNBEP_PMON_BOX_CTL_RST_CTRS   (1 << 1)
 
#define SNBEP_PMON_BOX_CTL_FRZ   (1 << 8)
 
#define SNBEP_PMON_BOX_CTL_FRZ_EN   (1 << 16)
 
#define SNBEP_PMON_BOX_CTL_INT
 
#define SNBEP_PMON_CTL_EV_SEL_MASK   0x000000ff
 
#define SNBEP_PMON_CTL_UMASK_MASK   0x0000ff00
 
#define SNBEP_PMON_CTL_RST   (1 << 17)
 
#define SNBEP_PMON_CTL_EDGE_DET   (1 << 18)
 
#define SNBEP_PMON_CTL_EV_SEL_EXT   (1 << 21) /* only for QPI */
 
#define SNBEP_PMON_CTL_EN   (1 << 22)
 
#define SNBEP_PMON_CTL_INVERT   (1 << 23)
 
#define SNBEP_PMON_CTL_TRESH_MASK   0xff000000
 
#define SNBEP_PMON_RAW_EVENT_MASK
 
#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK   0x1f000000
 
#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK
 
#define SNBEP_CBO_PMON_CTL_TID_EN   (1 << 19)
 
#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK
 
#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK   0x0000c000
 
#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK   0x1f000000
 
#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT   (1 << 30)
 
#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET   (1 << 31)
 
#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK
 
#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK
 
#define SNBEP_PCI_PMON_BOX_CTL   0xf4
 
#define SNBEP_PCI_PMON_CTL0   0xd8
 
#define SNBEP_PCI_PMON_CTR0   0xa0
 
#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0   0x40
 
#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1   0x44
 
#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH   0x48
 
#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL   0xf0
 
#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR   0xd0
 
#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0   0x228
 
#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1   0x22c
 
#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0   0x238
 
#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1   0x23c
 
#define SNBEP_U_MSR_PMON_CTR0   0xc16
 
#define SNBEP_U_MSR_PMON_CTL0   0xc10
 
#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL   0xc08
 
#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR   0xc09
 
#define SNBEP_C0_MSR_PMON_CTR0   0xd16
 
#define SNBEP_C0_MSR_PMON_CTL0   0xd10
 
#define SNBEP_C0_MSR_PMON_BOX_CTL   0xd04
 
#define SNBEP_C0_MSR_PMON_BOX_FILTER   0xd14
 
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK   0xfffffc1f
 
#define SNBEP_CBO_MSR_OFFSET   0x20
 
#define SNBEP_PCU_MSR_PMON_CTR0   0xc36
 
#define SNBEP_PCU_MSR_PMON_CTL0   0xc30
 
#define SNBEP_PCU_MSR_PMON_BOX_CTL   0xc24
 
#define SNBEP_PCU_MSR_PMON_BOX_FILTER   0xc34
 
#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK   0xffffffff
 
#define SNBEP_PCU_MSR_CORE_C3_CTR   0x3fc
 
#define SNBEP_PCU_MSR_CORE_C6_CTR   0x3fd
 
#define NHMEX_PMON_CTL_EV_SEL_MASK   0x000000ff
 
#define NHMEX_PMON_CTL_UMASK_MASK   0x0000ff00
 
#define NHMEX_PMON_CTL_EN_BIT0   (1 << 0)
 
#define NHMEX_PMON_CTL_EDGE_DET   (1 << 18)
 
#define NHMEX_PMON_CTL_PMI_EN   (1 << 20)
 
#define NHMEX_PMON_CTL_EN_BIT22   (1 << 22)
 
#define NHMEX_PMON_CTL_INVERT   (1 << 23)
 
#define NHMEX_PMON_CTL_TRESH_MASK   0xff000000
 
#define NHMEX_PMON_RAW_EVENT_MASK
 
#define NHMEX_U_MSR_PMON_GLOBAL_CTL   0xc00
 
#define NHMEX_U_MSR_PMON_CTR   0xc11
 
#define NHMEX_U_MSR_PMON_EV_SEL   0xc10
 
#define NHMEX_U_PMON_GLOBAL_EN   (1 << 0)
 
#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL   0x0000001e
 
#define NHMEX_U_PMON_GLOBAL_EN_ALL   (1 << 28)
 
#define NHMEX_U_PMON_GLOBAL_RST_ALL   (1 << 29)
 
#define NHMEX_U_PMON_GLOBAL_FRZ_ALL   (1 << 31)
 
#define NHMEX_U_PMON_RAW_EVENT_MASK
 
#define NHMEX_C0_MSR_PMON_GLOBAL_CTL   0xd00
 
#define NHMEX_C0_MSR_PMON_CTR0   0xd11
 
#define NHMEX_C0_MSR_PMON_EV_SEL0   0xd10
 
#define NHMEX_C_MSR_OFFSET   0x20
 
#define NHMEX_B0_MSR_PMON_GLOBAL_CTL   0xc20
 
#define NHMEX_B0_MSR_PMON_CTR0   0xc31
 
#define NHMEX_B0_MSR_PMON_CTL0   0xc30
 
#define NHMEX_B_MSR_OFFSET   0x40
 
#define NHMEX_B0_MSR_MATCH   0xe45
 
#define NHMEX_B0_MSR_MASK   0xe46
 
#define NHMEX_B1_MSR_MATCH   0xe4d
 
#define NHMEX_B1_MSR_MASK   0xe4e
 
#define NHMEX_B_PMON_CTL_EN   (1 << 0)
 
#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT   1
 
#define NHMEX_B_PMON_CTL_EV_SEL_MASK   (0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
 
#define NHMEX_B_PMON_CTR_SHIFT   6
 
#define NHMEX_B_PMON_CTR_MASK   (0x3 << NHMEX_B_PMON_CTR_SHIFT)
 
#define NHMEX_B_PMON_RAW_EVENT_MASK
 
#define NHMEX_S0_MSR_PMON_GLOBAL_CTL   0xc40
 
#define NHMEX_S0_MSR_PMON_CTR0   0xc51
 
#define NHMEX_S0_MSR_PMON_CTL0   0xc50
 
#define NHMEX_S_MSR_OFFSET   0x80
 
#define NHMEX_S0_MSR_MM_CFG   0xe48
 
#define NHMEX_S0_MSR_MATCH   0xe49
 
#define NHMEX_S0_MSR_MASK   0xe4a
 
#define NHMEX_S1_MSR_MM_CFG   0xe58
 
#define NHMEX_S1_MSR_MATCH   0xe59
 
#define NHMEX_S1_MSR_MASK   0xe5a
 
#define NHMEX_S_PMON_MM_CFG_EN   (0x1ULL << 63)
 
#define NHMEX_S_EVENT_TO_R_PROG_EV   0
 
#define NHMEX_M0_MSR_GLOBAL_CTL   0xca0
 
#define NHMEX_M0_MSR_PMU_DSP   0xca5
 
#define NHMEX_M0_MSR_PMU_ISS   0xca6
 
#define NHMEX_M0_MSR_PMU_MAP   0xca7
 
#define NHMEX_M0_MSR_PMU_MSC_THR   0xca8
 
#define NHMEX_M0_MSR_PMU_PGT   0xca9
 
#define NHMEX_M0_MSR_PMU_PLD   0xcaa
 
#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC   0xcab
 
#define NHMEX_M0_MSR_PMU_CTL0   0xcb0
 
#define NHMEX_M0_MSR_PMU_CNT0   0xcb1
 
#define NHMEX_M_MSR_OFFSET   0x40
 
#define NHMEX_M0_MSR_PMU_MM_CFG   0xe54
 
#define NHMEX_M1_MSR_PMU_MM_CFG   0xe5c
 
#define NHMEX_M_PMON_MM_CFG_EN   (1ULL << 63)
 
#define NHMEX_M_PMON_ADDR_MATCH_MASK   0x3ffffffffULL
 
#define NHMEX_M_PMON_ADDR_MASK_MASK   0x7ffffffULL
 
#define NHMEX_M_PMON_ADDR_MASK_SHIFT   34
 
#define NHMEX_M_PMON_CTL_EN   (1 << 0)
 
#define NHMEX_M_PMON_CTL_PMI_EN   (1 << 1)
 
#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT   2
 
#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK   (0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
 
#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT   4
 
#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK   (0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
 
#define NHMEX_M_PMON_CTL_WRAP_MODE   (1 << 6)
 
#define NHMEX_M_PMON_CTL_FLAG_MODE   (1 << 7)
 
#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT   9
 
#define NHMEX_M_PMON_CTL_INC_SEL_MASK   (0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
 
#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT   19
 
#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK   (0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
 
#define NHMEX_M_PMON_RAW_EVENT_MASK
 
#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK   (((1 << 11) - 1) | (1 << 23))
 
#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)   (0x7 << (11 + 3 * (n)))
 
#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK   (((1 << 12) - 1) | (1 << 24))
 
#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)   (0x7 << (12 + 3 * (n)))
 
#define MBOX_INC_SEL(x)   ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
 
#define MBOX_SET_FLAG_SEL(x)
 
#define MBOX_INC_SEL_MASK
 
#define MBOX_SET_FLAG_SEL_MASK
 
#define MBOX_INC_SEL_EXTAR_REG(c, r)
 
#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r)
 
#define NHMEX_R_MSR_GLOBAL_CTL   0xe00
 
#define NHMEX_R_MSR_PMON_CTL0   0xe10
 
#define NHMEX_R_MSR_PMON_CNT0   0xe11
 
#define NHMEX_R_MSR_OFFSET   0x20
 
#define NHMEX_R_MSR_PORTN_QLX_CFG(n)   ((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
 
#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n)   (0xe04 + (n))
 
#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n)   (0xe24 + (n))
 
#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n)   (((n) < 4 ? 0 : 0x10) + (n) * 4)
 
#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n)   (0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
 
#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n)   (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
 
#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n)   (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
 
#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n)   (0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
 
#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n)   (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
 
#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n)   (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
 
#define NHMEX_R_PMON_CTL_EN   (1 << 0)
 
#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT   1
 
#define NHMEX_R_PMON_CTL_EV_SEL_MASK   (0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
 
#define NHMEX_R_PMON_CTL_PMI_EN   (1 << 6)
 
#define NHMEX_R_PMON_RAW_EVENT_MASK   NHMEX_R_PMON_CTL_EV_SEL_MASK
 
#define NHMEX_W_MSR_GLOBAL_CTL   0xc80
 
#define NHMEX_W_MSR_PMON_CNT0   0xc90
 
#define NHMEX_W_MSR_PMON_EVT_SEL0   0xc91
 
#define NHMEX_W_MSR_PMON_FIXED_CTR   0x394
 
#define NHMEX_W_MSR_PMON_FIXED_CTL   0x395
 
#define NHMEX_W_PMON_GLOBAL_FIXED_EN   (1ULL << 31)
 
#define pmu_group   attr_groups[0]
 
#define format_group   attr_groups[1]
 
#define events_group   attr_groups[2]
 
#define UNCORE_BOX_FLAG_INITIATED   0
 
#define INTEL_UNCORE_EVENT_DESC(_name, _config)
 
#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)
 

Macro Definition Documentation

#define DEFINE_UNCORE_FORMAT_ATTR (   _var,
  _name,
  _format 
)
Value:
static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
struct kobj_attribute *attr, \
char *page) \
{ \
BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
return sprintf(page, _format "\n"); \
} \
static struct kobj_attribute format_attr_##_var = \
__ATTR(_name, 0444, __uncore_##_var##_show, NULL)

Definition at line 439 of file perf_event_intel_uncore.h.

#define events_group   attr_groups[2]

Definition at line 377 of file perf_event_intel_uncore.h.

#define format_group   attr_groups[1]

Definition at line 376 of file perf_event_intel_uncore.h.

#define INTEL_UNCORE_EVENT_DESC (   _name,
  _config 
)
Value:
{ \
.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
.config = _config, \
}

Definition at line 433 of file perf_event_intel_uncore.h.

#define MBOX_INC_SEL (   x)    ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)

Definition at line 289 of file perf_event_intel_uncore.h.

#define MBOX_INC_SEL_EXTAR_REG (   c,
  r 
)
Value:
EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)

Definition at line 296 of file perf_event_intel_uncore.h.

#define MBOX_INC_SEL_MASK
Value:
(NHMEX_M_PMON_CTL_INC_SEL_MASK | \
NHMEX_M_PMON_CTL_FLAG_MODE)

Definition at line 292 of file perf_event_intel_uncore.h.

#define MBOX_SET_FLAG_SEL (   x)
Value:
(((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
NHMEX_M_PMON_CTL_FLAG_MODE)

Definition at line 290 of file perf_event_intel_uncore.h.

#define MBOX_SET_FLAG_SEL_EXTRA_REG (   c,
  r 
)
Value:
EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
MBOX_SET_FLAG_SEL_MASK, \
(u64)-1, NHMEX_M_##r)

Definition at line 299 of file perf_event_intel_uncore.h.

#define MBOX_SET_FLAG_SEL_MASK
Value:
(NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
NHMEX_M_PMON_CTL_FLAG_MODE)

Definition at line 294 of file perf_event_intel_uncore.h.

#define NHM_UNC_CTL_CMASK_MASK   0xff000000

Definition at line 24 of file perf_event_intel_uncore.h.

#define NHM_UNC_FIXED_CTR   0x394

Definition at line 55 of file perf_event_intel_uncore.h.

#define NHM_UNC_FIXED_CTR_CTL_EN   (1 << 0)

Definition at line 25 of file perf_event_intel_uncore.h.

#define NHM_UNC_FIXED_CTR_CTRL   0x395

Definition at line 56 of file perf_event_intel_uncore.h.

#define NHM_UNC_GLOBAL_CTL_EN_FC   (1ULL << 32)

Definition at line 60 of file perf_event_intel_uncore.h.

#define NHM_UNC_GLOBAL_CTL_EN_PC_ALL   ((1ULL << 8) - 1)

Definition at line 59 of file perf_event_intel_uncore.h.

#define NHM_UNC_PERF_GLOBAL_CTL   0x391

Definition at line 54 of file perf_event_intel_uncore.h.

#define NHM_UNC_PERFEVTSEL0   0x3c0

Definition at line 63 of file perf_event_intel_uncore.h.

#define NHM_UNC_RAW_EVENT_MASK
Value:
(SNB_UNC_CTL_EV_SEL_MASK | \
SNB_UNC_CTL_UMASK_MASK | \
SNB_UNC_CTL_EDGE_DET | \
SNB_UNC_CTL_INVERT | \
NHM_UNC_CTL_CMASK_MASK)

Definition at line 33 of file perf_event_intel_uncore.h.

#define NHM_UNC_UNCORE_PMC0   0x3b0

Definition at line 64 of file perf_event_intel_uncore.h.

#define NHMEX_B0_MSR_MASK   0xe46

Definition at line 205 of file perf_event_intel_uncore.h.

#define NHMEX_B0_MSR_MATCH   0xe45

Definition at line 204 of file perf_event_intel_uncore.h.

#define NHMEX_B0_MSR_PMON_CTL0   0xc30

Definition at line 202 of file perf_event_intel_uncore.h.

#define NHMEX_B0_MSR_PMON_CTR0   0xc31

Definition at line 201 of file perf_event_intel_uncore.h.

#define NHMEX_B0_MSR_PMON_GLOBAL_CTL   0xc20

Definition at line 200 of file perf_event_intel_uncore.h.

#define NHMEX_B1_MSR_MASK   0xe4e

Definition at line 207 of file perf_event_intel_uncore.h.

#define NHMEX_B1_MSR_MATCH   0xe4d

Definition at line 206 of file perf_event_intel_uncore.h.

#define NHMEX_B_MSR_OFFSET   0x40

Definition at line 203 of file perf_event_intel_uncore.h.

#define NHMEX_B_PMON_CTL_EN   (1 << 0)

Definition at line 209 of file perf_event_intel_uncore.h.

#define NHMEX_B_PMON_CTL_EV_SEL_MASK   (0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)

Definition at line 211 of file perf_event_intel_uncore.h.

#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT   1

Definition at line 210 of file perf_event_intel_uncore.h.

#define NHMEX_B_PMON_CTR_MASK   (0x3 << NHMEX_B_PMON_CTR_SHIFT)

Definition at line 214 of file perf_event_intel_uncore.h.

#define NHMEX_B_PMON_CTR_SHIFT   6

Definition at line 213 of file perf_event_intel_uncore.h.

#define NHMEX_B_PMON_RAW_EVENT_MASK
Value:
(NHMEX_B_PMON_CTL_EV_SEL_MASK | \
NHMEX_B_PMON_CTR_MASK)

Definition at line 216 of file perf_event_intel_uncore.h.

#define NHMEX_C0_MSR_PMON_CTR0   0xd11

Definition at line 195 of file perf_event_intel_uncore.h.

#define NHMEX_C0_MSR_PMON_EV_SEL0   0xd10

Definition at line 196 of file perf_event_intel_uncore.h.

#define NHMEX_C0_MSR_PMON_GLOBAL_CTL   0xd00

Definition at line 194 of file perf_event_intel_uncore.h.

#define NHMEX_C_MSR_OFFSET   0x20

Definition at line 197 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_GLOBAL_CTL   0xca0

Definition at line 236 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_CNT0   0xcb1

Definition at line 245 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_CTL0   0xcb0

Definition at line 244 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_DSP   0xca5

Definition at line 237 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_ISS   0xca6

Definition at line 238 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_MAP   0xca7

Definition at line 239 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_MM_CFG   0xe54

Definition at line 247 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_MSC_THR   0xca8

Definition at line 240 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_PGT   0xca9

Definition at line 241 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_PLD   0xcaa

Definition at line 242 of file perf_event_intel_uncore.h.

#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC   0xcab

Definition at line 243 of file perf_event_intel_uncore.h.

#define NHMEX_M1_MSR_PMU_MM_CFG   0xe5c

Definition at line 248 of file perf_event_intel_uncore.h.

#define NHMEX_M_MSR_OFFSET   0x40

Definition at line 246 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_ADDR_MASK_MASK   0x7ffffffULL

Definition at line 252 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_ADDR_MASK_SHIFT   34

Definition at line 253 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_ADDR_MATCH_MASK   0x3ffffffffULL

Definition at line 251 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK   (0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)

Definition at line 258 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT   2

Definition at line 257 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_EN   (1 << 0)

Definition at line 255 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_FLAG_MODE   (1 << 7)

Definition at line 264 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_INC_SEL_MASK   (0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)

Definition at line 266 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT   9

Definition at line 265 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_PMI_EN   (1 << 1)

Definition at line 256 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK   (0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)

Definition at line 269 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT   19

Definition at line 268 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK   (0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)

Definition at line 261 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT   4

Definition at line 260 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_CTL_WRAP_MODE   (1 << 6)

Definition at line 263 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_MM_CFG_EN   (1ULL << 63)

Definition at line 250 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_RAW_EVENT_MASK
Value:
(NHMEX_M_PMON_CTL_COUNT_MODE_MASK | \
NHMEX_M_PMON_CTL_STORAGE_MODE_MASK | \
NHMEX_M_PMON_CTL_WRAP_MODE | \
NHMEX_M_PMON_CTL_FLAG_MODE | \
NHMEX_M_PMON_CTL_INC_SEL_MASK | \
NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)

Definition at line 271 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK (   n)    (0x7 << (11 + 3 * (n)))

Definition at line 280 of file perf_event_intel_uncore.h.

#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK   (((1 << 11) - 1) | (1 << 23))

Definition at line 279 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_EDGE_DET   (1 << 18)

Definition at line 167 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_EN_BIT0   (1 << 0)

Definition at line 166 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_EN_BIT22   (1 << 22)

Definition at line 169 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_EV_SEL_MASK   0x000000ff

Definition at line 164 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_INVERT   (1 << 23)

Definition at line 170 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_PMI_EN   (1 << 20)

Definition at line 168 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_TRESH_MASK   0xff000000

Definition at line 171 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_CTL_UMASK_MASK   0x0000ff00

Definition at line 165 of file perf_event_intel_uncore.h.

#define NHMEX_PMON_RAW_EVENT_MASK
Value:
(NHMEX_PMON_CTL_EV_SEL_MASK | \
NHMEX_PMON_CTL_UMASK_MASK | \
NHMEX_PMON_CTL_EDGE_DET | \
NHMEX_PMON_CTL_INVERT | \
NHMEX_PMON_CTL_TRESH_MASK)

Definition at line 172 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_GLOBAL_CTL   0xe00

Definition at line 305 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_OFFSET   0x20

Definition at line 308 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PMON_CNT0   0xe11

Definition at line 307 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PMON_CTL0   0xe10

Definition at line 306 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_IPERF_CFG0 (   n)    (0xe04 + (n))

Definition at line 312 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_IPERF_CFG1 (   n)    (0xe24 + (n))

Definition at line 313 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_QLX_CFG (   n)    ((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))

Definition at line 310 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_OFFSET (   n)    (((n) < 4 ? 0 : 0x10) + (n) * 4)

Definition at line 314 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK (   n)    (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)

Definition at line 320 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH (   n)    (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)

Definition at line 318 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG (   n)    (0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))

Definition at line 316 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK (   n)    (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)

Definition at line 326 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH (   n)    (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)

Definition at line 324 of file perf_event_intel_uncore.h.

#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG (   n)    (0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))

Definition at line 322 of file perf_event_intel_uncore.h.

#define NHMEX_R_PMON_CTL_EN   (1 << 0)

Definition at line 329 of file perf_event_intel_uncore.h.

#define NHMEX_R_PMON_CTL_EV_SEL_MASK   (0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)

Definition at line 331 of file perf_event_intel_uncore.h.

#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT   1

Definition at line 330 of file perf_event_intel_uncore.h.

#define NHMEX_R_PMON_CTL_PMI_EN   (1 << 6)

Definition at line 333 of file perf_event_intel_uncore.h.

#define NHMEX_R_PMON_RAW_EVENT_MASK   NHMEX_R_PMON_CTL_EV_SEL_MASK

Definition at line 334 of file perf_event_intel_uncore.h.

#define NHMEX_S0_MSR_MASK   0xe4a

Definition at line 227 of file perf_event_intel_uncore.h.

#define NHMEX_S0_MSR_MATCH   0xe49

Definition at line 226 of file perf_event_intel_uncore.h.

#define NHMEX_S0_MSR_MM_CFG   0xe48

Definition at line 225 of file perf_event_intel_uncore.h.

#define NHMEX_S0_MSR_PMON_CTL0   0xc50

Definition at line 223 of file perf_event_intel_uncore.h.

#define NHMEX_S0_MSR_PMON_CTR0   0xc51

Definition at line 222 of file perf_event_intel_uncore.h.

#define NHMEX_S0_MSR_PMON_GLOBAL_CTL   0xc40

Definition at line 221 of file perf_event_intel_uncore.h.

#define NHMEX_S1_MSR_MASK   0xe5a

Definition at line 230 of file perf_event_intel_uncore.h.

#define NHMEX_S1_MSR_MATCH   0xe59

Definition at line 229 of file perf_event_intel_uncore.h.

#define NHMEX_S1_MSR_MM_CFG   0xe58

Definition at line 228 of file perf_event_intel_uncore.h.

#define NHMEX_S_EVENT_TO_R_PROG_EV   0

Definition at line 233 of file perf_event_intel_uncore.h.

#define NHMEX_S_MSR_OFFSET   0x80

Definition at line 224 of file perf_event_intel_uncore.h.

#define NHMEX_S_PMON_MM_CFG_EN   (0x1ULL << 63)

Definition at line 232 of file perf_event_intel_uncore.h.

#define NHMEX_U_MSR_PMON_CTR   0xc11

Definition at line 180 of file perf_event_intel_uncore.h.

#define NHMEX_U_MSR_PMON_EV_SEL   0xc10

Definition at line 181 of file perf_event_intel_uncore.h.

#define NHMEX_U_MSR_PMON_GLOBAL_CTL   0xc00

Definition at line 179 of file perf_event_intel_uncore.h.

#define NHMEX_U_PMON_GLOBAL_EN   (1 << 0)

Definition at line 183 of file perf_event_intel_uncore.h.

#define NHMEX_U_PMON_GLOBAL_EN_ALL   (1 << 28)

Definition at line 185 of file perf_event_intel_uncore.h.

#define NHMEX_U_PMON_GLOBAL_FRZ_ALL   (1 << 31)

Definition at line 187 of file perf_event_intel_uncore.h.

#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL   0x0000001e

Definition at line 184 of file perf_event_intel_uncore.h.

#define NHMEX_U_PMON_GLOBAL_RST_ALL   (1 << 29)

Definition at line 186 of file perf_event_intel_uncore.h.

#define NHMEX_U_PMON_RAW_EVENT_MASK
Value:
(NHMEX_PMON_CTL_EV_SEL_MASK | \
NHMEX_PMON_CTL_EDGE_DET)

Definition at line 189 of file perf_event_intel_uncore.h.

#define NHMEX_W_MSR_GLOBAL_CTL   0xc80

Definition at line 337 of file perf_event_intel_uncore.h.

#define NHMEX_W_MSR_PMON_CNT0   0xc90

Definition at line 338 of file perf_event_intel_uncore.h.

#define NHMEX_W_MSR_PMON_EVT_SEL0   0xc91

Definition at line 339 of file perf_event_intel_uncore.h.

#define NHMEX_W_MSR_PMON_FIXED_CTL   0x395

Definition at line 341 of file perf_event_intel_uncore.h.

#define NHMEX_W_MSR_PMON_FIXED_CTR   0x394

Definition at line 340 of file perf_event_intel_uncore.h.

#define NHMEX_W_PMON_GLOBAL_FIXED_EN   (1ULL << 31)

Definition at line 343 of file perf_event_intel_uncore.h.

#define pmu_group   attr_groups[0]

Definition at line 375 of file perf_event_intel_uncore.h.

#define SNB_UNC_CBO_0_PER_CTR0   0x706

Definition at line 50 of file perf_event_intel_uncore.h.

#define SNB_UNC_CBO_0_PERFEVTSEL0   0x700

Definition at line 49 of file perf_event_intel_uncore.h.

#define SNB_UNC_CBO_MSR_OFFSET   0x10

Definition at line 51 of file perf_event_intel_uncore.h.

#define SNB_UNC_CTL_CMASK_MASK   0x1f000000

Definition at line 23 of file perf_event_intel_uncore.h.

#define SNB_UNC_CTL_EDGE_DET   (1 << 18)

Definition at line 20 of file perf_event_intel_uncore.h.

#define SNB_UNC_CTL_EN   (1 << 22)

Definition at line 21 of file perf_event_intel_uncore.h.

#define SNB_UNC_CTL_EV_SEL_MASK   0x000000ff

Definition at line 18 of file perf_event_intel_uncore.h.

#define SNB_UNC_CTL_INVERT   (1 << 23)

Definition at line 22 of file perf_event_intel_uncore.h.

#define SNB_UNC_CTL_UMASK_MASK   0x0000ff00

Definition at line 19 of file perf_event_intel_uncore.h.

#define SNB_UNC_FIXED_CTR   0x395

Definition at line 42 of file perf_event_intel_uncore.h.

#define SNB_UNC_FIXED_CTR_CTRL   0x394

Definition at line 41 of file perf_event_intel_uncore.h.

#define SNB_UNC_GLOBAL_CTL_CORE_ALL   ((1 << 4) - 1)

Definition at line 45 of file perf_event_intel_uncore.h.

#define SNB_UNC_GLOBAL_CTL_EN   (1 << 29)

Definition at line 46 of file perf_event_intel_uncore.h.

#define SNB_UNC_PERF_GLOBAL_CTL   0x391

Definition at line 40 of file perf_event_intel_uncore.h.

#define SNB_UNC_RAW_EVENT_MASK
Value:
(SNB_UNC_CTL_EV_SEL_MASK | \
SNB_UNC_CTL_UMASK_MASK | \
SNB_UNC_CTL_EDGE_DET | \
SNB_UNC_CTL_INVERT | \
SNB_UNC_CTL_CMASK_MASK)

Definition at line 27 of file perf_event_intel_uncore.h.

#define SNBEP_C0_MSR_PMON_BOX_CTL   0xd04

Definition at line 149 of file perf_event_intel_uncore.h.

#define SNBEP_C0_MSR_PMON_BOX_FILTER   0xd14

Definition at line 150 of file perf_event_intel_uncore.h.

#define SNBEP_C0_MSR_PMON_CTL0   0xd10

Definition at line 148 of file perf_event_intel_uncore.h.

#define SNBEP_C0_MSR_PMON_CTR0   0xd16

Definition at line 147 of file perf_event_intel_uncore.h.

#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK   0xfffffc1f

Definition at line 151 of file perf_event_intel_uncore.h.

#define SNBEP_CBO_MSR_OFFSET   0x20

Definition at line 152 of file perf_event_intel_uncore.h.

#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK
Value:
(SNBEP_PMON_RAW_EVENT_MASK | \
SNBEP_CBO_PMON_CTL_TID_EN)

Definition at line 99 of file perf_event_intel_uncore.h.

#define SNBEP_CBO_PMON_CTL_TID_EN   (1 << 19)

Definition at line 98 of file perf_event_intel_uncore.h.

#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0   0x40

Definition at line 127 of file perf_event_intel_uncore.h.

#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1   0x44

Definition at line 128 of file perf_event_intel_uncore.h.

#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH   0x48

Definition at line 129 of file perf_event_intel_uncore.h.

#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL   0xf0

Definition at line 131 of file perf_event_intel_uncore.h.

#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR   0xd0

Definition at line 132 of file perf_event_intel_uncore.h.

#define SNBEP_PCI_PMON_BOX_CTL   0xf4

Definition at line 121 of file perf_event_intel_uncore.h.

#define SNBEP_PCI_PMON_CTL0   0xd8

Definition at line 122 of file perf_event_intel_uncore.h.

#define SNBEP_PCI_PMON_CTR0   0xa0

Definition at line 124 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_CORE_C3_CTR   0x3fc

Definition at line 160 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_CORE_C6_CTR   0x3fd

Definition at line 161 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_BOX_CTL   0xc24

Definition at line 157 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_BOX_FILTER   0xc34

Definition at line 158 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK   0xffffffff

Definition at line 159 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_CTL0   0xc30

Definition at line 156 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET   (1 << 31)

Definition at line 106 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT   (1 << 30)

Definition at line 105 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK   0x0000c000

Definition at line 103 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK   0x1f000000

Definition at line 104 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_CTR0   0xc36

Definition at line 155 of file perf_event_intel_uncore.h.

#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK
Value:
(SNBEP_PMON_CTL_EV_SEL_MASK | \
SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
SNBEP_PMON_CTL_EDGE_DET | \
SNBEP_PMON_CTL_INVERT | \
SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)

Definition at line 107 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_BOX_CTL_FRZ   (1 << 8)

Definition at line 69 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_BOX_CTL_FRZ_EN   (1 << 16)

Definition at line 70 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_BOX_CTL_INT
Value:
(SNBEP_PMON_BOX_CTL_RST_CTRL | \
SNBEP_PMON_BOX_CTL_RST_CTRS | \
SNBEP_PMON_BOX_CTL_FRZ_EN)

Definition at line 71 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_BOX_CTL_RST_CTRL   (1 << 0)

Definition at line 67 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_BOX_CTL_RST_CTRS   (1 << 1)

Definition at line 68 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_EDGE_DET   (1 << 18)

Definition at line 78 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_EN   (1 << 22)

Definition at line 80 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_EV_SEL_EXT   (1 << 21) /* only for QPI */

Definition at line 79 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_EV_SEL_MASK   0x000000ff

Definition at line 75 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_INVERT   (1 << 23)

Definition at line 81 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_RST   (1 << 17)

Definition at line 77 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_TRESH_MASK   0xff000000

Definition at line 82 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_CTL_UMASK_MASK   0x0000ff00

Definition at line 76 of file perf_event_intel_uncore.h.

#define SNBEP_PMON_RAW_EVENT_MASK
Value:
(SNBEP_PMON_CTL_EV_SEL_MASK | \
SNBEP_PMON_CTL_UMASK_MASK | \
SNBEP_PMON_CTL_EDGE_DET | \
SNBEP_PMON_CTL_INVERT | \
SNBEP_PMON_CTL_TRESH_MASK)

Definition at line 83 of file perf_event_intel_uncore.h.

#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0   0x238

Definition at line 136 of file perf_event_intel_uncore.h.

#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1   0x23c

Definition at line 137 of file perf_event_intel_uncore.h.

#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0   0x228

Definition at line 134 of file perf_event_intel_uncore.h.

#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1   0x22c

Definition at line 135 of file perf_event_intel_uncore.h.

#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK
Value:
(SNBEP_PMON_RAW_EVENT_MASK | \
SNBEP_PMON_CTL_EV_SEL_EXT)

Definition at line 116 of file perf_event_intel_uncore.h.

#define SNBEP_U_MSR_PMON_CTL0   0xc10

Definition at line 141 of file perf_event_intel_uncore.h.

#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK   0x1f000000

Definition at line 90 of file perf_event_intel_uncore.h.

#define SNBEP_U_MSR_PMON_CTR0   0xc16

Definition at line 140 of file perf_event_intel_uncore.h.

#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK
Value:
(SNBEP_PMON_CTL_EV_SEL_MASK | \
SNBEP_PMON_CTL_UMASK_MASK | \
SNBEP_PMON_CTL_EDGE_DET | \
SNBEP_PMON_CTL_INVERT | \
SNBEP_U_MSR_PMON_CTL_TRESH_MASK)

Definition at line 91 of file perf_event_intel_uncore.h.

#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL   0xc08

Definition at line 143 of file perf_event_intel_uncore.h.

#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR   0xc09

Definition at line 144 of file perf_event_intel_uncore.h.

#define UNCORE_BOX_FLAG_INITIATED   0

Definition at line 426 of file perf_event_intel_uncore.h.

#define UNCORE_EVENT_CONSTRAINT (   c,
  n 
)    EVENT_CONSTRAINT(c, n, 0xff)

Definition at line 15 of file perf_event_intel_uncore.h.

#define UNCORE_FIXED_EVENT   0xff

Definition at line 10 of file perf_event_intel_uncore.h.

#define UNCORE_PMC_IDX_FIXED   UNCORE_PMC_IDX_MAX_GENERIC

Definition at line 12 of file perf_event_intel_uncore.h.

#define UNCORE_PMC_IDX_MAX   (UNCORE_PMC_IDX_FIXED + 1)

Definition at line 13 of file perf_event_intel_uncore.h.

#define UNCORE_PMC_IDX_MAX_GENERIC   8

Definition at line 11 of file perf_event_intel_uncore.h.

#define UNCORE_PMU_HRTIMER_INTERVAL   (60LL * NSEC_PER_SEC)

Definition at line 8 of file perf_event_intel_uncore.h.

#define UNCORE_PMU_NAME_LEN   32

Definition at line 7 of file perf_event_intel_uncore.h.

#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK (   n)    (0x7 << (12 + 3 * (n)))

Definition at line 283 of file perf_event_intel_uncore.h.

#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK   (((1 << 12) - 1) | (1 << 24))

Definition at line 282 of file perf_event_intel_uncore.h.

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