perf_event_p4.h File Reference

#include <linux/cpu.h>
#include <linux/bitops.h>

Go to the source code of this file.

Macros
#define	ARCH_P4_TOTAL_ESCR   (46)
#define	ARCH_P4_RESERVED_ESCR   (2) /* IQ_ESCR(0,1) not always present */
#define	ARCH_P4_MAX_ESCR   (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
#define	ARCH_P4_MAX_CCCR   (18)
#define	ARCH_P4_CNTRVAL_BITS   (40)
#define	ARCH_P4_CNTRVAL_MASK   ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
#define	ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
#define	P4_ESCR_EVENT_MASK   0x7e000000U
#define	P4_ESCR_EVENT_SHIFT   25
#define	P4_ESCR_EVENTMASK_MASK   0x01fffe00U
#define	P4_ESCR_EVENTMASK_SHIFT   9
#define	P4_ESCR_TAG_MASK   0x000001e0U
#define	P4_ESCR_TAG_SHIFT   5
#define	P4_ESCR_TAG_ENABLE   0x00000010U
#define	P4_ESCR_T0_OS   0x00000008U
#define	P4_ESCR_T0_USR   0x00000004U
#define	P4_ESCR_T1_OS   0x00000002U
#define	P4_ESCR_T1_USR   0x00000001U
#define	P4_ESCR_EVENT(v)   ((v) << P4_ESCR_EVENT_SHIFT)
#define	P4_ESCR_EMASK(v)   ((v) << P4_ESCR_EVENTMASK_SHIFT)
#define	P4_ESCR_TAG(v)   ((v) << P4_ESCR_TAG_SHIFT)
#define	P4_CCCR_OVF   0x80000000U
#define	P4_CCCR_CASCADE   0x40000000U
#define	P4_CCCR_OVF_PMI_T0   0x04000000U
#define	P4_CCCR_OVF_PMI_T1   0x08000000U
#define	P4_CCCR_FORCE_OVF   0x02000000U
#define	P4_CCCR_EDGE   0x01000000U
#define	P4_CCCR_THRESHOLD_MASK   0x00f00000U
#define	P4_CCCR_THRESHOLD_SHIFT   20
#define	P4_CCCR_COMPLEMENT   0x00080000U
#define	P4_CCCR_COMPARE   0x00040000U
#define	P4_CCCR_ESCR_SELECT_MASK   0x0000e000U
#define	P4_CCCR_ESCR_SELECT_SHIFT   13
#define	P4_CCCR_ENABLE   0x00001000U
#define	P4_CCCR_THREAD_SINGLE   0x00010000U
#define	P4_CCCR_THREAD_BOTH   0x00020000U
#define	P4_CCCR_THREAD_ANY   0x00030000U
#define	P4_CCCR_RESERVED   0x00000fffU
#define	P4_CCCR_THRESHOLD(v)   ((v) << P4_CCCR_THRESHOLD_SHIFT)
#define	P4_CCCR_ESEL(v)   ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
#define	P4_GEN_ESCR_EMASK(class, name, bit)   class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
#define	P4_ESCR_EMASK_BIT(class, name)   class##__##name
#define	p4_config_pack_escr(v)   (((u64)(v)) << 32)
#define	p4_config_pack_cccr(v)   (((u64)(v)) & 0xffffffffULL)
#define	p4_config_unpack_escr(v)   (((u64)(v)) >> 32)
#define	p4_config_unpack_cccr(v)   (((u64)(v)) & 0xffffffffULL)
#define	p4_config_unpack_emask(v)
#define	p4_config_unpack_event(v)
#define	P4_CONFIG_HT_SHIFT   63
#define	P4_CONFIG_HT   (1ULL << P4_CONFIG_HT_SHIFT)
#define	P4_CONFIG_ALIASABLE   (1 << 9)
#define	P4_CONFIG_MASK_ESCR
#define	P4_CONFIG_MASK_CCCR
#define	P4_CONFIG_MASK
#define	P4_CONFIG_EVENT_ALIAS_MASK
#define	P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS
#define	P4_OPCODE(event)   event##_OPCODE
#define	P4_OPCODE_ESEL(opcode)   ((opcode & 0x00ff) >> 0)
#define	P4_OPCODE_EVNT(opcode)   ((opcode & 0xff00) >> 8)
#define	P4_OPCODE_PACK(event, sel)   (((event) << 8) | sel)
#define	P4_PEBS_CONFIG_ENABLE   (1 << 7)
#define	P4_PEBS_CONFIG_UOP_TAG   (1 << 8)
#define	P4_PEBS_CONFIG_METRIC_MASK   0x3f
#define	P4_PEBS_CONFIG_MASK   0xff
#define	P4_PEBS_ENABLE   0x02000000U
#define	P4_PEBS_ENABLE_UOP_TAG   0x01000000U
#define	p4_config_unpack_metric(v)   (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
#define	p4_config_unpack_pebs(v)   (((u64)(v)) & P4_PEBS_CONFIG_MASK)
#define	p4_config_pebs_has(v, mask)   (p4_config_unpack_pebs(v) & (mask))

Enumerations
enum	P4_EVENTS {   P4_EVENT_TC_DELIVER_MODE, P4_EVENT_BPU_FETCH_REQUEST, P4_EVENT_ITLB_REFERENCE, P4_EVENT_MEMORY_CANCEL,   P4_EVENT_MEMORY_COMPLETE, P4_EVENT_LOAD_PORT_REPLAY, P4_EVENT_STORE_PORT_REPLAY, P4_EVENT_MOB_LOAD_REPLAY,   P4_EVENT_PAGE_WALK_TYPE, P4_EVENT_BSQ_CACHE_REFERENCE, P4_EVENT_IOQ_ALLOCATION, P4_EVENT_IOQ_ACTIVE_ENTRIES,   P4_EVENT_FSB_DATA_ACTIVITY, P4_EVENT_BSQ_ALLOCATION, P4_EVENT_BSQ_ACTIVE_ENTRIES, P4_EVENT_SSE_INPUT_ASSIST,   P4_EVENT_PACKED_SP_UOP, P4_EVENT_PACKED_DP_UOP, P4_EVENT_SCALAR_SP_UOP, P4_EVENT_SCALAR_DP_UOP,   P4_EVENT_64BIT_MMX_UOP, P4_EVENT_128BIT_MMX_UOP, P4_EVENT_X87_FP_UOP, P4_EVENT_TC_MISC,   P4_EVENT_GLOBAL_POWER_EVENTS, P4_EVENT_TC_MS_XFER, P4_EVENT_UOP_QUEUE_WRITES, P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,   P4_EVENT_RETIRED_BRANCH_TYPE, P4_EVENT_RESOURCE_STALL, P4_EVENT_WC_BUFFER, P4_EVENT_B2B_CYCLES,   P4_EVENT_BNR, P4_EVENT_SNOOP, P4_EVENT_RESPONSE, P4_EVENT_FRONT_END_EVENT,   P4_EVENT_EXECUTION_EVENT, P4_EVENT_REPLAY_EVENT, P4_EVENT_INSTR_RETIRED, P4_EVENT_UOPS_RETIRED,   P4_EVENT_UOP_TYPE, P4_EVENT_BRANCH_RETIRED, P4_EVENT_MISPRED_BRANCH_RETIRED, P4_EVENT_X87_ASSIST,   P4_EVENT_MACHINE_CLEAR, P4_EVENT_INSTR_COMPLETED }
enum	P4_EVENT_OPCODES {   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),   P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01), P4_OPCODE =(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01) }
enum	P4_ESCR_EMASKS {   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0),   P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0), P4_GEN_ESCR_EMASK =(P4_EVENT_TC_DELIVER_MODE, DD, 0) }
enum	P4_PEBS_METRIC {   P4_PEBS_METRIC__none, P4_PEBS_METRIC__1stl_cache_load_miss_retired, P4_PEBS_METRIC__2ndl_cache_load_miss_retired, P4_PEBS_METRIC__dtlb_load_miss_retired,   P4_PEBS_METRIC__dtlb_store_miss_retired, P4_PEBS_METRIC__dtlb_all_miss_retired, P4_PEBS_METRIC__tagged_mispred_branch, P4_PEBS_METRIC__mob_load_replay_retired,   P4_PEBS_METRIC__split_load_retired, P4_PEBS_METRIC__split_store_retired, P4_PEBS_METRIC__max }

Macro Definition Documentation

#define ARCH_P4_CNTRVAL_BITS   (40)

Definition at line 23 of file perf_event_p4.h.

#define ARCH_P4_CNTRVAL_MASK   ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)

Definition at line 24 of file perf_event_p4.h.

#define ARCH_P4_MAX_CCCR   (18)

Definition at line 21 of file perf_event_p4.h.

#define ARCH_P4_MAX_ESCR   (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)

Definition at line 20 of file perf_event_p4.h.

#define ARCH_P4_RESERVED_ESCR   (2) /* IQ_ESCR(0,1) not always present */

Definition at line 19 of file perf_event_p4.h.

#define ARCH_P4_TOTAL_ESCR   (46)

Definition at line 18 of file perf_event_p4.h.

#define ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))

Definition at line 25 of file perf_event_p4.h.

#define P4_CCCR_CASCADE   0x40000000U

Definition at line 44 of file perf_event_p4.h.

#define P4_CCCR_COMPARE   0x00040000U

Definition at line 52 of file perf_event_p4.h.

#define P4_CCCR_COMPLEMENT   0x00080000U

Definition at line 51 of file perf_event_p4.h.

#define P4_CCCR_EDGE   0x01000000U

Definition at line 48 of file perf_event_p4.h.

#define P4_CCCR_ENABLE   0x00001000U

Definition at line 55 of file perf_event_p4.h.

#define P4_CCCR_ESCR_SELECT_MASK   0x0000e000U

Definition at line 53 of file perf_event_p4.h.

#define P4_CCCR_ESCR_SELECT_SHIFT   13

Definition at line 54 of file perf_event_p4.h.

#define P4_CCCR_ESEL

(

v

)

((v) << P4_CCCR_ESCR_SELECT_SHIFT)

Definition at line 62 of file perf_event_p4.h.

#define P4_CCCR_FORCE_OVF   0x02000000U

Definition at line 47 of file perf_event_p4.h.

#define P4_CCCR_OVF   0x80000000U

Definition at line 43 of file perf_event_p4.h.

#define P4_CCCR_OVF_PMI_T0   0x04000000U

Definition at line 45 of file perf_event_p4.h.

#define P4_CCCR_OVF_PMI_T1   0x08000000U

Definition at line 46 of file perf_event_p4.h.

#define P4_CCCR_RESERVED   0x00000fffU

Definition at line 59 of file perf_event_p4.h.

#define P4_CCCR_THREAD_ANY   0x00030000U

Definition at line 58 of file perf_event_p4.h.

#define P4_CCCR_THREAD_BOTH   0x00020000U

Definition at line 57 of file perf_event_p4.h.

#define P4_CCCR_THREAD_SINGLE   0x00010000U

Definition at line 56 of file perf_event_p4.h.

#define P4_CCCR_THRESHOLD

(

v

)

((v) << P4_CCCR_THRESHOLD_SHIFT)

Definition at line 61 of file perf_event_p4.h.

#define P4_CCCR_THRESHOLD_MASK   0x00f00000U

Definition at line 49 of file perf_event_p4.h.

#define P4_CCCR_THRESHOLD_SHIFT   20

Definition at line 50 of file perf_event_p4.h.

#define P4_CONFIG_ALIASABLE   (1 << 9)

Definition at line 110 of file perf_event_p4.h.

#define P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS

Value:

((P4_CONFIG_HT)                 | \
     p4_config_pack_escr(P4_ESCR_T0_OS      | \
                 P4_ESCR_T0_USR     | \
                 P4_ESCR_T1_OS      | \
                 P4_ESCR_T1_USR)        | \
     p4_config_pack_cccr(P4_CCCR_OVF        | \
                 P4_CCCR_CASCADE        | \
                 P4_CCCR_FORCE_OVF      | \
                 P4_CCCR_THREAD_ANY     | \
                 P4_CCCR_OVF_PMI_T0     | \
                 P4_CCCR_OVF_PMI_T1     | \
                 P4_CONFIG_ALIASABLE))

Definition at line 145 of file perf_event_p4.h.

#define P4_CONFIG_EVENT_ALIAS_MASK

Value:

(p4_config_pack_escr(P4_CONFIG_MASK_ESCR)   | \
     p4_config_pack_cccr(P4_CCCR_EDGE       | \
                 P4_CCCR_THRESHOLD_MASK | \
                 P4_CCCR_COMPLEMENT     | \
                 P4_CCCR_COMPARE))

Definition at line 138 of file perf_event_p4.h.

#define P4_CONFIG_HT   (1ULL << P4_CONFIG_HT_SHIFT)

Definition at line 102 of file perf_event_p4.h.

#define P4_CONFIG_HT_SHIFT   63

Definition at line 101 of file perf_event_p4.h.

#define P4_CONFIG_MASK

Value:

(p4_config_pack_escr(P4_CONFIG_MASK_ESCR))  | \
    (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))

Definition at line 130 of file perf_event_p4.h.

#define P4_CONFIG_MASK_CCCR

Value:

P4_CCCR_EDGE        |   \
    P4_CCCR_THRESHOLD_MASK  |   \
    P4_CCCR_COMPLEMENT  |   \
    P4_CCCR_COMPARE     |   \
    P4_CCCR_THREAD_ANY  |   \
    P4_CCCR_RESERVED

Definition at line 121 of file perf_event_p4.h.

#define P4_CONFIG_MASK_ESCR

Value:

P4_ESCR_EVENT_MASK  |   \
    P4_ESCR_EVENTMASK_MASK  |   \
    P4_ESCR_TAG_MASK    |   \
    P4_ESCR_TAG_ENABLE

Definition at line 115 of file perf_event_p4.h.

#define p4_config_pack_cccr

(

v

)

(((u64)(v)) & 0xffffffffULL)

Definition at line 81 of file perf_event_p4.h.

#define p4_config_pack_escr

(

v

)

(((u64)(v)) << 32)

Definition at line 80 of file perf_event_p4.h.

#define p4_config_pebs_has	(		v,
			mask
	)		(p4_config_unpack_pebs(v) & (mask))

Definition at line 802 of file perf_event_p4.h.

#define p4_config_unpack_cccr

(

v

)

(((u64)(v)) & 0xffffffffULL)

Definition at line 83 of file perf_event_p4.h.

#define p4_config_unpack_emask

(

v

)

Value:

({                      \
		u32 t = p4_config_unpack_escr((v));   \
        t = t &  P4_ESCR_EVENTMASK_MASK;    \
        t = t >> P4_ESCR_EVENTMASK_SHIFT;   \
        t;                  \
    })

Definition at line 85 of file perf_event_p4.h.

#define p4_config_unpack_escr

(

v

)

(((u64)(v)) >> 32)

Definition at line 82 of file perf_event_p4.h.

#define p4_config_unpack_event

(

v

)

Value:

({                      \
		u32 t = p4_config_unpack_escr((v));   \
        t = t &  P4_ESCR_EVENT_MASK;        \
        t = t >> P4_ESCR_EVENT_SHIFT;       \
        t;                  \
    })

Definition at line 93 of file perf_event_p4.h.

#define p4_config_unpack_metric

(

v

)

(((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)

Definition at line 799 of file perf_event_p4.h.

#define p4_config_unpack_pebs

(

v

)

(((u64)(v)) & P4_PEBS_CONFIG_MASK)

Definition at line 800 of file perf_event_p4.h.

#define P4_ESCR_EMASK

(

v

)

((v) << P4_ESCR_EVENTMASK_SHIFT)

Definition at line 40 of file perf_event_p4.h.

#define P4_ESCR_EMASK_BIT	(		class,
			name
	)		class##__##name

Definition at line 66 of file perf_event_p4.h.

#define P4_ESCR_EVENT

(

v

)

((v) << P4_ESCR_EVENT_SHIFT)

Definition at line 39 of file perf_event_p4.h.

#define P4_ESCR_EVENT_MASK   0x7e000000U

Definition at line 27 of file perf_event_p4.h.

#define P4_ESCR_EVENT_SHIFT   25

Definition at line 28 of file perf_event_p4.h.

#define P4_ESCR_EVENTMASK_MASK   0x01fffe00U

Definition at line 29 of file perf_event_p4.h.

#define P4_ESCR_EVENTMASK_SHIFT   9

Definition at line 30 of file perf_event_p4.h.

#define P4_ESCR_T0_OS   0x00000008U

Definition at line 34 of file perf_event_p4.h.

#define P4_ESCR_T0_USR   0x00000004U

Definition at line 35 of file perf_event_p4.h.

#define P4_ESCR_T1_OS   0x00000002U

Definition at line 36 of file perf_event_p4.h.

#define P4_ESCR_T1_USR   0x00000001U

Definition at line 37 of file perf_event_p4.h.

#define P4_ESCR_TAG

(

v

)

((v) << P4_ESCR_TAG_SHIFT)

Definition at line 41 of file perf_event_p4.h.

#define P4_ESCR_TAG_ENABLE   0x00000010U

Definition at line 33 of file perf_event_p4.h.

#define P4_ESCR_TAG_MASK   0x000001e0U

Definition at line 31 of file perf_event_p4.h.

#define P4_ESCR_TAG_SHIFT   5

Definition at line 32 of file perf_event_p4.h.

#define P4_GEN_ESCR_EMASK	(		class,
			name,
			bit
	)		class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)

Definition at line 64 of file perf_event_p4.h.

#define P4_OPCODE

(

event

)

event##_OPCODE

Definition at line 293 of file perf_event_p4.h.

#define P4_OPCODE_ESEL

(

opcode

)

((opcode & 0x00ff) >> 0)

Definition at line 294 of file perf_event_p4.h.

#define P4_OPCODE_EVNT

(

opcode

)

((opcode & 0xff00) >> 8)

Definition at line 295 of file perf_event_p4.h.

#define P4_OPCODE_PACK	(		event,
			sel
	)		(((event) << 8) | sel)

Definition at line 296 of file perf_event_p4.h.

#define P4_PEBS_CONFIG_ENABLE   (1 << 7)

Definition at line 787 of file perf_event_p4.h.

#define P4_PEBS_CONFIG_MASK   0xff

Definition at line 790 of file perf_event_p4.h.

#define P4_PEBS_CONFIG_METRIC_MASK   0x3f

Definition at line 789 of file perf_event_p4.h.

#define P4_PEBS_CONFIG_UOP_TAG   (1 << 8)

Definition at line 788 of file perf_event_p4.h.

#define P4_PEBS_ENABLE   0x02000000U

Definition at line 796 of file perf_event_p4.h.

#define P4_PEBS_ENABLE_UOP_TAG   0x01000000U

Definition at line 797 of file perf_event_p4.h.

Enumeration Type Documentation

enum P4_ESCR_EMASKS

Enumerator:

P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK
P4_GEN_ESCR_EMASK

Definition at line 593 of file perf_event_p4.h.

enum P4_EVENT_OPCODES

Enumerator:

P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE
P4_OPCODE

Definition at line 311 of file perf_event_p4.h.

enum P4_EVENTS

Enumerator:

P4_EVENT_TC_DELIVER_MODE
P4_EVENT_BPU_FETCH_REQUEST
P4_EVENT_ITLB_REFERENCE
P4_EVENT_MEMORY_CANCEL
P4_EVENT_MEMORY_COMPLETE
P4_EVENT_LOAD_PORT_REPLAY
P4_EVENT_STORE_PORT_REPLAY
P4_EVENT_MOB_LOAD_REPLAY
P4_EVENT_PAGE_WALK_TYPE
P4_EVENT_BSQ_CACHE_REFERENCE
P4_EVENT_IOQ_ALLOCATION
P4_EVENT_IOQ_ACTIVE_ENTRIES
P4_EVENT_FSB_DATA_ACTIVITY
P4_EVENT_BSQ_ALLOCATION
P4_EVENT_BSQ_ACTIVE_ENTRIES
P4_EVENT_SSE_INPUT_ASSIST
P4_EVENT_PACKED_SP_UOP
P4_EVENT_PACKED_DP_UOP
P4_EVENT_SCALAR_SP_UOP
P4_EVENT_SCALAR_DP_UOP
P4_EVENT_64BIT_MMX_UOP
P4_EVENT_128BIT_MMX_UOP
P4_EVENT_X87_FP_UOP
P4_EVENT_TC_MISC
P4_EVENT_GLOBAL_POWER_EVENTS
P4_EVENT_TC_MS_XFER
P4_EVENT_UOP_QUEUE_WRITES
P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE
P4_EVENT_RETIRED_BRANCH_TYPE
P4_EVENT_RESOURCE_STALL
P4_EVENT_WC_BUFFER
P4_EVENT_B2B_CYCLES
P4_EVENT_BNR
P4_EVENT_SNOOP
P4_EVENT_RESPONSE
P4_EVENT_FRONT_END_EVENT
P4_EVENT_EXECUTION_EVENT
P4_EVENT_REPLAY_EVENT
P4_EVENT_INSTR_RETIRED
P4_EVENT_UOPS_RETIRED
P4_EVENT_UOP_TYPE
P4_EVENT_BRANCH_RETIRED
P4_EVENT_MISPRED_BRANCH_RETIRED
P4_EVENT_X87_ASSIST
P4_EVENT_MACHINE_CLEAR
P4_EVENT_INSTR_COMPLETED

Definition at line 244 of file perf_event_p4.h.

enum P4_PEBS_METRIC

Enumerator:

P4_PEBS_METRIC__none
P4_PEBS_METRIC__1stl_cache_load_miss_retired
P4_PEBS_METRIC__2ndl_cache_load_miss_retired
P4_PEBS_METRIC__dtlb_load_miss_retired
P4_PEBS_METRIC__dtlb_store_miss_retired
P4_PEBS_METRIC__dtlb_all_miss_retired
P4_PEBS_METRIC__tagged_mispred_branch
P4_PEBS_METRIC__mob_load_replay_retired
P4_PEBS_METRIC__split_load_retired
P4_PEBS_METRIC__split_store_retired
P4_PEBS_METRIC__max

Definition at line 804 of file perf_event_p4.h.